Method for producing transistors, in particular selection transistors for non-volatile memory, and corresponding device

Abstract

A MOS transistor with two vertical gates is formed within a substrate zone of a semiconductor substrate doped with a first type of conductivity and separated from a remaining portion of the substrate by two first parallel trenches extending in a first direction. An isolated gate region rests on each flank of the substrate zone and on a portion of the bottom of the corresponding trench to form the two vertical gates. At least one gate connection region electrically connects the two vertical gates. A first buried region located under the substrate zone is doped with a second type of conductivity to form a first conduction electrode of the MOS transistor. A second region doped with the second type of conductivity is located at the surface of the substrate zone to form a second conduction electrode of the MOS transistor.

Claims

1. An integrated circuit, comprising: a plurality of MOS transistors with two vertical gates comprising: a substrate zone of a semiconductor substrate doped with a first type of conductivity and having flanks defined by two first parallel trenches extending in a first direction, an isolated gate region resting on each flank of the substrate zone and on a portion of a bottom of a corresponding trench of said two first parallel trenches to form said two vertical gates, a gate connection region electrically connecting the two vertical gates, a first buried region located under the substrate zone and doped with a second type of conductivity to form a first conduction electrode of each MOS transistor, a plurality of second regions doped with the second type of conductivity and located at a surface of the substrate zone to form second conduction electrodes of the plurality of MOS transistors, and a trench isolation region located at the surface of, and extending into, the substrate zone, wherein each trench isolation region is positioned between two of said second regions in the substrate zone.

2. The integrated circuit according to claim 1, wherein a size of said portion of the bottom of the corresponding trench measured in a second direction that is perpendicular to the first direction is smaller than half of a size of the bottom of the corresponding trench measured in said second direction.

3. The integrated circuit according to claim 1, wherein each trench of said two first parallel trenches has a width greater than a depth.

4. The integrated circuit according to claim 1, wherein said gate connection region comprises a second trench having a depth greater than a width and which extends between the two first parallel trenches in a second direction that is perpendicular to the first direction.

5. The integrated circuit according to claim 1, further comprising a plurality of memory cells superposed over said plurality of MOS transistors with two vertical gates, wherein each MOS transistor is electrically connected to one memory cell and functions as a selection transistor.

6. The integrated circuit according to claim 5, wherein the electrically connected MOS transistor and memory cell form a memory point, and wherein the memory point is one of a plurality of memory points arranged in a matrix of rows extending in the first direction and columns extending in a second direction that is perpendicular to the first direction.

7. The integrated circuit according to claim 6, wherein said isolated gate regions that are located on the flanks facing the respective substrate zones of two selection transistors belonging to one and the same column and to a neighboring row are located in one and the same trench of said two first parallel trenches and are at a distance from one another in the bottom of said same trench.

8. The integrated circuit according to claim 6, wherein gate connection regions electrically connecting the two vertical gates are located on either side of a group of selection transistors belonging to one and the same row.

9. The integrated circuit according to claim 8, wherein said shallow trench isolations separate the second regions of the selection transistors of one and the same group.

10. The integrated circuit according to claim 6, further comprising word lines that extend in the first direction and which are electrically connected by vertical vias to said gate connection regions.

11. The integrated circuit according to claim 5, wherein the memory cell is a resistive memory cell.

12. The integrated circuit according to claim 1, wherein the integrated circuit is a component of an electronic apparatus, said electronic apparatus selected from a group consisting of: a personal computer, a mobile phone, and an on-board computer of an automobile.

13. The integrated circuit according to claim 1, wherein the trench isolation regions penetrate into the substrate zone to a depth which is deeper than a depth of the plurality of second regions, but less than a depth of the two first parallel trenches.

14. A plurality of MOS transistors commonly controlled by two vertical gates, comprising: a semiconductor substrate doped with a first type of conductivity; a first buried region in the semiconductor substrate, said first buried region doped with a second type of conductivity so as to form a first conduction electrode of the plurality of MOS transistors; two first parallel trenches in the semiconductor substrate that extend in a first direction; two second parallel trenches in the semiconductor substrate that extend in a second direction perpendicular to the first direction; wherein the first and second parallel trenches surround a substrate zone having a width and length, wherein the length of the substrate zone extends in the first direction and is greater than the width which extends in the second direction; an isolated region comprising a gate material on each flank of the substrate zone along said length of the substrate zone in said two first parallel trenches, wherein the isolated region comprising the gate material forms the two vertical gates; an electrically conductive connection between the two vertical gates on each flank of the substrate zone along said width of the substrate zone in said two second parallel trenches; and a plurality of second regions doped with the second type of conductivity at a top surface of the substrate zone, wherein the second regions are insulated from each other and arranged in a row along the length of the substrate zone so as to form second conduction electrodes of the plurality of MOS transistors.

15. The plurality of MOS transistors according to claim 14, wherein the two first parallel trenches each have a width in the second direction that is greater than a depth in the depth direction.

16. The plurality of MOS transistors according to claim 14, wherein the two second parallel trenches each have a depth greater than a width in the first direction.

17. The plurality of MOS transistors according to claim 14, further comprising a plurality of memory cells superposed over said plurality of MOS transistors with two vertical gates, wherein each MOS transistor is electrically connected to one memory cell and functions as a selection transistor.

18. The plurality of MOS transistors according to claim 17, wherein the electrically connected MOS transistor and memory cell form a memory point.

19. The plurality of MOS transistors according to claim 14, wherein the integrated circuit is a component of an electronic apparatus, said electronic apparatus selected from a group consisting of: a personal computer, a mobile phone, and an on-board computer of an automobile.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other advantages and features of the invention will become apparent on detailed examination of non-limiting embodiments and implementations and the appended drawings in which:

(2) FIGS. 1 to 10 schematically show various structures obtained during the implementation of a production method according to various embodiments of an electronic circuit and an electronic apparatus.

DETAILED DESCRIPTION

(3) Three directions X, Y, Z form an orthogonal basis for the space, and are indicated in each figure.

(4) FIGS. 1 to 4 show cross-sectional views in a plane (Y, Z) of structures obtained in various steps of an exemplary method for producing a transistor with two vertical gates.

(5) FIG. 1 shows a semiconductor substrate SUB, doped for example of P type, in which a first buried region CTR, doped for example of N type, commonly referred to by the acronym NISO (for n-type isolation region) by those skilled in the art, has been implanted at depth, and in which two first trenches, referred to as gate trenches GT1, GT2, are etched.

(6) The gate trenches GT1, GT2 are formed so as to be identical and extend in parallel in the direction X.

(7) The gate trenches GT1, GT2 are etched through an upper portion of the substrate SUB and at least partially into the buried layer CTR and are wider than they are deep (GTP<GTL), GTP and GTL denoting the depth and the width of a trench, respectively.

(8) The gate trenches GT1, GT2 together delimit a substrate zone ZS that is separated from the rest of the substrate SUB by said gate trenches and the buried layer CTR.

(9) The substrate zone ZS will eventually accommodate an active region of a transistor.

(10) Thus, as will become apparent below, it is particularly the depth of the buried layer CTR that parametrizes the area occupied by a transistor.

(11) FIG. 2 shows the result of a step in which a gate material GM is deposited on the structure described in relation to FIG. 1.

(12) In a conventional manner, a layer of gate oxide OX has been formed beforehand in said gate trenches GT1, GT2, allowing the gate material to be electrically isolated from the substrate and from the first doped region CTR.

(13) The gate material GM may be, for example, vapor-phase-deposited polycrystalline silicon, or a metal deposited according to, for example, a Damascene process.

(14) The deposition forms a layer of gate material GM whose thickness, taken perpendicularly to the surface on which it rests, is substantially constant. Said layer substantially hugs the form of the structure on which it has been deposited, with a tendency to blunt, or round off, the edge of said structure.

(15) Thus, on the surface of the layer of gate material GM, this deposition results in a formation of furrows S1, S2 that are located facing the gate trenches GT1, GT2. Said furrows are substantially as deep as, but narrower than, the gate trenches.

(16) FIG. 3 shows the structure obtained after anisotropically etching GRA, in the vertical direction Z, through the layer of gate material GM and through the previously deposited layer of gate oxide OX to reach the surface of the region CTR.

(17) Conforming to the geometries of said gate trenches GT1, GT2 and said furrows S1, S2, the operation of vertically anisotropically etching GRA the gate material GM leads to the formation of two gate regions that are positioned against the lateral walls of each trench GT1, GT2 and at a distance from one another in the bottom of the trench.

(18) Relative to the orientation of FIG. 3, the gate region positioned against the left lateral wall of the left trench GT1 is denoted by G11, and that against the right lateral wall by G12.

(19) Relative to the orientation of FIG. 3 and in a homologous manner, the gate regions positioned against the left and right lateral walls of the right trench GT2 are denoted by G21 and G22, respectively.

(20) Stated otherwise, a first isolated gate region G12 is formed on the left flank of the substrate zone ZS and on a portion of the bottom of the trench GT1, and a second isolated gate region G21 is formed on the right flank of the substrate zone ZS and on a portion of the bottom of the trench GT2.

(21) This formation may be likened to a typical formation of spacers in a dielectric material surrounding, for example, a gate region of a conventional planar MOS transistor.

(22) Next, as shown in FIG. 4, a second doped region DP is implanted into the surface of the substrate zone ZS.

(23) The structure located between the two gate trenches GT1, GT2 thus obtained forms a transistor TS with two vertical gates G12, G21.

(24) The first doped region CTR located at depth forms, in this instance, the source of the transistor TS and the second doped region DP located on the surface of zone ZS forms, in this instance, the drain of the transistor TS.

(25) The gate regions G12 and G21, positioned on the flanks of the substrate zone ZS, form the two vertical gates of the transistor TS.

(26) Two conduction channels, for a single transistor TS, may be formed in two respective channel regions RC1, RC2, located in the active region between the source and the drain along the flanks on which said vertical gates G12, G21 are located, respectively.

(27) The implantation of the second doped region DP may be, for example, of N type, thus forming an NMOS transistor with two vertical gates.

(28) It is apparent in FIG. 4 that the width, in the direction Y, of a transistor TS depends on the width of a vertical gate, namely substantially the half-width of a gate trench. In turn, the width of a gate trench GTL depends on the depth of the buried layer CTR. Thus, the depth of implantation of the layer CTR is a parameter having an influence on the area occupied by the transistor TS.

(29) However, in particular for reasons related to the control of anisotropic etching and gate material deposition techniques, this production may occupy an area of 2F×2F, where F is the common notation for the smallest dimension achievable using a given technique.

(30) FIGS. 5 and 6 show cross-sectional views in a plane (X, Z) of the structures obtained in steps for producing transistors TS, and, more particularly, producing gate connection regions allowing, in particular, the two gates of a transistor TS to be electrically connected to one another.

(31) FIG. 5 shows a cross-sectional view in the plane (X, Z) corresponding to the plane V-V of FIG. 1. The sectional plane of FIG. 1 corresponds to the plane I-I of FIG. 5.

(32) In the step of etching the first gate trenches GT1, GT2, two second trenches GCT1, GCT2, referred to as gate connection trenches, are also etched in the semiconductor substrate SUB extending through the upper portion of the substrate and at least partially into the buried layer CTR.

(33) The gate connection trenches extend parallel to the direction Y and are deeper than they are wide (GCTP>GCTL), where GCTP is the depth and GCTL the width of a gate connection trench (furthermore, GCTP=GTP).

(34) The second trenches GCT1, GCT2 are etched, in the direction X, on either side of a zone ZS of the substrate corresponding to an active region of a transistor, or corresponding to multiple respective active regions of multiple transistors forming a group.

(35) FIG. 6 shows a cross-sectional view in the plane (X, Z) corresponding to the plane VI-VI of FIG. 3. The sectional plane of FIG. 3 corresponds to the plane of FIG. 6.

(36) The gate material has been deposited then etched in the manners described in relation to FIGS. 2 and 3, forming gate connection regions GC1, GC2 that fill the respective gate connection trenches GCT1, GCT2.

(37) The gate connection regions GC1, GC2 connect the two vertical gates G12, G21 of the transistor TS to one another. In this representation, the gate connection regions GC1, GC2 connect the two vertical gates G12, G21 of the transistors belonging to one and the same group to one another, which group is formed, in this instance, by four transistors, whose gates are consequently shared.

(38) Additionally, between each transistor of a group, shallow trench isolations STI have been formed which individually isolate, in the direction X, the portions of the second doped region DP that individually belong to one transistor of the group.

(39) This method has been described in relation to the formation of a single group of transistors. However, this method may easily be adapted to the production of a single transistor, or of a multiplicity of transistors side-by-side and arranged individually or in groups, for example by reproducing, in the directions X and Y of the memory plane, the configuration described above for producing the selection transistors.

(40) In particular, the unused gate regions G11 and G22 will each serve as transistor gates directly neighboring one another in the Y direction.

(41) The transistors thus formed may advantageously be employed as selection transistors for a memory plane, for example for a resistive non-volatile memory.

(42) FIGS. 7 to 9 show, in various sectional planes, the structure obtained after having formed, within BEOL interconnect layers, a resistive memory cell CEL.sub.i,j superposed over each of the selection transistors.

(43) The structure thus obtained forms a memory plane of a resistive memory, comprising memory points that are arranged in a matrix, in rows in the direction X and in columns in the direction Y. Each memory point comprises a selection transistor and a resistive memory cell.

(44) A resistive memory cell usually comprises a resistive structure, comprising, for example, a phase-change material.

(45) Voltages applied to the terminals of the resistive structure allow the resistivity of the resistive structure to be modified in a permanent and reversible manner and thus a logical datum represented by said resistivity to be stored.

(46) However, in FIGS. 7 to 9, the elements in common with the preceding figures bear the same reference along with the row “i” to which they belong and/or the column “j” to which they belong in subscript. For the sake of clarity, the gate regions previously denoted by G11, G12, G21, G22, are in this instance denoted by G2.sub.i−1, G1.sub.i, G2.sub.i, G1.sub.i+1, respectively.

(47) FIG. 7 shows a cross-sectional view in a plane (Y, Z) of one portion of a memory plane of a non-volatile memory device comprising selection transistors TS.sub.i,j produced via the method described in relation to FIGS. 1 to 6.

(48) The memory cell CEL.sub.i,j is connected to the drain of the selection transistor TS.sub.i,j and to a metallic track, referred to as a bit line BL.sub.i, along the direction Y of the columns of the memory plane through metallic vias made in the BEOL interconnect layers of the integrated circuit.

(49) The production method described above makes it possible, in particular, for the vertical gate G1.sub.i of the transistor TS.sub.i,j to be electrically isolated from the vertical gate G2.sub.i−1 of the transistor TS.sub.i−1,j belonging to the same column j and to an adjacent row i−1, even though said gates G1.sub.i, G2.sub.i−1 have been formed in the same trench.

(50) Likewise, the vertical gate G2.sub.i of the transistor TS.sub.i,j is electrically isolated from the vertical gate G1.sub.i+1 of the transistor TS.sub.i+1,j belonging to the same column j and to an adjacent row i+1, even though said gates G2.sub.i, G1.sub.i+1 have been formed in the same trench.

(51) Thus, each vertical gate of each selection transistor is electrically isolated from the vertical gates of the selection transistor of a memory cell belonging to the same column and to a neighboring row.

(52) Accessing a memory cell by selecting its row may be done via the gates thus formed in trenches extending in the direction X of said rows of the memory plane.

(53) However, it is advantageous to regularly make gate connections to metallic tracks along the direction X, in particular for reasons related to controlling the conductivity of the tracks for accessing a memory cell.

(54) FIG. 8 shows a cross-sectional view in a plane (X, Z) corresponding to the plane VIII-VIII of FIG. 7. The sectional plane of FIG. 7 corresponds to the plane VII-VII of FIG. 8.

(55) The gate connection regions GC1.sub.i, GC2.sub.i also allow contact to be made by respective vertical metallic vias WLV1.sub.i, WLV2.sub.i with a word line WL.sub.i extending over the memory plane in the direction X of the rows.

(56) Said contacts are made regularly, for example by groups of transistors.

(57) One group of transistors comprises, for example, at least four transistors, depending on the conduction conditions preferred by the gate material GM and the implementation requirements of the device thus produced.

(58) FIG. 9 shows a top view of the structure described in relation to FIGS. 7 and 8, their sectional planes corresponding to the planes VII-VII and VIII-VIII, respectively, of FIG. 9.

(59) Each memory point formed by a memory cell CEL.sub.i,j that is superposed over a respective selection transistor TS, is connected to a bit line BL.sub.j and to a word line WL.sub.i.

(60) The bit lines BL.sub.j and the word lines WL.sub.i are formed within the BEOL interconnect layers by metallic tracks extending in the directions of the columns Y and the rows X of the memory plane, respectively, and thus allow a memory point to be selected in the matrix in order to access it.

(61) A memory point is connected to a bit line BL.sub.j by a metallic via making contact with one terminal of the memory cell CEL.sub.i,j the other terminal being connected, also by a metallic via, to the drain of the selection transistor TS.sub.i,j of the memory point.

(62) A memory point is connected to a word line WL.sub.i by metallic vias WLV.sub.i making contact with the gate connection regions GC1.sub.i, GC2.sub.i, which regions are connected to each vertical gate G1.sub.i, G2.sub.i on either side of the selection transistors TS.sub.i,j of one and the same row i.

(63) The selection transistors of the memory plane thus obtained may, in particular, carry twice as much current as a vertical transistor having only one gate and are not subject to the formation of parasitic conduction channels.

(64) The vertical design of the transistors provides substantial savings in terms of the area occupied by each transistor, said area being, in particular, parametrized and adjustable by the depth of implantation of the buried layer.

(65) Additionally, this method is compatible with the methods already in existence, and the structure obtained functions in a similar manner to existing technologies, for example in terms of accessing a memory point by means of row and column decoders.

(66) FIG. 10 shows an electronic apparatus APP, such as a personal computer, a mobile phone, or an on-board computer of an automobile, comprising an integrated circuit CI obtained through the implementation of the method described in relation to FIGS. 1 to 9, equipped, for example, with a resistive non-volatile memory.