Detector circuit

Abstract

A waveform synthesizer comprises a controllable oscillator for generating an oscillator waveform having an oscillator cycle; a reference input for accepting a reference signal having a reference cycle; and a waveform detector coupled to said oscillator and said reference input. The waveform detector is arranged to sample said waveform in response to said reference input and to determine waveform information about said oscillator. The waveform information is operative to adjust said controllable oscillator.

Claims

1. A waveform synthesizer comprising: a controllable oscillator for generating an oscillator waveform having an oscillator cycle; a reference input for accepting a reference signal having a reference cycle; and a waveform detector coupled to said oscillator and said reference input, wherein said waveform detector is arranged to sample said waveform in response to said reference input and to determine waveform information about said oscillator, wherein said waveform information is operative to adjust said controllable oscillator.

2. The waveform synthesizer of claim 1, wherein said waveform detector is capable of detecting any one or more of the amplitude, frequency, phase, and harmonic level of the oscillator waveform.

3. The waveform synthesizer of claim 1, wherein said adjusting comprises changing at least one of a frequency and of a harmonic level of said controllable oscillator.

4. The waveform synthesizer of claim 1, wherein said controllable oscillator is a digitally controlled oscillator (DCO) or a class-F oscillator.

5. The waveform synthesizer of claim 1, wherein said waveform detector is configured to sample the oscillator waveform multiple times per said oscillator cycle.

6. The waveform synthesizer of claim 5, wherein said waveform detector is configured to sample the oscillator waveform multiple times per said reference cycle.

7. The waveform synthesizer of claim 1, wherein said waveform is sampled at a significant edge of said reference signal and at a short time, Delta-t, afterwards, and wherein said Delta-t is less than said oscillator cycle.

8. The waveform synthesizer of claim 1, wherein said waveform is sampled at a significant edge of said reference signal and at multiple times afterwards, and wherein delays between said sampling times are less than said oscillator cycle.

9. The waveform synthesizer of claim 1, further comprising a controller coupled to said waveform detector, said controller arranged to adjust a waveform parameters of said controllable oscillator.

10. The waveform synthesizer of claim 9, wherein said waveform parameter is at least one of a frequency and a harmonic level.

11. The waveform synthesizer of claim 1, wherein said reference cycle is at least ten times longer than said oscillator cycle.

12. The waveform synthesizer of claim 1, wherein said waveform information comprises phase, frequency and amplitude.

13. The waveform synthesizer of claim 1, wherein said waveform information comprises a harmonic level.

14. The waveform synthesizer of claim 1, wherein the waveform synthesizer is arranged to determine both frequency and amplitude information in one period of the oscillator cycle.

15. The waveform synthesizer of claim 1, wherein the waveform synthesizer is arranged to use oversampling and reconstruction of the waveform in the digital domain in order to extract phase error information.

16. The waveform synthesizer of claim 1 comprising a frequency synthesizer, wherein: the oscillator waveform is a variable clock, and said waveform detector samples said reference signal multiple times per reference cycle.

17. A frequency synthesizer comprising: a controllable oscillator for generating a variable clock having an oscillator cycle; a reference input for accepting a reference signal having a reference cycle; and a waveform detector coupled to said oscillator and said reference input, wherein said waveform detector samples said reference signal multiple times per reference cycle.

18. The frequency synthesizer of claim 17, wherein said reference cycle is at least ten times longer than said oscillator cycle.

19. The frequency synthesizer of claim 17, wherein each of said multiple reference events is synchronous to said variable clock.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) The disclosure is described in further detail in the following by way of exemplary embodiments with reference to the accompanying drawings in which:

(2) FIG. 1 is a simplified diagram of a conventional Charge-Pump PLL;

(3) FIG. 2 is a simplified diagram of a conventional all-digital PLL (AD-PLL);

(4) FIG. 3 is theoretical in-band phase noise limit considering the quantization noise from the TDC and reference clock;

(5) FIG. 4 is a simplified diagram of the waveform synthesizer, sometimes referred to as a wave-locked loop, according to one or more embodiments;

(6) FIG. 5 is a simplified diagram of the wave-locked detector of FIG. 4 which are composed of DCO, reference delayed line, sample-and-hold circuits, ADC, and DSP block;

(7) FIG. 6 is a timing diagram of the wave-locked detector of FIGS. 4 and 5;

(8) FIG. 7 is a flow chart of an algorithm for precise phase estimation derived from the wave detector describing FIGS. 4 and 5;

(9) FIG. 8 shows a circuit diagram and waveform information for an example of a harmonic oscillator which may have several harmonic contents in the frequency domain;

(10) FIG. 9 shows alternatives to oversampling for the purpose of waveform detection and estimation: (a) continuous-time integration, (b) continuous-time matching of the oscillator waveform, and (c) continuous time waveform subtraction; and

(11) FIG. 10 shows a frequency synthesizer according to an embodiment of the invention.

DESCRIPTION

(12) FIG. 4 shows a simplified circuit diagram of a waveform synthesizer circuit, sometimes referred to as a wave locked loop (WLL).

(13) The waveform synthesizer comprises a controllable oscillator (Digitally Controlled Oscillator—DCO) for generating a waveform having an oscillator cycle, a reference input for accepting a reference signal having a reference cycle and repetition frequency f.sub.REF, a waveform detector coupled to said oscillator and said reference input, wherein said waveform detector determines waveform information about said oscillator.

(14) As is well known to those skilled in the art, when discussing waveforms a cycle is a complete oscillation. E.g. for a sine wave, it is the complete event starting with a rise from zero energy to a maximum amplitude, its return to zero, the rise to a maximum in the opposite direction, and then its return to zero. The “reference cycle” is the cycle of the reference signal, which is a periodic wave.

(15) In this embodiment, the waveform information is arranged to be used to adjust the controllable oscillator (e.g., digital control for the DCO). In some embodiments, the adjusting comprises changing one or both of the frequency or a harmonic level of the controllable oscillator, which is optionally a digitally controlled oscillator, and can be a class F oscillator.

(16) The waveform detector samples the oscillator signal multiple times per said oscillator cycle (e.g., 4 or 8). In some embodiments, said sampling of multiple times is performed at every reference cycle. Alternatively some reference cycles might be skipped or the sampling of multiple times can be repeated several times within the reference cycle, such as when triggered on both the positive and on the negative edges of the reference clock.

(17) The waveform is sampled at a significant edge (i.e. a rising and/or falling edge) of said reference signal and at a short time afterwards Δt or Delta-t, wherein said Delta-t is less than said oscillator cycle.

(18) The waveform is sampled at a significant edge of said reference signal and at multiple times afterwards, wherein delays between said sampling times are less than said oscillator cycle.

(19) The waveform may be sampled at (and optionally also near, i.e. spaced by Delta-t/multiple times afterwards with delays smaller than the oscillator cycle) more than one significant edge of the same reference cycle.

(20) The reference input is used to sample the oscillator waveform. The sampling may be vectorial, meaning that it is not just a simple sample that is taken, but rather a series of tightly spaced samples

(21) The waveform synthesizer further comprises a controller coupled to said waveform detector, said controller operational for adjusting waveform parameters of said controllable oscillator. As such, the waveform synthesizer may provide a feedback loop, adjusting the controllable oscillator based upon the determined waveform information about the oscillator waveform.

(22) The waveform parameter is frequency in some embodiments, and in some embodiments said waveform parameter is a harmonic level.

(23) The reference cycle is significantly longer than said oscillator cycle in some embodiments. The reference cycle may be tens-to-hundred MHz range, whereas the cycle of the input signal from the oscillator may be in the one-to-tens of GHz range, for example. A ratio of 1:10, 1:100 or 1:1000 in frequency, or therebetween, may therefore be used.

(24) The skilled person will appreciate that such ratios apply for frequency generations using phase-locked loops which generate precise frequency/clock at higher frequency than a commercial clean reference clock from a crystal oscillator (tens-to-hundreds of MHz) which is an off-chip component. The reference cycle is the period of such a reference clock which is used as a reference to compare with more noisy signal from an oscillator on chip (typically running at several GHz or more).

(25) The waveform information is phase information and one or more of a frequency, and an amplitude.

(26) In some embodiments, the waveform information includes a harmonic level.

(27) The roles of the reference and variable clocks can be reversed. The variable clock of high frequency can sample a reference waveform (sinusoidal or sinusoidal with many harmonics which make it more ‘square-ish’) in order to get an information about the difference between variable/reference parameters. It should be appreciated that measuring of absolute parameters, such as frequency and/or phase, is not possible without references. In one embodiment it is the reference that samples the variable quantity; in another embodiment is the variable that samples the reference quantity. What matters in the parameter detection process is the relative reference/variable relationship. In an embodiment, the invention also provides a frequency synthesizer comprising: a) a controllable oscillator for generating a variable clock having an oscillator cycle, b) a reference input for accepting a reference signal having a reference cycle, c) a waveform detector coupled to said oscillator and said reference input, wherein said waveform detector samples said reference signal multiple times per reference cycle.

(28) The reference cycle is significantly longer than said oscillator cycle in some embodiments, for example 10, 100 or 1000 times longer, or a value therebetween.

(29) Each of said multiple sampling events is synchronous to said variable clock in some embodiments.

(30) In one embodiment, the WLL receives a reference frequency, generally from a reference oscillator, such as a crystal oscillator (sometimes referred to as a XTAL), which is provided to a detector circuit, sometimes described as a wave detector, which will be described in further detail below with respect to FIG. 5. The signal generated by the reference oscillator may be referred to as a reference signal. The waveform detector provides a reconstructed waveform and phase (and/or frequency) information to a digital loop filter. The loop filter determines the dynamics of the loop based on the reconstructed waveform and phase and/or frequency information and supplies that information to a digitally controlled oscillator (DCO). The output of the DCO is then fed back to the wave detector and also used as desired.

(31) The simplified schematic of the wave detector is shown in FIG. 5. Firstly, the output waveform from a Digitally-Controlled Oscillator (DCO), which is in GHz frequency range, is sampled into a voltage domain by a reference clock, which is further converted into digital domain by an analog-to-digital converter (ADC). Note that the sampling and quantization process can be combined. Through a set of M delayed reference clocks which can be implemented using a buffer or inverter chain, the waveform is further sampled by the ADC's and converted into M sets of digital samples. It can be appreciated that although multiple ADC's or samplers are shown for sampling the signals, specifically one ADC per branch, a single, or group of samplers may be used for each or several branches, for example one group of samplers for the DCO signal and another group for the reference signal.

(32) Unlike conventional digital sub-sampling PLL, where only a single sample point per reference event is used to measure the phase information which put the constraint on the linearity of the conversion function and resolution of an ADC, in this invention, after M digital samples in the sample-and-hold period are captured, they are processed in the digital signal processing blocks. The digital signal processing approximates the phase through the reconstructed waveform which is much more robust over the noise or nonlinearity associated in the input waveforms. In the next section, the method of amplitude and phase approximation from the digital samples will be explained.

(33) As mentioned earlier, the input waveform is compared with a model waveform which can be written as:
x=A*sin(ωn+φ)  (2)
where A is amplitude of the sinusoidal waveform, ω is the angular (or radial) oscillation frequency of the input waveform, n is the sample time index, and φ is the phase. This equation can be rewritten using a superposition of sine and cosine function as follows:
x=a.sub.1.Math.sin(ωn)+a.sub.2.Math.cos(ωn)  (3)

(34) Eq. 2 can be represented in the matrix form as:
H.Math.a=x  (4)

(35) Where x=[x.sub.0, x.sub.1, . . . x.sub.N-1]; column vector of input sinusoid, a=[a.sub.1, a.sub.2]; column vector of fit parameters and H can be expressed as:

(36) $\begin{array}{cc}H=\left(\begin{array}{cc}\sin \left(\omega .Math.0\right)& \cos \left(\omega .Math.0\right)\\ \sin \left(\omega .Math.1\right)& \cos \left(\omega .Math.1\right)\\ \mathrm{.Math.}& \mathrm{.Math.}\\ \sin \left(\omega .Math.\left(N-1\right)\right)& \cos \left(\omega .Math.\left(N-1\right)\right)\end{array}\right)& \left(5\right)\end{array}$

(37) By multiplying H.sup.T on both sides of Eq. (4), a can be rewritten as follows:
a=(H.sup.T.Math.H).sup.−1.Math.H.sup.T.Math.x  (6)

(38) Eq. (3) forms N linear equations. By solving this set of linear equations, we can find the fit parameters (a.sub.0, . . . a.sub.n). Therefore, estimation of the amplitude and phase can be derived as follows:

(39) $\begin{array}{cc}\phi ={\tan }^{-1}\left(\frac{a_2}{a_1}\right)& \left(7\right)\\ \mathrm{amplitude}=\mathrm{norm}\left(a\right)& \left(8\right)\end{array}$
where a.sub.1=A.Math.cos(φ); a.sub.2=A.Math.sin(φ). From Eq. (7), phase information can be estimated after multiplying the sampled data by the H matrix as shown in Eq. (6). In the presence of noise the sinusoidal signal can be represented as follows:
y[n]=x[n]+w[n]  (9)
where x[n] is signal with n samples and w[n] is associated noise. The estimation can be expressed as follows:
â=a+e  (10)
where e is estimation error due to noise which is expressed as (H.sup.T.Math.H).sup.−1.Math.H.sup.T.Math.w. By assuming the noise w is white then its mean is zero with a variance of σ.sup.2. The error covariance can be expressed as:
E{ee.sup.t}=σ.sup.2.Math.I.Math.(H.sup.T.Math.H).sup.−1  (11)

(40) If the samples are separated by integer multiples of

(41) $\frac{2\pi }{N}$
radians, or in other words

(42) $\frac{T_{\mathrm{DCO}}}{N}.$
Then, the column of H are orthogonal and

(43) $\left(H^T.Math.H\right)=\frac{N}{2}.Math.I.$
The error variance now can be expressed as:

(44) $\begin{array}{cc}E\left\{{\mathrm{ee}}^t\right\}=\frac{2{\sigma }^2}{N}.Math.I& \left(12\right)\end{array}$

(45) From Eq. (12), it can be observed that increasing number of samples (N) or increasing ADC resolution decreases error variance.

(46) From the above calculation and analysis, the simplified diagram of the digital signal processing block to estimate the phase in Eq. (7) requires the calculation for a1[k] and a2[k], which are summarized in FIG. 7. The result is processed in Eq. (7) to achieve a fine phase estimation. According to simulation, using 4 samples with 4-bit ADC, phase error could be less than 1 degree which is equivalent to a time resolution of approximately 0.6 ps for 5 GHz input waveform. This equates to an in-band phase noise of −122 dBc/Hz, which is close to the theoretical limit of in-band phase noise contributed by the use of a crystal oscillator as a reference clock.

(47) FIGS. 4-7 emphasize the detection of phase, frequency and amplitude; i.e. the waveform information detected is not just phase.

(48) FIG. 8 shows an example of waveform and harmonic contents of class-F oscillators. All of the waveform information depicted in the two graphs is determined by the waveform synthesizer in the embodiment being described (i.e. harmonic level including the harmonic's relative phase, amplitude, frequency, etc.).

(49) In the example embodiments described above, oversampling is used to determine waveform information. However, the invention is not intended to be limited to this and FIG. 9 illustrates examples of alternative techniques that may be used instead of oversampling. Continuous-time techniques, which are widely used in communication systems, can be used to reconstruct the waveform with its parameters. The techniques shown in FIG. 9 are: (a) continuous-time integration; (b) continuous-time matching of the oscillator waveform; and (c) continuous time waveform subtraction.

(50) The skilled person will appreciate that these options are provided by way of example only, and that any suitable technique may be used.

(51) The technique described above for sampling an oscillator waveform may also be applied to the reference signal. FIG. 10 illustrates a frequency synthesizer arranged to implement the invention in this fashion; the frequency synthesizer may or may not be part of a waveform synthesizer. The technique described herein can be used to oversample the reference waveform of a crystal oscillator. This allows a user to regenerate multiple reference events. The multiple reference events can then be used in the frequency synthesizer as a much faster reference clock.

(52) According to an aspect of the invention, there is provided a detector circuit for a frequency synthesizer, said circuit comprising: an oscillator configured to generate an input signal; an input configured to receive a reference signal having a reference cycle; and a sampler configured to sample multiple reference events of the input signal per reference cycle.

(53) Optionally, the detector circuit further comprises a digital signal processor configured to determine phase information about the input signal from the multiple reference events.

(54) The digital signal processor is optionally configured to generate a reconstructed waveform representative of the input signal from the information.

(55) The digital signal processor optionally determines the phase information of the input signal from the reconstructed waveform.

(56) The digital signal processor optionally determines harmonic information of the input signal from the reconstructed waveform.

(57) The digital signal processor optionally extracts amplitude information of the input signal from the sample multiple reference events.

(58) The reconstructed waveform is optionally a digital waveform, and further optionally the digital waveform is reconstructed in the digital domain.

(59) Optionally the reconstructed waveform is compared against a model waveform.

(60) Optionally the sampler extracts 2, 3, 4, 5, 6, 7, 8, 9 or more sample multiple reference events per reference cycle.

(61) Optionally the oscillator is a digitally controlled oscillator.

(62) Optionally the reference signal is substantially sinusoidal.

(63) Optionally the reference signal is substantially saw toothed.

(64) Optionally the reference signal is an undefined signal, and further optionally the reference signal is a time varying signal, such as an audio signal, such as speech.

(65) Optionally the sampler samples every reference event.

(66) Optionally the reference event is one of zero-point edges, rising edges, falling edges, peaks and troughs.

(67) Optionally the sampler is an analog to digital converter.

(68) Optionally the sampler is an array of samplers.

(69) According to another aspect, the invention provides a method of estimating the phase of an input signal, said method comprising the steps of: generating an input signal using a detector circuit according to any preceding claim; receiving a reference signal having a reference cycle to the input; and oversampling the input signal to extract multiple reference events per reference cycle.

(70) Optionally the method further comprises the step of generating a reconstructed signal from the multiple reference events.

(71) Optionally the reconstructed signal is a digital signal generated in the digital domain.

(72) Optionally the method further comprises the step of comparing the reconstructed signal to the input signal.

(73) Optionally the method further comprises the step of determining wavesignal information of the input signal from the comparison.

(74) Optionally the wavesignal information is one or more of phase information, harmonics or amplitude of the input signal. In particular, the wavesignal information may be more than just phase information, i.e. it may include amplitude information in addition to phase information and/or harmonics.

(75) According to another aspect, the invention provides a frequency synthesizer circuit comprising: a detector circuit according to the above-mentioned aspect; a digital loop filter; a reference oscillator for supplying the reference signal; and a feedback mechanism for correcting the phase of the input signal based on the phase information and the reference signal.