Active quadrature circuits for high frequency applications

Abstract

An active quadrature generation circuit configured to provide an in-phase output signal and a quadrature output signal based on an input signal and a method of fabricating the active quadrature generation circuit on an integrated circuit are described. The circuit includes an input node to receive the input signal and a first transistor including a collector connected to a power supply pin. The circuit also includes a second transistor including a base connected to the power supply pin, the second transistor differing in size from the first transistor by a factor of K, wherein the in-phase output signal and the quadrature output signal are generated based on an inherent phase difference of 90 degrees between a current at a collector of the first transistor and a current at a base of the second transistor.

Claims

1. An active quadrature generation circuit configured to provide an in-phase output signal and a quadrature output signal based on an input signal, the circuit comprising: an input node configured to receive the input signal; a first transistor including a collector connected to a power supply pin; and a second transistor including a base connected to the power supply pin, the second transistor differing in size from the first transistor by a factor of K, wherein the in-phase output signal and the quadrature output signal are generated based on an inherent phase difference of 90 degrees between a current at a collector of the first transistor and a current at a base of the second transistor.

2. The circuit according to claim 1, wherein the input signal is a radio frequency (RF) signal.

3. The circuit according to claim 1, wherein the input node is a differential input node and the input signal is a differential signal.

4. The circuit according to claim 3, wherein a pair of the first transistor and the second transistor is associated with each side of the differential input node.

5. The circuit according to claim 3, wherein the in-phase output signal and the quadrature output signal are both differential signals.

6. The circuit according to claim 1, wherein an amplitude of the in-phase output signal and an amplitude of the quadrature output signal are balanced at a frequency of interest.

7. The circuit according to claim 6, wherein the frequency of interest is between 76 gigahertz (GHz) and 81 GHz.

8. The circuit according to claim 7, wherein the frequency of interest is 77 GHz.

9. The circuit according to claim 6, wherein the frequency of interest is between 22 gigahertz (GHz) and 29 GHz.

10. The circuit according to claim 9, wherein the frequency of interest is 24 GHz.

11. A method of fabricating an active quadrature generation circuit on an integrated circuit, the method comprising: arranging an input node to receive the input signal; arranging a first transistor such that a collector of the first transistor is connected to a power supply pin of the integrated circuit; arranging a second transistor such that a base of the second transistor is connected to the power supply pin; sizing the second transistor to differ by a factor of K from a size of the first transistor; and generating an in-phase output signal and a quadrature output signal from the input signal based on an inherent phase difference of 90 degrees between a current at the collector of the first transistor and a current at the base of the second transistor.

12. The method according to claim 11, wherein the arranging the input node to receive the input signal includes arranging a differential input node to receive a differential signal.

13. The method according to claim 12, further comprising arranging a pair of the first transistor and the second transistor associated with each side of the differential input node.

14. The method according to claim 12, wherein the generating the in-phase output signal and the quadrature output signal includes generating differential signals.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other features, advantages and details appear, by way of example only, in the following detailed description of embodiments, the detailed description referring to the drawings in which:

(2) FIG. 1 is a circuit diagram of a single-end, active, internally matched, quadrature generation circuit according to an embodiment; and

(3) FIG. 2 is a circuit diagram of a differential quadrature generation circuit according to an embodiment.

DESCRIPTION OF THE EMBODIMENTS

(4) The following description is merely exemplary in nature and is not intended to limit the present disclosure, its application or uses. It should be understood that throughout the drawings, corresponding reference numerals indicate like or corresponding parts and features.

(5) Embodiments discussed herein relate to active quadrature generation circuits that consume less power than traditional quadrature generation circuits that use active elements. The quadrature generation circuits according to the embodiments detailed herein rely on inherent characteristics of transistors for quadrature generation.

(6) In accordance with an exemplary embodiment of the invention, a single-end, active, internally matched, quadrature generation circuit 100 is shown in FIG. 1. A voltage source Vs 10 and source impedance Rs 15 present a radio frequency (RF) input 17 at node 1, at the input to the quadrature generation circuit 100. The quadrature generation circuit 100, according to the embodiment shown in FIG. 1, includes a capacitor Ccc1 20 to isolate the dc bias at Vs 10. The two bipolar junction transistors (BJTs) Qmain 30, Qaux 50 that are part of the quadrature generation circuit 100 are of different sizes. Specifically, a scaling factor K is used to change the size of Qaux 50 from that of Qmain 30. That is, K is the size ration between transistors Qmain 30 and Qaux 50. The tail current source I.sub.EE 25 at the emitter of Qmain 30 and Qaux 50 provides the DC bias current of Qmain 30 and Qaux 50. The collector supply voltage (Vcc) 40 is a power supply pin of the integrated circuit 101 on which the quadrature generation circuit 100 is formed. When an RF input 17 is applied to the quadrature generation circuit 100, a corresponding RF current IRC 37 is generated and flows through collector resistor (R.sub.C) 35 to the collector of the first transistor Qmain 30 at node 2. The other RF corresponding current I.sub.RB 57 is also generated and flows through base resistor (RB) 55 to the base of the second transistor Qaux 57 at node 3. The phase difference between I.sub.RC 37 and I.sub.RB 57 is 90 degrees at higher frequencies (on the order of gigahertz (GHz) to several ten GHz). Resistor Rdum 45 is at the collector of Qaux 50. Rdum 45 may be adjusted to adjust the collector voltage of Qaux 50 (to match the biasing of Qmain 30 and Qaux 50). At the collector of Qmain 30 (at node 2) and at the base of Qaux 50 (at node 3), a dc-decoupled capacitor C.sub.CC2 60 is arranged in series with a load resistor R.sub.L 65. The in-phase output signal Iout 70 is across the R.sub.L 65 associated with node 2, and the quadrature phase output signal Qout 75 (90 degrees out of phase with Iout 70) is across the R.sub.L 65 associated with node 3.

(7) The phase difference between the in-phase and quadrature output signals, Iout 70 and Qout 75, is ensured based on the transistor inherent characteristics of Qmain 30 and Qaux 50. When the (normalized) current gain between nodes 1 and 3 (RF input node and the node at the collector of Qmain 30) and the (normalized) current gain between nodes 1 and 2 (RF input node and the node at the base of Qaux 50) is equal or within 3 decibels (dB) of each other, then the output phase difference (phase difference between Iout 70 and Qout 75) is at or about 90 degrees. Perfect amplitude balance (|I.sub.RC|=|I.sub.RB|) occurs when the frequency f is given by:

(8) $\begin{array}{cc}f\approx \frac{f_T}{\left(K+1\right)}& \left[\mathrm{EQ}.1\right]\end{array}$
At higher frequencies, when f>>fT/β (where fT is cutoff frequency of the transistor (on the order of 100 GHz, for example), and β is the dc gain current or collector current/base current), the ratio of I.sub.RC 37 to I.sub.RB 57 is given by:

(9) $\begin{array}{cc}\frac{I_{RC}}{I_{RB}}\approx -j\frac{f_T}{f}\times \frac{1}{\left(K+1\right)}& \left[\mathrm{EQ}.2\right]\end{array}$
As EQ. 2 illustrates, when EQ. 1 is true, then
I.sub.RC≈−jI.sub.RB  [EQ. 3]
That is, I.sub.RC 37 and I.sub.RB 57 are 90 degrees apart in phase. Further, the quadrature (90 degree) relationship is achieved by the inherent characteristics between the collector and base alternating current (AC) (I.sub.RC 37 to I.sub.RB 57). To achieve a wide-band matching, the resistor values are selected such that:

(10) $\begin{array}{cc}{R}_s\approx \frac{1}{\left(g_{m,\mathrm{Qmain}}+g_{m,Q\mathrm{aux}}\right)}& \left[\mathrm{EQ}.4\right]\end{array}$
In EQ. 4, gm is the transconductance of the transistors Qmain 30 and Qaux 50. In order to match the load impedance, R.sub.L 65, R.sub.C 35, and R.sub.B 55 can be chosen as:
R.sub.C≈R.sub.L  [EQ. 5]
R.sub.B≈R.sub.L  [EQ. 6]

(11) In accordance with another exemplary embodiment of the invention, a differential, active, internally matched, quadrature generation circuit 200 is shown in FIG. 2. The differential voltage Vin+ 210 and Vin− 220 is converted to differential current. According to the current embodiment, Iout 280 and Qout 290 are differential outputs. Each side (p and m) of the differential quadrature generation circuit 200 includes three transistors. On the p side, these are Qinp 217, Qmainp 240, and Quxp 245. On them side, these are Qinm 218, Qmainm 250, and Qauxm 255. All of the transistors may be BJTs. On each side, a scaling factor is used to change the size of the auxiliary transistor from that of the main transistor. That is, a scaling factor K is used to change the size of Qauxp 245 from that of Qmainp 240 and the scaling factor K is also used to change the size of Qauxm 255 from that of Qmainm 250. The capacitors Ccc1 215 isolate the dc bias at the voltages Vin+ 210 and Vin− 220. At the base of Qinp 217 and Qinm 218, parallel resistors R.sub.BB 225 are in series with voltage source V.sub.BB 235 to provide the base bias voltages. The emitters of Qinp 217 and Qinm 218 connect to a current source I.sub.EE 230. The collector supply voltage (Vcc) 270 is a power supply pin of the integrated circuit 101 on which the quadrature generation circuit 200 is formed. As a comparison of FIG. 1 with FIG. 2 indicates, R.sub.C 35 and R.sub.B 55 are replaced with inductors L.sub.C 260 and L.sub.B 275. The inductors increase gain with less energy consumption at higher frequencies (e.g., 77 GHz). The resistor Rdum 265 is at the collector of each of Qauxp 245 and Qauxm 255. There is an inherent phase difference of 90 degrees between the collector of Qmainp 240 (associated with Iout+ 280) and the base of Qauxp 245 (associated with Qout+ 290). There is also an inherent phase difference of 90 degrees between the collector of Qmainm 250 (associated with Iout− 280) and the base of Qauxm 255 (associated with Qout− 290). As a result, a phase difference of 90 degrees is ensured between the in-phase and quadrature output signals, Iout 280 and Qout 290.

(12) Some common features of the circuits according to the embodiments discussed with reference to FIG. 1 and FIG. 2 include temperature insensitivity. Other features, in addition to the 90 degree phase difference between the in-phase and quadrature outputs based on the inherent characteristics of the transistors, include amplitude balance near the frequency of interest (e.g., 24 GHz, 77 GHz, 22-29 GHz, 76-81 GHz). That is, the amplitude of the in-phase and quadrature outputs is nearly equal. In addition, both circuits provide good input and output matching at high frequencies. This prevents bounce-back of the RF input, for example. Also, the differential topology shown in FIG. 2 provides immunity to common-mode interferences. While the active circuits shown in FIG. 1 and FIG. 2 avoid the accuracy issues associated with passive quadrature circuits, they also avoid the high power consumption associated with traditional active element devices that include a divider and latch, for example.

(13) While the invention has been described with reference to exemplary embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiments disclosed, but that the invention will include all embodiments falling within the scope of the application.