Low-power-consumption high-speed zero-current switch

Abstract

A low-power-consumption high-speed zero-current switch includes a delay controller, a driving stage and a power transistor MN, wherein: an input of the delay controller is connected with an external clock CLK, an output of the delay controller is connected with an input of the driving stage, and an output of the driving stage is connected with a gate of the power transistor MN; the delay controller includes a gate signal generator, a sampling circuit and a current controller, and three of which form a negative feedback loop for stabilizing the turn-on voltage V.sub.ON and the turn-off voltage V.sub.D to 0, so that when the power transistor MN is turned on or off, the source-drain voltage thereof is 0. The present invention no longer uses a high-power-consumption high-speed comparator, but uses a low-power-consumption delay controller to generate turn-on and turn-off signals of the power transistor.

Claims

1. A low-power-consumption high-speed zero-current switch, which comprises a delay controller, a driving stage and a power transistor (MN), wherein: an input of the delay controller is connected with an external clock (CLK), an output of the delay controller is connected with an input of the driving stage, and an output of the driving stage is connected with a gate of the power transistor (MN); the delay controller comprises a gate signal generator, a sampling circuit and a current controller; the gate signal generator is configured to use the external clock (CLK) and two currents (I.sub.ON) and (I.sub.D) controlled by the current controller to generate a gate signal (V.sub.GN) of the power transistor (MN) required by the zero-current switch; the sampling circuit comprises a sampling logic unit and a switched capacitor sampling unit; the sampling logic unit is configured to utilize the external clock (CLK) and the gate signal (V.sub.GN) of the power transistor (MN) to control the switched capacitor sampling unit for sampling source-drain voltages of the zero-current switch at turn-on and turn-off moments thereof, and then transmit a sampled turn-on voltage (V.sub.ON) and a sampled turn-off voltage (V.sub.D) to the current controller; the current controller is configured to utilize the turn-on voltage (V.sub.ON) and the turn-off voltage (V.sub.D) to adaptively adjust the two currents (I.sub.ON) and (I.sub.D), respectively; the gate signal generator, the sampling circuit and the current controller form a negative feedback loop for stabilizing the turn-on voltage (V.sub.ON) and the turn-off voltage (V.sub.D) to 0, so that when the power transistor (MN) is turned on or off, a source-drain voltage thereof is 0.

2. The low-power-consumption high-speed zero-current switch, as recited in claim 1, wherein: the gate signal generator comprises two cascaded current control delay line (CCDL) units, two single pulse generators and an SR (set-reset) latch; the two cascaded current control delay line (CCDL) units are respectively a first CCDL unit and a second CCDL unit; an input of the first CCDL unit is connected with the external clock (CLK), a current control terminal of the first CCDL unit is connected with the current (I.sub.ON), an output of the first CCDL unit is connected with an input of the second CCDL unit and an input of a first single pulse generator; a current control terminal of the second CCDL unit is connected with the current (I.sub.D), an output of the second CCDL unit is connected with an input of the second single pulse generator; the first single pulse generator and the second single pulse generator respectively output two pulse signals (P.sub.RA) and (P.sub.FA) to two inputs of the SR latch, and an output of the SR latch outputs the gate signal (V.sub.GN) of the power transistor (MN).

3. The low-power-consumption high-speed zero-current switch, as recited in claim 2, wherein: the first CCDL unit is controlled by the current (I.sub.ON) to adjust a turn-on time of the gate signal; the second CCDL unit is controlled by the current (I.sub.D) to adjust a turn-off time of the gate signal.

4. The low-power-consumption high-speed zero-current switch, as recited in claim 3, wherein: both of the first and second single pulse generators are configured to restore the gate signal after being delayed to a short pulse, and transmit the short pulse to the SR latch for generating the required gate signal (V.sub.GN).

5. The low-power-consumption high-speed zero-current switch, as recited in claim 1, wherein: the current controller comprises a level shifting circuit, a first comparator (CMP1), a second comparator (CMP2), a logic control circuit, a current-switching integrator, a voltage to current converter and a current subtractor connected with each other in sequence, wherein: the two voltages (V.sub.ON) and (V.sub.D) are respectively introduced to two inputs of the level shifting circuit, and two outputs of the current subtractor respectively output the two currents (I.sub.ON) and (I.sub.D).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a structurally schematic view of a zero-current switch provided by the present invention.

(2) FIG. 2 is a structurally schematic view of a gate signal generator of the zero-current switch provided by the present invention.

(3) FIG. 3 is a waveform diagram of key nodes in the gate signal generator.

(4) FIG. 4 is a structurally schematic view of any one of the first and second CCDL units of the gate signal generator.

(5) FIG. 5 is a waveform diagram of key nodes in any one of the first and second CCDL units.

(6) FIG. 6 is a structurally schematic view of a current controller of the zero-current switch provided by the present invention.

(7) FIG. 7 is a waveform diagram of key nodes in the current controller.

(8) FIG. 8 is a topologically schematic view of a switched capacitor sampling unit of the zero-current switch provided by the present invention.

(9) FIG. 9 is a Montecarlo simulation waveform when a source (S) of the zero-current switch is connected with ground.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

(10) Referring to FIG. 1, a low-power-consumption high-speed zero-current switch according to a preferred embodiment of the present invention is illustrated, which is able to produce turn-on and turn-off signals of a power transistor through a delay circuit; and control a delay through a negative feedback circuit to ensure that zero-current characteristics when the power transistor is turned on and off.

(11) FIG. 1 is a structurally schematic view of the low-power-consumption high-speed zero-current switch according to the preferred embodiment of the present invention, which comprises a delay controller, a driving stage and a power transistor MN. The power transistor MN is a main component of the low-power-consumption high-speed zero-current switch. Since the power transistor has a large gate parasitic capacitance, the delay controller is unable to be directly driven; and the driving stage is able to enhance a driving capability of signals, so that after an output signal of an active circuit passes through the driving stage, the power transistor with larger gate parasitic capacitance is driven. The delay controller generates a power-stage gate signal by means of delay control, and controls and maintains the stability of the gate signal at rising and falling times through negative feedback.

(12) FIG. 1 is a structurally schematic view of the zero-current switch of the present invention, which comprises the delay controller, the driving stage and the power transistor MN. An input of the delay controller is connected with an external clock CLK, an output of the delay controller is connected with an input of the driving stage, and an output of the driving stage is connected with a gate of the power transistor MN.

(13) The delay controller comprises a gate signal generator, a sampling circuit and a current controller.

(14) The gate signal generator uses the external clock CLK and two currents I.sub.ON and I.sub.D controlled by the current controller to generate a gate signal V.sub.GN of the power transistor MN required by the zero-current switch. The sampling circuit comprises a sampling logic unit and a switched capacitor sampling unit. The sampling logic unit utilizes the external clock CLK and the gate signal V.sub.GN of the power transistor MN to control the switched capacitor sampling unit for sampling a voltage difference between a source (S) and a drain (D) of the zero-current switch at turn-on and turn-off moments thereof, and then transmits a sampled turn-on voltage V.sub.ON and a sampled turn-off voltage V.sub.D to the current controller. The current controller utilizes the turn-on voltage V.sub.ON and the turn-off voltage V.sub.D to adaptively adjust the two currents I.sub.ON and I.sub.D, respectively. The gate signal generator, the sampling circuit and the current controller form a negative feedback loop for stabilizing the turn-on voltage V.sub.ON and the turn-off voltage V.sub.D to 0, so that when the power transistor MN is turned on or off, the source-drain voltage thereof is 0, thereby achieving zero-current turn-on and turn-off.

(15) FIG. 2 is a structurally schematic view of the gate signal generator, which comprises two cascaded current control delay line (CCDL) units, two single pulse generators and an SR (set-reset) latch. An input of a first current control delay line (CCDL) unit is connected with CLK, a current control terminal of the first CCDL unit is connected with I.sub.ON, an output of the first CCDL unit is connected with an input of a second CCDL unit and an input of a first single pulse generator; a current control terminal of the second CCDL unit is connected with I.sub.D, an output of the second CCDL unit is connected with an input of the second single pulse generator; the first single pulse generator and the second single pulse generator respectively output two pulse signals P.sub.RA and P.sub.FA to two inputs of the SR latch, and an output of the SR latch outputs the gate signal V.sub.GN of the power transistor MN.

(16) The first CCDL unit is controlled by I.sub.ON to adjust the turn-on time of the gate signal; the second CCDL unit is controlled by I.sub.D to adjust the turn-off time of the gate signal, as shown in FIG. 3. Both of the first and second single pulse generators restore a delayed signal to a short pulse, and transmit the short pulse to the SR latch for generating the required gate signal V.sub.GN.

(17) FIG. 4 is a structurally schematic view of any one of the first and second CCDL units of the gate signal generator. MN1 and MN2 form a current mirror. MN2 mirrors the current I.sub.ON or I.sub.D which passes through MN1. The first and second CCDL units control a discharge rate of a capacitor CP through controlling the current I.sub.ON or I.sub.D. When the voltage on the capacitor drops to a certain level, the output voltage OUT flips. Different currents mean different discharge rates and different delay times, as shown in FIG. 5.

(18) FIG. 6 is a structurally schematic view of the current controller, which comprises a level shifting circuit, a first comparator CMP1, a second comparator CMP2, a logic control circuit, a current-switching integrator, a voltage to current converter and a current subtractor connected with each other in sequence. The level shifting circuit converts a sampled voltage V.sub.ON (V.sub.D) into a higher voltage V.sub.ON S (V.sub.D_S) and provides two reference voltages V.sub.ON_H and V.sub.ON_L (V.sub.D_H and V.sub.D_L). A voltage window ranges from V.sub.OS− to 0 is introduced equivalently at an input node of the level shifting circuit through V.sub.ON_H and V.sub.ON_L. The comparators CMP1 and CMP2 respectively compare V.sub.ON_S with V.sub.ON_H and V.sub.ON_L, which is equivalent to comparing V.sub.ON with V.sub.OS− and 0, respectively. Moreover, the comparators CMP1 and CMP2 output digital codes for controlling turning on and turning off switches S.sub.inj and S.sub.ext of the current-switching integrator, thereby adjusting V.sub.R_ON. Through the voltage to current converter and the current subtractor, the voltage change of V.sub.R_ON is able to adjust the current I.sub.ON. FIG. 7 is a waveform diagram of key nodes in the current controller.

(19) The zero-current switch provided by the present invention generates the gate signal of the power transistor through the delay controlled by the current, thereby avoiding the use of a high-power-consumption comparator. Due to the successive approximation negative feedback technique, the zero-current switch based on the delay controller is able to achieve a higher switching speed at lower power consumption. The low-power-consumption high-speed zero-current switch facilitates improving performances of other circuits which adopt this switch.

(20) In addition, the negative feedback mechanism inside the delay controller enables the active rectifier to have a good resistance to process variations, and has strong process robustness, as shown in FIG. 9.