DETECTOR CIRCUIT AND SYSTEM FOR GALVANICALLY ISOLATED TRANSMISSION OF DIGITAL SIGNALS

Abstract

A detector circuit for galvanically isolated transmission of digital signals. The detector circuit includes two differential signal inputs, one input common-mode voltage connection, one alternating voltage coupling, and one differential stage. The detector circuit also includes one operating voltage connection, one operating ground connection, one signal output, one bias current connection, and one rectifier stage. The alternating current coupling includes two capacitors and two resistors. The differential stage includes a first n-channel transistor and a second n-channel transistor. The bias current connection is connected to the differential stage via a third n-channel transistor. The bias current connection is connected to the rectifier stage via a fourth n-channel transistor and a fifth n-channel transistor. The rectifier stage includes five p-channel transistors.

Claims

1-6 (canceled)

7. A detector circuit for galvanically isolated transmission of digital signals, comprising: two differential signal inputs; an input common-mode voltage connection; an alternating voltage coupling; a differential stage; an operating voltage connection; an operating ground connection; a signal output; a bias current connection; and a rectifier stage; wherein the alternating voltage coupling includes two capacitors and two resistors, and one of the capacitors, in each case, being connected to a first side at one of the differential signal inputs, and two sides of the two capacitors each being connected to the differential stage and to the input common-mode voltage connection via one of the resistors; wherein the differential stage including a first n-channel transistor and a second n-channel transistor, and the first n-channel transitory and the second n-channel transistor each being connected to one of the resistors of the alternating voltage coupling and one of the capacitors of the alternating voltage coupling; wherein the bias current connection is connected to the differential stage via a third n-channel transistor, and the bias current connection being connected to the rectifier stage via a fourth n-channel transistor and a fifth n-channel transistor; wherein the operating ground connection is connected to the third n-channel transistor, the fourth n-channel transistor, and the fifth n-channel transistor; wherein the rectifier stage includes five p-channel transistors, the first n-channel transistor being connected to a first one of the p-channel transistors, a fourth one of the p-channel transistors and a fifth one of the p-channel transistors, and the second n-channel transistor being connected to a second one of the p-channel transistors, the fourth one of the p-channel transistors and the fifth one of the p-channel transistors; wherein the operating voltage connection is connected to the first one of the p-channel transistors, the second one of the p-channel transistors, and a third one of the p-channel transistors; and wherein the signal output is connected to the fourth one of the p-channel transistors and the fifth one of the p-channel transistors.

8. The detector circuit as recited in claim 7, wherein the first one of the p-channel transistors and the second one of the p-channel transistors are configured in such a way that they may supply higher currents than may be taken up by the first n-channel transistor and the second n-channel transistor when no differential signal is present at the differential signal inputs.

9. The detector circuit as recited in claim 7, wherein the first n-channel transistor and the second n-channel transistor are configured in such a way that they may take up higher currents than may be supplied by the first one of the p-channel transistors and the second one of the p-channel transistors when a high frequency differential signal having a sufficiently high amplitude is present at the differential signal inputs.

10. The detector circuit as recited in claim 7, wherein a drain current from the third n-channel transistor is conducted all the way through the first n-channel transistor or the second n-channel transistor when a high frequency differential signal having a sufficiently high amplitude is present at the differential signal inputs.

11. The detector circuit as recited in claim 10, wherein the fourth one of the p-channel transistors and the fifth one of the p-channel transistors are alternately turned on, and unused drain current in each case is conducted from the first one of the p-channel transistors and the second one of the p-channel transistors to the signal output when a high frequency differential signal having a sufficiently high amplitude is present at the differential signal inputs.

12. A system for galvanically isolated transmission of digital signals, comprising: a transmitter side which includes a transmitter encompassing an on-off keying modulator; and a receiver side which includes a current comparator, a common-mode control circuit, and a detector circuit, the detector circuit including: two differential signal inputs; an input common-mode voltage connection; an alternating voltage coupling; a differential stage; an operating voltage connection; an operating ground connection; a signal output; a bias current connection; and a rectifier stage; wherein the alternating voltage coupling includes two capacitors and two resistors, and one of the capacitors, in each case, being connected to a first side at one of the differential signal inputs, and two sides of the two capacitors each being connected to the differential stage and to the input common-mode voltage connection via one of the resistors; wherein the differential stage including a first n-channel transistor and a second n-channel transistor, and the first n-channel transitory and the second n-channel transistor each being connected to one of the resistors of the alternating voltage coupling and one of the capacitors of the alternating voltage coupling; wherein the bias current connection is connected to the differential stage via a third n-channel transistor, and the bias current connection being connected to the rectifier stage via a fourth n-channel transistor and a fifth n-channel transistor; wherein the operating ground connection is connected to the third n-channel transistor, the fourth n-channel transistor, and the fifth n-channel transistor; wherein the rectifier stage includes five p-channel transistors, the first n-channel transistor being connected to a first one of the p-channel transistors, a fourth one of the p-channel transistors and a fifth one of the p-channel transistors, and the second n-channel transistor being connected to a second one of the p-channel transistors, the fourth one of the p-channel transistors and the fifth one of the p-channel transistors; wherein the operating voltage connection is connected to the first one of the p-channel transistors, the second one of the p-channel transistors, and a third one of the p-channel transistors; and wherein the signal output is connected to the fourth one of the p-channel transistors and the fifth one of the p-channel transistors.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Exemplary embodiments of the present invention are explained in greater detail based on the figures and the description below.

[0043] FIG. 1 shows a schematic representation of a system according to an example embodiment of the present invention.

[0044] FIG. 2 shows a specific embodiment of a detector circuit according to an example embodiment of the present invention.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0045] The present invention provides a detector circuit of a receiver for a galvanically isolated signal transmission. A preferably large number of the following requirements should be met:

[0046] differential transmission and high common-mode and interference suppression;

[0047] OOK modulation;

[0048] short delay times; and

[0049] suitability for magnetic and capacitive galvanic isolation.

[0050] FIG. 1 shows one specific embodiment of a system 1 according to the present invention for the galvanically isolated transmission of digital signals. System 1 encompasses a transmitter side 2, which includes a transmitter 4 encompassing an on-off keying modulator, as well as a receiver side 3, which includes a receiver 5, a current comparator 7 and a common-mode control circuit 9. Detector circuit 8 according to the present invention includes receiver 5 and a galvanic isolator 6.

[0051] FIG. 2 shows one specific embodiment of a detector circuit 8 according to the present invention for galvanically isolated transmission of digital signals. The detector circuit includes two differential signal inputs RF1, RF2, one input common-mode voltage connection VCM and one alternating voltage coupling. The alternating current coupling includes two capacitors C1, C2 and two resistors R1, R2. One capacitor C1, C2 in each case is connected to one of the differential signal inputs RF1, RF2 on a first side. The second sides of the two capacitors C1, C2 are each connected to a differential stage of the detector circuit and to input common-mode voltage connection VCM via one resistor R1, R2 in each case.

[0052] Detector circuit 8 further includes one operating voltage connection AVDD, one signal output IRECT, one bias current connection IBIAS and one rectifier stage. The differential stage includes a first n-channel transistor MN1 and a second n-channel transistor MN2. First and second n-channel transistors MN1, MN2 are each connected to one resistor R1, R2 and one capacitor C1, C2 of the alternating voltage coupling.

[0053] Bias current connection IBIAS is connected to the differential stage via a third n-channel transistor MN3. Bias current connection IBIAS is connected to the rectifier stage via a fourth n-channel transistor MN4 and a fifth n-channel transistor MN5.

[0054] An operating ground connection AVSS is connected to third, fourth and fifth n-channel transistors MN3, MN4, MN5.

[0055] The rectifier stage includes five p-channel transistors MP1, MP2, MP3, MP4, MP5. First n-channel transistor MN1 is connected to first p-channel transistor MP1, fourth p-channel transistor MP4 and fifth p-channel transistor MP5. Second n-channel transistor MN2 is connected to second p-channel transistor MP2, fourth p-channel transistor MP4 and fifth p-channel transistor MP5.

[0056] Operating voltage connection AVDD is connected to first, second and third p-channel transistors MP1, MP2, MP3.

[0057] Signal output IRECT is connected to fourth and fifth p-channel transistors MP4, MP5.

[0058] The drain currents in first n-channel transistor MN1 and in second n-channel transistor MN2 are equally high and each are double that of the current present at bias current connection IBIAS (I.sub.DS,MN1=I.sub.DS,MN2=2 I.sub.BIAS) if no differential signal is present at differential signal inputs RF1, RF2. The drain currents of third p-channel transistor MP3 and fourth p-channel transistor MP4 are three times as high as the current present at bias current connection IBIAS (I.sub.DS,MP3=I.sub.DS,MP4=3 if no differential signal is present at differential signal inputs RF1, RF2.

[0059] The current from third n-channel transistor MN3 (IDS,MN3=4 IBIAS) is conducted all the way through first n-channel transistor MN1 or second n-channel transistor MN2 if a high-frequency differential signal having a sufficiently high amplitude is present at differential signal inputs RF1, RF2. The corresponding potential at node k1 or k2 of detector circuit 8 is then temporarily reduced, since the drain currents of the re-channel transistors are higher than the drain currents of the p-channel transistors (I.sub.DS,MNx>I.sub.DS,MPX, x=1, 2).

[0060] Fourth p-channel transistor MP4 and fifth p-channel transistor MP5 are alternately turned on, and the unused drain current in each case is conducted from first p-channel transistor MP1 and second p-channel transistor MP2 to signal output IRECT if a high-frequency differential signal having a sufficiently high amplitude is present at differential signal inputs RF1, RF2.

[0061] In particular, the following four advantages may result due to the approach according to the present invention:

[0062] 1. The example detector circuit 8 outputs a corresponding current signal with the aid of the first applied half-wave of the carrier signal. This permits a high transmission speed, which is essentially determined by the inertia of current comparator 7.

[0063] 2. Due to the nearly digital control of fourth p-channel transistor MP4 and fifth p-channel transistor MP5, the active rectification of the high-frequency signal becomes more robust with respect to a mismatch within detector circuit 8 and permits without problems the demodulation of an OOK signal with the aid of downstream current comparator 7.

[0064] 3. The differential stage suppresses common-mode interferences to a significant degree. This interference suppression is limited in a first approximation only by the mismatch between first n-channel transistor MN1 and second n-channel transistor MN2 and by the finite output resistance of third n-channel transistor MN3.

[0065] 4. It is not important how the high frequency differential signal reaches differential signal inputs RF1, RF2, whereby receiver 5 may be used for capacitive and magnetic isolation alike.

[0066] In particular, advantages 2 and 3 set the approach according to the present invention apart from those of the related art.