RC OSCILLATOR

Abstract

The disclosure relates to a square wave RC oscillator circuit, example embodiments of which include an oscillator circuit for generating an output square wave signal (OUT) having first and second voltage output levels (L, H), the oscillator circuit comprising: a comparator having an output and first and second inputs; a switching circuit configured to provide an oscillatory waveform at the first input of the comparator; and a feedback circuit arranged to sample the first input of the comparator each time the output square wave signal (OUT) switches between the first and second voltage output levels (L, H) and to compare this sampled voltage with first and second reference voltages (V.sub.A, V.sub.B) to adjust a voltage provided to the second input of the comparator.

Claims

1. An oscillator circuit for generating an output square wave signal (OUT) having first and second voltage output level, the oscillator circuit comprising: a comparator having an output and first and second inputs; a switching circuit configured to provide an oscillatory waveform at the first input of the comparator; and a feedback circuit arranged to sample the first input the comparator each time the output square wave signal (OUT) switches between the first and second voltage output levels (L, H) and to compare this sampled voltage with first and second reference voltages (V.sub.A, V.sub.B) to adjust a voltage provided to the second input of the comparator.

2. The oscillator circuit of claim 1 wherein the switching circuit comprises: a first capacitor (C.sub.OSC) connected between the first input of the comparator and a common connection; a first switch connected between the first input of the comparator and a first current source, the first switch configured to connect the first current source to charge the first capacitor (C.sub.OSC) when the output square wave signal (OUT) is at the first voltage level (L); a second switch connected between the first input of the comparator and a second current source, the second switch configured to connect the second current source to discharge the capacitor (C.sub.OSC) when the output square wave signal (OUT) is at the second voltage level (H).

3. The oscillator circuit of claim 1, wherein the feedback circuit comprises: a sampler having an input connected to the output of the comparator and configured to provide a first sampling pulse (sam_hi) when the output of the comparator (505) changes from the first voltage level (L) to the second voltage level (H) and a second sampling pulse (sam_lo) when the voltage at the output (509) of the comparator (505) changes from the second voltage level (H) to the first voltage level (L); a first amplifier having a first input connected to the first input of the comparator via a third switch configured to close upon receiving the first sampling pulse (sam_hi) from the sampler and a second input connected to a first reference voltage source (V.sub.A); a second capacitor (C.sub.2) connected between the first input of the first amplifier and the common connection; a second amplifier having a first input connected to the first input of the comparator via a fourth switch configured to close upon receiving the second sampling pulse (sam_lo) from the sampler and a second input connected to a second reference voltage source (V.sub.B); a third capacitor (C.sub.3) connected between the first input of the second amplifier and the common connection; and a fifth switch connected between the second input of the comparator and outputs of the first and second amplifiers, the fifth switch configured to alternately connect the second input of the comparator to the output of the first amplifier and the output of the second amplifier.

4. The oscillator circuit of claim 3 wherein the fifth switch is configured to connect the second input of the comparator to the output of the first amplifier when the output of the comparator is at the first voltage level (L) and to the output of the second amplifier when the output of the comparator is at the second voltage level (H).

5. The oscillator circuit of claim 3 wherein the fifth switch is configured to connect the second input of the comparator to the output of the first amplifier when the output square wave signal (OUT) is at the first voltage level (L) and to the output of the second amplifier when the output square wave signal (OUT) is at the second voltage level (H).

6. The oscillator circuit of claim 2 wherein the outputs of the first and second amplifiers are connected to the fifth switch via respective first and second low pass filters.

7. The oscillator circuit of claim 1 wherein the switching circuit is configured to provide a triangular waveform to the first input of the comparator.

8. The oscillator circuit of claim 7 wherein the first and second current sources are each configured to provide a current having a magnitude equal to a difference between the first and second reference voltages divided by a first resistor (R.sub.OSC).

9. An integrated circuit comprising: an oscillator circuit according to any preceding claim; and an analog to digital converter configured to output a digital value (DIG OUT) corresponding to a ratio between a first input voltage (V.sub.REF) and a second input voltage (V.sub.IN), wherein the output square wave signal (OUT) of the oscillator circuit is provided as a clock signal (CLK) to the analog to digital converter.

10. The integrated circuit of claim 9, wherein the first input voltage is a reference voltage and the second input voltage is temperature dependent, such that the output digital value (DIG OUT) of the analog to digital converter corresponds to a temperature.

11. An integrated circuit comprising: an oscillator circuit according to claim 1; and a switched capacitor resistor circuit, wherein the output square wave signal (OUT) of the oscillator circuit is provided as a switching signal to the switched capacitor resistor circuit.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0037] Embodiments will be described, by way of example only, with reference to the drawings, in which:

[0038] FIG. 1 is a schematic diagram of a conventional square wave oscillator circuit;

[0039] FIG. 2 is a schematic diagram of triangular and square waveforms from the circuit of FIG. 1;

[0040] FIG. 3 is a schematic diagram of triangular and square waveforms with inaccurate switching levels caused by time delays;

[0041] FIG. 4 is a schematic diagram of a triangular waveform having step changes caused by charge injection;

[0042] FIG. 5 is a schematic diagram of an example square wave oscillator circuit;

[0043] FIG. 6 is a schematic diagram of various waveforms from the oscillator circuit of FIG. 5;

[0044] FIG. 7 is a plot of simulated voltages as a function of time for the circuit of FIG. 5;

[0045] FIG. 8 is a schematic diagram of an example analog to digital converter (ADC) using a clock signal provided by the oscillator circuit of FIG. 5;

[0046] FIG. 9 is a schematic diagram of example voltage signals in the ADC of FIG. 8; and

[0047] FIG. 10 is a schematic diagram of an example switched capacitor resistor circuit.

[0048] It should be noted that the Figures are diagrammatic and not drawn to scale. Relative dimensions and proportions of parts of these Figures have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments.

DETAILED DESCRIPTION OF EMBODIMENTS

[0049] FIGS. 1 to 4 have been described above in relation to the background.

[0050] FIG. 5 is a schematic diagram of an example square wave oscillator circuit 500 that aims to address one or more of the problems outlined above relating to accuracy of providing a square wave output signal. The circuit 500 comprises an RC oscillator switching circuit 530 similar to that of the conventional oscillator circuit 100 of FIG. 1, and with a comparator 505 similar to the comparator 105 of FIG. 1. The RC oscillator circuit 530 comprises a capacitor C.sub.OSC connected between a switching circuit and a common connection 512. The switching circuit comprises a pair of current sources 514, 515 switchably connected to the capacitor C.sub.OSC, the switching being controlled by the high and low voltage levels of the output signal OUT from the circuit 500. When the output signal is low, switch 502 connects current source 514 to capacitor C.sub.OSC and when the output signal is high, switch 515 connects current source 515 to capacitor C.sub.OSC Each current source provides a current to capacitor C.sub.OSC that is determined by the difference between reference voltage levels V.sub.A and V.sub.B, termed V.sub.AB, and by the resistor component R.sub.OSC of the RC oscillator circuit 530. When switch 502 connects current source 514 to capacitor C.sub.OSC, the voltage across C.sub.OSC increases at a constant rate, and when switch 515 connects current source 515 to capacitor C.sub.OSC, the voltage across C.sub.OSC decreases at the same constant rate. The voltage across the capacitor C.sub.OSC is provided at a non-inverting input 510 of a comparator 505 as a triangular wave voltage signal V.sub.IN.

[0051] As with the comparator 105 of FIG. 1, the comparator 505 is configured to compare the triangular waveform provided at the first input 510 with a voltage provided to a second input 511, in this case the inverting input of the comparator 505. The voltage provided at the second input 511 is switched by switch 522 each time the output 509 of the comparator switches between a high and low state. In this case, however, the comparison is made with a voltage that is adjusted by a feedback circuit 531 that is arranged to sample the voltage V.sub.IN at the first input 510 each time the output 509 switches between high and low states and compare this sampled voltage with first and second reference voltages V.sub.A, V.sub.B, which are the intended peak values of the triangular waveform provided to the input 510, to adjust a voltage provided to the second input 511 of the comparator 505.

[0052] In the arrangement shown in FIG. 5, switch 522 is controlled by the output comp_out of the comparator 505. In alternative arrangements, switch 522 may instead be controlled by the square wave output OUT, i.e. the output from the sampler 508.

[0053] The feedback circuit 531 comprises a sampler 508, which is connected to the output 509 of the comparator and provides sample pulses sam_hi and sam_lo from the output voltage signal comp_out of the comparator 505. The signals comp_out, sam_hi and sam_lo, along with the input triangular waveform V.sub.IN 601 and output square wave OUT 602, are illustrated in FIG. 6.

[0054] Sample pulse sam_hi goes from low to high when the output comp_out of the comparator 505 goes from low to high. When sam_hi goes low again the output OUT goes from high to low. Conversely, sample pulse sam_lo goes from low to high when comp_out goes from high to low. When sam_lo goes low again, OUT goes from high to low. The effect of this is that a sample is taken each time the output switches state, and this is used to control the voltage level the input signal V.sub.IN is compared with.

[0055] Sample switches 517 or 520 are closed for a the short time interval that sample pulses sam_hi or sam_lo are high. When sample switches 517, 520 open again, the output signal OUT changes state.

[0056] Charge/discharge switches 502 and 503 are controlled by the output signal OUT after the samples are taken, but switch 522 can be switched by the output of the comparator 505 comp_out instead of the output signal OUT. For practical reasons, this is preferable because a possible delay of switch 522 is less critical and the spikes that are caused by the switching of switch 522 will not affect the switching of switches 502/503 or the charge/discharge cycles. Therefore, switch 522 can be controlled by either comp_out or OUT, while switches 502 and 503 must be controlled by OUT.

[0057] Operation of switch 522 does not affect the comp_out state: when the voltage at the inverting input 511 of comparator 505 is connected via switch 522 to Vcomp_lo and V.sub.IN drops below Vcomp_lo, then comp_out goes low. As a result, 522 switches and Vcomp_hi is connected to the inverting input 511. This results in positive feedback: the voltage at node 511 is suddenly way below the voltage V.sub.IN at node 510, which will help the comparator 505 switch faster.

[0058] First and second amplifiers 506, 507 each have a first input 516, 519 that is switchably connected to the first input 510 of the comparator 505 via respective switches 517, 520. Switch 517 closes upon receiving the sample pulse sam_hi, while switch 520 closes upon receiving the sample pulse sam_lo. A second input 518, 521 of each amplifier is connected to respective reference voltage sources V.sub.A, V.sub.B. The first input 516, 519 of each amplifier 506, 507 is connected to the common connection 512 via respective capacitors C.sub.2, C.sub.3. An output 523, 524 of each amplifier 506, 507 is connected to switch 522 via an optional low pass filter 525, 526.

[0059] The timing of the sampler 508 means that sample pulses sam_hi and sam_lo are used to take a voltage sample from the triangular waveform provided at the comparator input 510 at its high and low peaks, resulting in samples Vhigh and Vlow respectively (see FIG. 6). A first amplifier 506 amplifies the difference between Vhigh and a first reference voltage V.sub.A, and the output from the amplifier 506 is fed to optional low pass filter 525 to provide a signal Vcomp_hi that is connected to the comparator second input 511 during the low phase of the comparator output signal comp_out. Amplifier 507 amplifies the difference between Vlow and a second reference voltage V.sub.B, and the output from amplifier 507 is fed to optional low pass filter 526 that is connected to the comparator second input 511 during the high phase of the output signal. The effect of this is that, once the feedback loop is settled, the peak to peak amplitude of the triangular waveform 601 becomes identical to the intended difference between the first and second reference voltages, i.e. V.sub.A−V.sub.B=V.sub.AB.

[0060] Input offset voltages of the amplifiers 506, 507 may cause an error on the amplitude of the triangular waveform 601. These errors can however be made small because the size of the input transistors of the amplifiers 506, 507 can be chosen to be larger without resulting in a system performance penalty.

[0061] FIG. 7 illustrates an example simulation plot of the expected behaviour of the circuit 500 of FIG. 5 in terms of the reference voltages V.sub.A, V.sub.B, the signal V.sub.IN (i.e. the input triangular waveform) and signals Vhigh and Vlow. Once the reference voltage levels V.sub.A, V.sub.B have stabilised, at around 1 μs, the oscillator circuit 530 begins to provide a triangular waveform V.sub.IN and the voltage signals Vhigh, Vlow are progressively adjusted by the feedback circuit 531. At around 4 μs the triangular waveform V.sub.IN begins to stabilise and by around 8 μs the output had fully stabilised such that Vhigh=V.sub.A and Vlow=V.sub.B.

[0062] The waveform provided to the comparator in the examples above is in the form of a triangular waveform, i.e. with equal charge and discharge rates given by V.sub.AB/R.sub.OSC. In other examples a different shaped waveform may also be used, for example an asymmetrical type waveform, where the charge and discharge rates are unequal. Such alternative examples may for example involve the use of one capacitor that is charged at a constant rate and then reset to 0V, or by using two capacitors in one RC oscillator where a first capacitor is discharged to 0V while a second is charged to V.sub.A, followed by toggling of the output and discharging the second capacitor to 0V while the first capacitor is charged to V.sub.A. Other types of RC oscillator arrangements may also be possible. The common feature to all such RC oscillators with the square wave oscillator of the type disclosed herein is that the peak amplitude of the input voltage signal is sampled each time the output of the comparator switches, and this is compared with the intended value (i.e. V.sub.A or V.sub.B) in a feedback loop that is used to adjust the value provided to the second input of the comparator to make the output square wave signal have an amplitude equal to the difference between the reference voltages.

[0063] A square wave oscillator of the type disclosed herein may be used in applications where it is important that the period of a clock signal is accurately related to an RC product, where R and C are internal component values of the IC. A first example is an analog to digital converter (ADC) 800 with a counting DAC in a feedback path, an example of which is shown in FIG. 8. An example set of voltage signals in the ADC 800 is shown in FIG. 9. In this, the ratio between an input voltage V.sub.IN and a reference voltage V.sub.REF is expressed as an n-bit digital word. V.sub.REF is converted into a current I.sub.REF=V.sub.REF/R.sub.REF, where R.sub.REF is an internal resistor in the IC. The n-bit digital output word K.sub.dig is stored in an n-bit counter 801, which counts down to zero in K.sub.digT.sub.CLK seconds. During that time, an internal capacitor C.sub.REF is charged with I.sub.REF to a voltage V.sub.RAMP. V.sub.RAMP is compared with the analog input voltage V.sub.IN by comparator 802. The comparator output controls the up/down input of a successive approximation register (SAR) block 803. When the down counter contents 904 has counted down to zero, the SAR 803 will respond at its U/D input 902 by either increasing or decreasing its contents K.sub.dig and the new SAR contents 901 is loaded in the down counter 801. The capacitor C.sub.REF is discharged to 0V subsequently with a reset switch 805 activated by logic 804 that closes the reset switch.

[0064] When Vramp is below Vin, the up/down output 902 is high. At the upgoing edge of signal EN SAR 903, the SAR contents 901 is increased or decreased, depending on the sign of the up/down signal 902 at that moment.

[0065] The SAR 803 responds to its up/down input U/D in a way such that it finally iterates to its end value. This may be a simple up-down counter that increases or decreases by 1 each time it is enabled. When this feedback loop is settled the SAR contents 901 will toggle between two values. The contents K.sub.dig will then represent the ratio V.sub.IN/V.sub.REF. The peak value of V.sub.RAMP will be V.sub.IN in that case, i.e. V.sub.IN=V.sub.RAMP=(I.sub.REF.Math.K.sub.DIG.Math.T.sub.CLK)/C.sub.REF. If T.sub.CLK is derived from an RC oscillator, it is possible to make T.sub.CLK=R.sub.OSC.Math.C.sub.OSC, where R.sub.OSC and C.sub.OSC are the internal components of the IC as well. Further, with I.sub.REF=V.sub.REF/R.sub.REF, we obtain:

V.sub.IN=N.sub.REF.Math.K.sub.dig.Math.R.sub.OSC.Math.C.sub.OSC)/R.sub.REF.Math.C.sub.REF)

or:

K.sub.dig=(V.sub.IN/V.sub.REF).sub..Math.{(R.sub.REF.Math.C.sub.REF)/(R.sub.OSC.Math.C.sub.OSC)}=k.sub..Math.V.sub.IN/V.sub.REF

[0066] If R.sub.REF, C.sub.REF, R.sub.OSC and C.sub.OSC are all realized in the same IC, the ratio k can be made accurate due to the close matching of resistors and capacitors of the same type in the same IC. The clock period of the internal RC square wave oscillator as described herein can be made accurately proportional to an internal RC time and is therefore very suitable for this application.

[0067] In a second example, a temperature sensor may be based on an ADC with a counting DAC in a feedback path. In an IC, bandgap reference circuits are circuits that generate a fairly accurate (1-2%) temperature compensated reference voltage V.sub.REF, based on the (extrapolated) bandgap voltage of a PN junction. A bandgap reference voltage is a voltage that is sum of a diode voltage V.sub.diode (with negative temperature coefficient) and a PTAT-voltage V.sub.ptat (positive temperature coefficient). PTAT stands for ‘proportional to absolute temperature’. Such a voltage can be accurately obtained from the difference between two diode voltages with different current densities. The PTAT voltage can be amplified such that it has the same but opposite temperature dependency as the diode voltage temperature dependency. The ratio of V.sub.ptat and V.sub.REF can therefore be used for a temperature measurement. If, in the ADC circuit 800 shown in FIG. 8, the PTAT voltage V.sub.ptat is used as the input V.sub.IN and the bandgap reference voltage V.sub.bg as V.sub.REF, a temperature sensor with a digital output reading is obtained, where a digital output of 0 corresponds to 0K. An offset may be implemented to select a different temperature to correspond to a digital output of 0.

[0068] In a third example application, a switched capacitor resistor 1000, a schematic diagram of which is shown in FIG. 10, may be driven by the clock signal from the square wave oscillator circuit 500. In a first period of a clock cycle, a capacitor Cs is charged to an input voltage V.sub.in by closing switch S1 and opening switch S2 and then, during a second period of the clock cycle, the capacitor Cs discharged to an output voltage V.sub.t by opening switch 51 and closing switch S2. The amount of charge transferred from the input to the output is Q=C.sub.s.Math.(V.sub.in−V.sub.out). If the clock frequency is f.sub.CLK, the average current flowing from input to output is I.sub.AV=f.sub.CLK.Math.C.sub.s(V.sub.in−V.sub.out). The equivalent resistor is then R.sub.EQ=(V.sub.in−V.sub.out)/I.sub.AV=1/(f.sub.CLK.Math.C.sub.s). If f.sub.CLK is derived from an accurate RC oscillator, f.sub.CLK=1/(R.sub.OSC.Math.C.sub.OSC). The equivalent resistor is therefore R.sub.EQ=R.sub.OSC.Math.C.sub.OSC/C.sub.S, which is accurately proportional to R.sub.OSC. R.sub.EQ can then be easily scaled by changing C.sub.s or scaling f.sub.CLK with dividers or rate multipliers. Switched capacitor resistors may for example be used in switched capacitor filters.

[0069] From reading the present disclosure, other variations and modifications will be apparent to the skilled person. Such variations and modifications may involve equivalent and other features which are already known in the art of electronic circuit design, and which may be used instead of, or in addition to, features already described herein.

[0070] Although the appended claims are directed to particular combinations of features, it should be understood that the scope of the disclosure of the present invention also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention.

[0071] Features which are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable sub-combination. The applicant hereby gives notice that new claims may be formulated to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.

[0072] For the sake of completeness it is also stated that the term “comprising” does not exclude other elements or steps, the term “a” or “an” does not exclude a plurality, and reference signs in the claims shall not be construed as limiting the scope of the claims.