Method for equivalent high sampling rate FIR filtering based on FPGA

Abstract

The present invention provides a method for equivalent high sampling rate FIR filtering based on FPGA, first, the coefficients h(k) of FIR filter are found by using MATLAB, multiplied by an integer and then rounded for the purpose that the rounded coefficients h(k) can be directly used into a FPGA, then the ADC's output of high data rate fs is lowered by dividing the ADC's output x(n) into M parallel data streams xi(n) of low data rate, and the M×L samples in one clock cycle is obtained by delaying the M parallel data streams xi(n) simultaneously by 1, 2, . . . , L′ periods of the synchronous clock, at last, the samples yi(n) of FIR filtering output is calculated according to the samples selected from the M×L samples, and the filtered data y(n) of data rate fs is obtained by putting the samples yi(n) together in ascending order of i. Thus, the continuous FIR filtering of an ADC's output sampled with high sampling rate is realized, while the data rates before and after the FIR filtering are unchanged.

Claims

1. A method for equivalent high sampling rate FIR filtering based on FPGA, comprising: (1). finding the coefficients h(k) of FIR filter according to the requirements of an actual application, where the length L of the FIR filter satisfies that L mod M=0, and letting L′=L/M; (2). multiplying the coefficients h(k) by an integer, and then rounding the multiplied coefficients h(k) for the purpose that the rounded coefficients h(k) can be directly used into a FPGA; (3). using a divider in the FPGA to lower the data rate f.sub.s of an ADC's output x(n) by dividing the ADC's output x(n) into M parallel data streams x.sub.i(n) (i=0, 1, . . . , M−1) of f.sub.s/M data rate; (4). using M delay elements in the FPGA to respectively delay the M parallel data streams x.sub.i(n) simultaneously by 1, 2, . . . , L′ synchronous clock periods to obtain M×L samples in one clock cycle; (5). using a selecting circuit in the FPGA to select L+M−1 samples from the obtained M×L samples in a clock cycle, and using the rounded coefficients h(k) by multipliers and adders in the FPGA to calculate the samples y.sub.i(n) (i=0, 1, . . . , M−1) of FIR filtering output as follows: $\begin{array}{c}{y}_i\left(n\right)=\underset{k=0}{\overset{L-1}{.Math.}}h\left(k\right)x\left(\mathrm{nM}+i-k\right)\\ =h\left(0\right)x\left(\mathrm{nM}+i\right)+h\left(1\right)x\left(\mathrm{nM}+i-1\right)+\mathrm{.Math.}+h\left(L-1\right)x\left(\begin{array}{c}\mathrm{nM}+i-\\ \left(L-1\right)\end{array}\right)\\ =h\left(0\right)x\left(\mathrm{nM}+i\right)+h\left(1\right)x\left(\mathrm{nM}+i-1\right)+\mathrm{.Math.}+h\left(L-1\right)x\left(\begin{array}{c}\left(n-L^{\prime }\right)\\ M+i+1\end{array}\right);\end{array}$ (6). putting the samples y.sub.i(n) together in ascending order of i to obtain the filtered data y(n) of data rate f.sub.s; (7). repeating the step (5), step (6) in later cycles, continuously obtaining the filtered data y(n) of data rate f.sub.s.

2. The method for equivalent high sampling rate FIR filtering based on FPGA of claim 1, wherein the integer is the integral power of 2.

Description

BRIEF DESCRIPTION OF THE DRAWING

(1) The above and other objectives, features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

(2) FIG. 1 is a diagram of a FIR filtering structure based on the combination of multi-channel parallel data in prior art;

(3) FIG. 2 is a diagram of a polyphase filtering structure in prior art;

(4) FIG. 3 is a diagram of a FIR filtering structure in accordance with the present invention;

(5) FIG. 4 is a flow diagram of an equivalent high sampling rate FIR filtering based on FPGA in accordance with the present invention;

(6) FIG. 5 is a diagram of locations of the L+M−1 continuous samples of an ADC's output x(n) in L′+1 continuous clock cycles of CLK in accordance with the present invention;

(7) FIG. 6 is a diagram of locations of the L+M−1 continuous samples of an ADC's output x(n) in one cycle of CLK in accordance with the present invention;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

(8) Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that the similar modules are designated by similar reference numerals although they are illustrated in different drawings. Also, in the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may obscure the subject matter of the present invention.

Embodiment

(9) FIG. 3 is a diagram of a FIR filtering structure in accordance with the present invention.

(10) In one embodiment, the data rate of an ADC's output x(n) is f.sub.s, i.e. the ADC's output x(n) is obtained at sampling rate f.sub.s. The impulse response, namely the coefficients of FIR filter are h(k), k=1, 2, . . . , L−1. The filtered data of the ADC's output x(n) is y(n). The data rate of the filtered data y(n) is same as that of the ADC's output x(n), also is f.sub.s. The filtered data y(n) is:

(11) $\begin{array}{cc}y\left(n\right)=\underset{k=-\infty }{\overset{\infty }{.Math.}}h\left(k\right)x\left(n-k\right)& \left(1\right)\end{array}$

(12) Where the clock frequency of filtering operation is f.sub.s. While the filtering operation is realized in a FPGA, the ADC's output x(n) cannot directly be received by the FPGA because the clock frequency f.sub.s of filtering operation is higher than the highest system clock frequency of the FPGA. Thus, the data rate f.sub.s of the ADC's output x(n) is needed to be lowered by using a high-speed receiver to divide it into M parallel data streams x.sub.i(n). So the equation (1) is performed in parallel, and multi channels (M) filtered data y.sub.i(n), i=1, 2, . . . M−1, are outputted. The multi channels filtered data are the polyphase decompositions of the filtered data y(n), and the data rate of the filtered data y(n) is same as that of the ADC's output x(n). Therefore, the essence of the present invention is: by using the multi channels of parallel filtering to realize that the data rate before and after the FIR filtering is unchanged.

(13) FIG. 4 is a flow diagram of an equivalent high sampling rate FIR filtering based on FPGA in accordance with the present invention.

(14) In one embodiment, As shown in FIG. 3 and FIG. 4, a method for equivalent high sampling rate FIR filtering based on FPGA comprises the following steps:

(15) Step S1: Using MATLAB to find the coefficients h(k) of FIR filter according to the requirements of an actual application, where the length L of the FIR filter satisfies that L mod M=0, and letting L′=L/M.

(16) Step S2: Multiplying the coefficients h(k) by an integer, and then rounding the multiplied coefficients h(k) for the purpose that the rounded coefficients h(k) can be directly used into a FPGA.

(17) In the embodiment, the integer is selected as the integral power of 2.

(18) Step S3: Lowering the data rate f.sub.s of an ADC's output x(n) by dividing the ADC's output x(n) into M parallel data streams x.sub.i(n) (i=0, 1, . . . , M−1) of f.sub.s/M data rate.

(19) In the embodiment, the high-speed receiver divides the ADC's output x(n) into M parallel data streams x.sub.i(n) of f.sub.s/M data rate, the filtered data y(n) are decomposed into y.sub.i(n) (i=0, 1, . . . , M−1), They can be expressed in equation as:

(20) $\begin{array}{cc}\{\begin{array}{c}{x}_i\left(n\right)=x\left(\mathrm{nM}+i\right)\\ y_i\left(n\right)=y\left(\mathrm{nM}+i\right)\end{array}& \left(2\right)\end{array}$

(21) Step S4: Delaying the M parallel data streams x.sub.i(n) simultaneously by 1, 2, . . . , L′ periods of the synchronous clock to obtain M×L samples in one clock cycle.

(22) When the length of the FIR filter is L, and L mod M=0, the samples y.sub.i(n) (i=0, 1, . . . , M−1) of FIR filtering output is:

(23) $\begin{array}{cc}\begin{array}{c}{y}_i\left(n\right)=y\left(\mathrm{nM}+i\right)\\ =\underset{k=0}{\overset{L-1}{.Math.}}h\left(k\right)x\left(\mathrm{nM}+i-k\right)\end{array}& \left(3\right)\end{array}$

(24) Further:

(25) $\left(4\right)$$\begin{array}{c}{y}_i\left(n\right)=\underset{k=0}{\overset{L-1}{.Math.}}h\left(k\right)x\left(\mathrm{nM}+i-k\right)\\ =h\left(0\right)x\left(\mathrm{nM}+i\right)+h\left(1\right)x\left(\mathrm{nM}+i-1\right)+\mathrm{.Math.}+h\left(L-1\right)x\left(\begin{array}{c}\mathrm{nM}+\\ i-\left(L-1\right)\end{array}\right)\\ =h\left(0\right)x\left(\mathrm{nM}+i\right)+h\left(1\right)x\left(\mathrm{nM}+i-1\right)+\mathrm{.Math.}+h\left(L-1\right)x\left(\begin{array}{c}\left(n-L^{\prime }\right)\\ M+i+1\end{array}\right)\end{array}$

(26) From equation (4), to obtain one sample y.sub.i(n), i+1+(L′−1)M+M−i−1=L′M=L continuous samples of x(n) are needed to implement the multiple-accumulating in equation (4). And if M continuous samples of filtered data y(n), which respectively respond to the samples y.sub.i(n) (i=0, 1, . . . , M−1), are needed to be obtained simultaneously in one clock cycle, the L+M−1 continuous samples from x((n−L′)M+1) to x((nM+M−1) are needed.

(27) The locations of the L+M−1 continuous samples are shown in FIG. 5, where CLK is the synchronous clock of frequency f.sub.s/M. From the FIG. 5, we will find that the L+M−1 continuous samples are distributed in L′+1 continuous clock cycles of CLK.

(28) As shown in FIG. 6, to obtain the L+M−1 continuous samples in one clock cycle, the M parallel data streams x.sub.i(n) are delayed simultaneously by 1, 2, . . . , L′ periods of the synchronous clock, where x.sub.i.sup.j(n) is the sample obtained by delaying x.sub.i(n) j periods of CLK and can be express as follows:

(29) $\begin{array}{cc}\begin{array}{c}{x}_i^j\left(n\right)=x_i\left(n-j\right)\\ =x\left(\left(n-j\right)M+i\right)\end{array}& \left(5\right)\end{array}$

(30) where j=1, 2, . . . , L′.

(31) After delaying the M parallel data streams x.sub.i(n), the M×L samples in one clock cycle (for example, the leftmost column) are obtained in one clock cycle. The L+M−1 continuous samples from x((n−L′)M+1) to x((nM+M−1) are in the M×L samples.

(32) In the embodiment, datain_i denotes x.sub.i(n) and datain_i_j is obtained by delaying datain_i_j periods of CLK. The related Verilog codes in FPGA are as follows:

(33) TABLE-US-00001   always @ (posedge CLK)  begin   datain_0_1 <= datain _0;   datain_0_2 <= datain_0_1;   ...   datain_0_j <= datain_0_(j-1);   ...   datain_0_L′ <= datain_0_(L’-1); //i=0   --------------------------------------------------------------------   datain_1_1 <= datain _1;   datain_1_2 <= datain_1_1;   ...   datain_1_j <= datain_1_(j-1);   ...   datain_1_L' <= datain_1_(L’-1); // i=1   --------------------------------------------------------------------   ......................   --------------------------------------------------------------------   datain_(M-1)_1 <= datain _(M-1);   datain_(M-1)_2 <= datain_(M-1)_1;   ...   datain_(M-1)_j <= datain_(M-1)_(j-1);   ...   datain_(M-1)_L’ <= datain_(M-1)_(L’-1); //i=M-1 end

(34) After executing the above codes, the M×L samples in one clock cycle are obtained.

(35) Step S5: Selecting L+M−1 samples from the obtained M×L samples in a clock cycle, and calculating the samples y.sub.i(n) (i=0, 1, . . . , M−1) of FIR filtering output as follows:

(36) $\left(6\right)$$\begin{array}{c}{y}_i\left(n\right)=\underset{k=0}{\overset{L-1}{.Math.}}h\left(k\right)x\left(\mathrm{nM}+i-k\right)\\ =h\left(0\right)x\left(\mathrm{nM}+i\right)+h\left(1\right)x\left(\mathrm{nM}+i-1\right)+\mathrm{.Math.}+h\left(L-1\right)x\left(\begin{array}{c}\mathrm{nM}+\\ i-\left(L-1\right)\end{array}\right)\\ =h\left(0\right)x\left(\mathrm{nM}+i\right)+h\left(1\right)x\left(\mathrm{nM}+i-1\right)+\mathrm{.Math.}+h\left(L-1\right)x\left(\begin{array}{c}\left(n-L^{\prime }\right)\\ M+i+1\end{array}\right)\end{array}$

(37) In the embodiment, dataout_i denotes y.sub.i(n), and coeff_n denotes the coefficients h(k) (k=0, 1, . . . , L−1). The related Verilog codes are as follows:

(38) TABLE-US-00002  always @(posedge CLK)  begin    data_out_0 <= coeff_0*datain_0 + coeff_1*datain_(M-1)_1 + ... +    coeff_(L-1)*datain_1_L′; // i=0    data_out_1 <= coeff_0*datain_1 + coeff_1*datain_0 + ... +    coeff_(L-1)*datain_2_L′; //  i=1  ......................    data_out_(M-1) <= coeff_0*datain_(M-1) + coeff_1*datain_(M-2) + ... +   coeff_(L-1)*datain_0_(L'-1); //i=M-1 end

(39) After executing the above codes, the samples y.sub.i(n) (i=0, 1, . . . , M−1) of FIR filtering output are obtained.

(40) Step S6: Putting the samples y.sub.i(n) together in ascending order of i to obtain a filtered data y(n) of data rate f.sub.s.

(41) Step S7: Repeating the step S5, step S6 in later cycles, continuously obtaining the filtered data y(n) of data rate f.sub.s.

(42) Thus, the continuous FIR filtering of an ADC's output sampled with high sampling rate is realized, while the data rates before and after the FIR filtering are unchanged.

(43) In present invention, according to equation (4), the calculation of each sample y.sub.i(n) needs all L filter coefficients, but different samples of the ADC's output x(n) are involved. For the calculation of one sample y.sub.i(n), L multipliers are needed. Thus, for the calculation of all samples y.sub.i(n) (i=0, 1, . . . , M−1), MX L multipliers are needed. In actual application, the coefficients of FIR filter are symmetric, i.e. h(k)=h(L−1−k), k=0, 1, . . . , L−1, only half of the MX L multipliers are needed, saving half of multiplier sources.

(44) While illustrative embodiments of the invention have been described above, it is, of course, understand that various modifications will be apparent to those of ordinary skill in the art. Such modifications are within the spirit and scope of the invention, which is limited and defined only by the appended claims