METHOD FOR PRODUCING A PHOTOEMITTING OR PHOTORECEIVING DIODE

Abstract

Method for producing a photoemitting or photoreceiving diode, including: producing, on a first substrate, first and second semiconductor layers with opposite dopings, and a third intrinsic semiconductor layer; etching trenches surrounding remaining portions of the second and third layers and of a first part of the first layer; producing, in the trenches, a dielectric spacer covering side walls of said remaining portions; etching extending the trenches as far as the first substrate; laterally etching a part of the dielectric spacer, exposing contact surfaces of the second part of the first layer; producing, in the trenches, a first electrode in contact with the contact surfaces of the second part of the first layer and with lateral flanks of the second part of the first layer.

Claims

1. A method for producing at least one photoemitting or photoreceiving diode, including at least: producing, on a first substrate, at least one stack comprising first and second layers of semiconductor doped according to opposite conductivity types, and at least a third layer of intrinsic semiconductor disposed between the first and second layers, the first layer being disposed between the first substrate and the third layer; etching trenches passing through the second and third layers and a first part of the first layer, surrounding remaining portions of the second and third layers and of the first part of the first layer, and such that bottom walls of the trenches are formed by a second part of the first layer disposed between the first part of the first layer and the first substrate; producing, in the trenches, at least one dielectric spacer covering side walls of said remaining portions; etching extending the trenches through portions of the second part of the first layer not covered by the dielectric spacer, as far as the first substrate; laterally etching a part of the dielectric spacer, exposing contact surfaces of the second part of the first layer; producing, in the trenches, at least one first electrode in contact with the contact surfaces of the second part of the first layer and with lateral flanks of the second part of the first layer.

2. The method according to claim 1, wherein the dielectric spacer has, before implementation of the lateral etching, an initial thickness greater than or equal to 1 μm.

3. The method according to claim 1, wherein the part of the dielectric spacer removed during the lateral etching has a thickness of between 10 nm and an initial thickness of the spacer minus 10 nm.

4. The method according to claim 1, wherein the contact surfaces of the second part of the first layer are perpendicular to the side walls of said remaining portions.

5. The method according to claim 1, further including, between the production of the stack and the etching of the trenches through the second and third layers and the first part of the first layer, the production of at least one etching mask disposed on the stack and having a pattern corresponding to that of the trenches, and wherein the dielectric spacer is produced by also covering side walls of the etching mask.

6. The method according to claim 1, wherein the lateral etching of a part of the dielectric spacer is an isotropic etching.

7. The method according to claim 5, wherein the lateral etching of a part of the dielectric spacer is an isotropic etching, and wherein the etching mask includes at least one material that is at least partially etched during the lateral etching of a part of the dielectric spacer.

8. The method according to claim 6, wherein the dielectric spacer includes SiO.sub.2.

9. The method according to claim 1, wherein the production of the dielectric spacer includes: depositing at least one layer of a first dielectric material covering the side walls of said remaining portions; depositing at least one layer of a second dielectric material covering the layer of the first dielectric material, the second dielectric material being chosen so that it has an etching speed greater than that of the first dielectric material during the lateral etching of a part of the dielectric spacer that corresponds to an anisotropic etching; and wherein the etching extending the trenches and the lateral etching of a part of the dielectric spacer may be implemented simultaneously during the same etching step.

10. The method according to claim 1, wherein: the stack further includes at least one electrically conductive layer such that the second layer is disposed between the third layer and the electrically conductive layer; the etched trenches pass through the electrically conductive layer and surround at least one remaining portion of the electrically conductive layer forming a first part of a second electrode; the dielectric spacer covers side walls of the first part of the second electrode; and further including, after the lateral etching of a part of the dielectric spacer, a step of producing a second part of the second electrode.

11. The method according to claim 10, wherein the production of the first electrode and of the second part of the second electrode includes at least: producing at least one opening through the stack and emerging on the first part of the second electrode; depositing at least one electrically conductive material in the opening and in the trenches; planarizing the electrically conductive material.

12. The method according to claim 10, further including, after the production of the first electrode and of the second part of the second electrode, a transfer of the photoemitting or photoreceiving diode onto an interconnection substrate such that the first and second electrodes of the photoemitting or photoreceiving diode are electrically connected to the interconnection substrate, and then a step of removing the first substrate.

13. The method according to claim 10, wherein the electrically conductive layer is optically reflective.

14. A method for producing an electronic device, including the implementation of a method according to claim 1, wherein the steps performed form a plurality of photoemitting diodes and/or a plurality of photoreceiving diodes wherein the first electrodes of said diodes are electrically connected to each other.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The present invention will be understood better from a reading of the description of example embodiments given purely indicatively and in no way limitatively, referring to the accompanying drawings, on which:

[0058] FIGS. 1A to 1J show the steps of a method for producing an electronic device, including a method for producing a photoemissive or photoreceiving diode, according to a first embodiment;

[0059] FIGS. 2A and 2B show photographs of a structure obtained when use is made of an isotropic lateral etching of an etching mask similar to that used during the method for producing a photoemissive or photoreceiver diode, according to the first embodiment;

[0060] FIGS. 3A and 3B show some of the steps of a method for producing an electronic device, including a method for producing a photoemissive or photoreceiver diode, according to a second embodiment.

[0061] Identical, similar or equivalent parts of the various figures described below bear the same numerical references so as to facilitate passing from one figure to another.

[0062] The various parts shown in the figures are not necessarily shown to a uniform scale, in order to make the figures more legible.

[0063] The various possibilities (variants and embodiments) must be understood as not being exclusive of one another and may be combined with one another.

DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS

[0064] FIGS. 1A to 1J show the steps of a method for producing an electronic device 100 according to a first embodiment. In the first embodiment described here, the device 100 includes a plurality of diodes 102 corresponding here to photoemissive or light-emitting diodes.

[0065] As shown in FIG. 1A, the device 100 is produced from a first substrate 104 comprising for example sapphire, silicon, a semiconductor similar to the one used for forming the active part of the diodes 102, or any other material enabling the first substrate 104 to form a growth substrate for the deposition of a semiconductor stack from which the diodes 102 will be produced. The first substrate 104 is used as a support for the deposition or growth of layers intended for producing the diodes 102 of the device 100.

[0066] A first layer 106 of semiconductor doped according to a first conductivity type, for example n type, is produced on the first substrate 104.

[0067] According to a particular example embodiment, this first layer 106 corresponds to a stack of a plurality of distinct semiconductor layers, for example a layer 108 of n+ doped semiconductor with a donor concentration for example of between approximately 5.Math.10.sup.17 and 5.Math.10.sup.20 donors/cm.sup.3, on which another layer 110 of n− doped semiconductor with a donor concentration of for example between approximately 10.sup.17 and 5.Math.10.sup.19 donors/cm.sup.3 is disposed. For example, the layer 108 may include GaN and the layer 110 may include InGaN. The thickness of the layer 108 is for example greater than approximately 100 nm, for example equal to approximately 3 μm, and the thickness of the layer 110 is for example between approximately 5 nm and 500 nm. The total thickness of the first layer 106, that is to say the sum of the thicknesses of the layers 108 and 110 in this particular example embodiment, is for example between approximately 20 nm and 10 μm, and preferably between approximately 2 μm and 4 μm. The layer 108 forms here a buffer layer disposed between the layer 110 and the first substrate 104 and is used in particular to filter the growth defects in order for these defects not to be located in the layer 110 which is used to form the p-n junctions of the diodes 102.

[0068] In a variant, the layers 108 and 110 may be doped with the same doping level.

[0069] According to another variant, the layer 106 may correspond to a single semiconductor layer. This single semiconductor layer is for example n doped and may have a donor concentration for example of between approximately 10.sup.17 and 5.Math.10.sup.20 donors/cm.sup.3. By way of example, this layer may include GaN and the thickness thereof is for example between approximately 20 nm and 10 μm, and advantageously between approximately 2 μm and 4 μm.

[0070] According to another variant, the layer 106 may correspond to a stack of a plurality of distinct semiconductor layers, for example a layer 108 of intentionally non-doped semiconductor forming a buffer layer disposed between the layer 110 and the first substrate 104, on which the layer 110 of n doped semiconductor with a donor concentration of for example between approximately 10.sup.17 and 5.Math.10.sup.20 donors/cm.sup.3 is disposed. The thickness of the layer 108 is for example greater than approximately 100 nm, for example equal to approximately 3 μm, and the thickness of the layer 110 is for example between approximately 100 nm and 3 μm.

[0071] One or more third layers 112 of intrinsic semiconductor, that is to say intentionally non-doped (with a residual donor concentration n.sub.nid for example equal to approximately 10.sup.17 donors/cm.sup.3, or between 10.sup.15 and 10.sup.18 donors/cm.sup.3), are produced on the first layer 106 (on the layer 110 in the example shown in FIG. 1A). In the first embodiment described here, the third layers 112 are an active region comprising one or more emissive layers, for example five, intended each to form, in the diodes 102, a quantum well. These emissive layers include for example InGaN. Each emissive layer is disposed between two barrier layers, including for example GaN. The thickness of the or of each of the emissive layers is for example equal to approximately 3 nm and more generally between approximately 0.5 nm and 10 nm, and the thickness of each of the barrier layers is for example between approximately 1 nm and 25 nm.

[0072] A second layer 114 of semiconductor doped according to a second conductivity type, opposite to the doping type of the first layer 106 and therefore here of p type, with a concentration of acceptors for example between approximately 10.sup.17 and 5.Math.10.sup.19 acceptors/cm.sup.3, is produced on the third layer or layers 112. The layers 106, 112 and 114 (and more particularly the layers 110, 112 and 114 in the example described here) are intended to form the p-i-n junctions of the diodes 102. The semiconductor of the second layer 114 is for example GaN and the thickness thereof is for example between approximately 20 nm and 10 μm.

[0073] In a variant embodiment, an electron-blocking layer (not shown in FIGS. 1A to 1J) may be disposed between the second layer 114 and the third layer or layers 112, this electron-blocking layer including for example AlGaN with 12% aluminum and being able to be p doped with a concentration of acceptors for example equal to approximately 1.Math.10.sup.17 acceptors/cm.sup.3.

[0074] Materials other than those cited above may be used for producing the layers 106, 112 and 114. For example, the material of the emissive layers formed by the third layers 112 is chosen according to the required emission spectrum of the diodes 102.

[0075] An electrically conductive layer 115 intended to form, in each diode 102, a first part of a second electrode that will be in contact with the semiconductor of the second layer 114, is disposed on the second layer 114. The electrically conductive material used is advantageously optically reflective and is for example aluminum or silver.

[0076] A layer 116 intended to form an etching mask is produced on the layer 115. The material of this layer 116 is for example SiO.sub.2.

[0077] The layers 106, 112, 114 and 115 form together a stack 117 from which the diodes 102 will be produced.

[0078] As shown in FIG. 1B, patterns are produced by lithography and etching (using for example a fluorinated plasma such as CHF.sub.3 or SF.sub.6) in the layer 116 so that the remaining portions of this layer 116 form an etching mask 118. The photolithography resin used for producing the etching mask 118 is next removed. The openings formed in the etching mask 118 correspond to the patterns of trenches to be etched in the layers of the stack 117 in order to define the mesa structures of the diodes 102.

[0079] An etching of trenches 120 passing through the electrically conductive layer 115, the second layer 114, the third layer or layers 112 and a first part 122 of the first layer 106 is implemented according to the pattern of the etching mask 118. This etching is stopped at a depth level located in the first layer 106 such that a second part 123 of the first layer 106 is preserved at the bottom of each of the etched trenches 120. In FIG. 1B, the first part 122 of the first layer 106 is delimited symbolically from the second part 123 of the first layer 106 by a dotted line. In the example described here, the etching is stopped at a level located in the layer 110 such that the layer 108 and a part of the thickness of the layer 110 are not etched. The thickness of the first layer 106 that is etched, that is to say the thickness of the first part 122 of the first layer 106, is for example between approximately 100 nm and 5 μm.

[0080] At the end of this etching, the trenches 120 surround: [0081] the etching mask 118; [0082] remaining portions 124 of the electrically conductive layer 115 intended to form first parts of the second electrodes of the diodes 102; [0083] remaining portions 126 of the second layer 114 intended to form part of the p-n junctions of the diodes 102; [0084] remaining portions 128 of the third layer or layers 112 intended to form the active regions of each diode 102, and [0085] remaining portions 130 of the first part 122 of the first layer 106 intended to form, with the remaining portions 126 of the second layer 114, the p-n junctions of the diodes 102.

[0086] The layers 115, 112, 114 and 106 are etched by dry method, for example by a reactive ion etching performed with a plasma torch system, or ICP-RIE, standing for “Inductively Coupled Plasma-Reactive Ion Etching”.

[0087] A dielectric spacer 132 is next produced in the trenches 120 (see FIG. 1C). For this purpose, a dielectric layer is conformally deposited, for example by a deposition of the PECVD (plasma enhanced chemical vapor deposition) type, on the etching mask 118 and against the side walls and the bottom walls of the trenches 120. The parts of this dielectric layer that do not cover the side walls of the trenches 120, that is to say those located on the etching mask 118 and those located at the bottom of the trenches 120, are eliminated by an anisotropic etching, corresponding for example to a dry etching such as a RIE etching or reactive ion etching. The remaining portions of this dielectric layer form the dielectric spacer 132 that covers the side walls of the remaining portions 124, 126, 128 and 130 and those of the etching mask 118.

[0088] The dielectric spacer 132 has an initial thickness equal to that of the dielectric layer deposited. This thickness is great and is for example greater than or equal to approximately 1 μm. On this FIG. 1C, this initial thickness bears the reference “e1”. The thickness of the dielectric spacer 132 corresponds to the dimension perpendicular to the surface against which the material of the dielectric spacer 132 is deposited.

[0089] As shown in FIG. 1D, a second etching of the layer 106 is then performed, extending the trenches 120 as far as the first substrate 104, through the portions of the second part 123 of the first layer 106 that are not covered by the dielectric spacer 132. At the end of this second etching, the trenches 120 also surround remaining portions 134 of the second part 123 of the first layer 106.

[0090] The etching mask 118, the remaining portions 124, 126, 128, 130, 134 and the dielectric spacer 132 form mesa structures, that is to say stacks in the form of islands, disposed on the first substrate 104. Each mesa structure of each diode 102 has a cross-section in a plane parallel to the face of the first substrate 104 on which these structures rest, for example rectangular in shape. Each of the mesa structures may therefore form a parallelepipedal-shaped element. Mesa structures with a different shape are possible, for example cylindrical.

[0091] A lateral etching of a part of the dielectric spacer 132 is next implemented, exposing contact surfaces 136 of the second part 123 of the first layer 106 (see FIG. 1E). The contact surfaces 136 of the second part 123 of the first layer 106 exposed are preferably substantially horizontal, in the direction of orientation of the figures. The lateral etching therefore exposes crystal planes parallel to the growth surface having better electrical properties than the planes perpendicular to the growth surface. The part of the dielectric spacer 132 that is eliminated during this lateral etching has a thickness (referenced “e2” in FIG. 1E) of for example between approximately 10 nm and the initial thickness of the spacer (e1) minus approximately 10 nm, so that the remaining spacer thickness (referenced “e3”) is sufficient to ensure good electrical insulation. The thickness e2 is for example equal to approximately 600 nm when the dielectric spacer 132 has an initial thickness e1 equal to approximately 1 μm. The remaining part of the dielectric spacer 132 therefore has a thickness e3=e1−e2, and for example equal to 400 nm for the example described above.

[0092] In this first embodiment, the lateral etching of the dielectric spacer 132 implemented is an isotropic etching, for example a wet chemical etching or an isotropic plasma etching. During such an isotropic etching, the etching mask 118 is therefore also at least partially etched if the material of the etching mask 118 is sensitive to the etching agents used (this is the case in the example embodiment described here where the etching mask 118 and the dielectric spacer 132 include SiO.sub.2).

[0093] Openings 138 are next produced through the etching mask 118, forming locations for producing second parts of the second electrodes of the diodes 102 (FIG. 1F). These openings 138 pass through the entire thickness of the etching mask 118 so that the bottom walls of the openings 138 are formed by the portions 124. This etching is for example of the ICP-RIE type.

[0094] A first electrically conductive material 140 is next deposited in the trenches 120, as well as on the top faces of the etching mask 118 and in the openings 138 (FIG. 1G). This first electrically conductive material 140 is conformally deposited, that is to say forming a layer of substantially constant thickness on the etching mask 118 and along the walls of the trenches 120 and of the openings 138. In the example embodiment described here, the first electrically conductive material 140 is formed by the deposition of a first layer of titanium with a thickness for example of between approximately 5 nm and 300 nm, followed by a deposition of a second layer of aluminum with a thickness of for example between approximately 50 nm and 1 μm. In a variant embodiment, the first electrically conductive material 140 is formed by a single layer of aluminum with a thickness of for example between approximately 50 nm and 1 μm.

[0095] The first electrically conductive material 140 deposited is in contact electrically with the lateral flanks of the portions 134 but also with the contact surfaces 136 that actively participate in the electrical contact with the semiconductor of the first layer 106 in addition to the contact with the lateral flanks of the portions 134. The electrically conductive material 140 is also in contact with the portions 124 at the bottom walls of the openings 138. These electrical contacts are intended to form electrical contacts between the p-n junctions and the anodes and cathodes of the diodes 102.

[0096] As shown in FIG. 1H, a second electrically conductive material 142 is deposited by filling the remaining volume of the trenches 120 and of the openings 138. In FIG. 1H, the thickness of this second electrically conductive material 142 is such that it also covers the parts of the first electrically conductive material 140 disposed on the etching mask 118. The second electrically conductive material 142 is for example copper, which can be formed by the implementation of a full-wafer electrochemical deposition (ECD), that is to say on the whole of the structure previously produced.

[0097] Finally, the diodes 102 of the device 100 are completed by performing a chemical-mechanical planarization (CMP) eliminating the portions of the first and second electrically conductive materials 140 and 142 that project beyond the trenches 120 and the openings 138 and which are disposed on the etching mask 118. This planarization electrically insulates the portions of conductive material disposed in the trenches 120 vis-à-vis those disposed in the openings 138 (FIG. 1I). The portions of the electrically conductive materials 140 and 142 disposed in the trenches 120 form first electrodes 144 (corresponding to cathodes in the example embodiment described here) extending over the entire height of the mesa structures of the diodes 102 and which are electrically connected to the semiconductor portions 134. The portions of the electrically conductive materials 140 and 142 disposed in the openings 138 form second parts of the second electrodes 146 (corresponding to anodes in the example described here) electrically connected to the portions 124 corresponding to the first parts of the second electrodes 146. The second electrodes 146 are connected to the portions 126 at the top faces of these portions 126.

[0098] This planarization also forms a face 148 of the device 100 that is substantially planar and formed by the top faces of the electrodes 144, 146, of the dielectric spacer 132 and of the etching mask 118. This face 148 forms the rear faces of the diodes 102 at which electrical connections with the electrodes 144, 146 will be made.

[0099] By means of the dielectric spacer 132, the first electrodes 144 are well insulated electrically from the semiconductor portions 124, from the second electrodes 146 and from the portions 128 forming the active regions of the diodes 102.

[0100] In order to guarantee electrical insulation between the electrodes 144, 146 of the diodes 102, and to avoid the presence of parts of the electrically conductive materials 140 and 142 electrically connecting one or more of the first electrodes 144 with one or more of the second electrodes 146, the planarization step may advantageously be performed until an overetching of the portions of the electrically conductive materials 140 and 142 disposed in the trenches 120 and in the openings 138 is achieved with respect to the dielectric materials of the dielectric spacer 132 and of the etching mask 118, forming, in the electrodes 144, 146, hollows at the top faces of these electrodes. These hollows may have a depth, with respect to the plane of the top face 148, of between approximately 5 nm and 150 nm. This overetching may be obtained by acting on the etching selectivity that exists between the dielectric materials of the spacer 132 and of the etching mask 118 and the electrically conductive materials 140 and 142. The CMP implemented has a different abrasion speed according to the materials and, in the method described here, the abrasion of the electrically conductive materials 140 and 142 is more rapid than the abrasion of the dielectric materials of the spacer 132 and of the etching mask 118. This results, at the top face 148 of the device 100, in a removal of the materials 140, 142 with respect to the dielectric spacer 132 and to the etching mask 118. Thus the electrodes 144, 146 of the diodes 102 remain perfectly isolated from each other by virtue of an intrinsic property of the planarization used. Such overetching may also be implemented by an RIE etching.

[0101] The substantially flat surface obtained at the top face 148 of the device 100 makes it possible to easily hybridize the matrix of diodes 102 produced with any type of connection element such as an electronic circuit, and makes it possible in particular to perform such hybridization by direct bonding, also referred to as molecular adhesion bonding, of the matrix of diodes 102 to the electronic circuit without using inserts, such as microbeads, between the matrix of diodes 102 and the electronic circuit. Direct bondings of the metal-metal and dielectric-dielectric type made in this case have the advantage of being impervious. The fact that these hollows are present at the top faces of the electrodes 144, 146 does not pose any problem for implementation of such direct bonding since, during this direct bonding, the materials of these portions expand and it is therefore possible to obtain very good contact between these electrodes and conductive elements of the electronic circuit. Details of implementation of such direct bonding are for example described in the document “Mechanisms of copper direct bonding observed by in-situ and quantitative transmission electron microscopy” by M. Martinez et al., Thin Solid Films 530 (2013) 96-99.

[0102] As shown in FIG. 1J, the matrix of diodes 102 is transferred, at the top face 148 thereof, onto an interconnection substrate 150 including electrical contacts 152 and 154 to which the electrodes 144, 146 can be electrically connected, for example via direct bonding as described above. This interconnection substrate 150 may be an electronic circuit on to which the matrix of diodes 102 is transferred.

[0103] The method here described and the substantially flat surface obtained at the top face 148 of the device 100 is also compatible with the conventional hybridization methods using for example inserts, such as microbeads or microtubes, for hybridizing the matrix of diodes 102.

[0104] After this transfer, the first substrate 104 can be removed, thus leaving clear a front face 156 of the diodes 102 through which the light is intended to enter or leave (leave in the example described here, where the diodes 102 are LEDs). The type of removal implemented depends in particular on the nature of the first substrate 104. For example, in the case of a first sapphire substrate 104, this can be removed by lift-off. It is also possible for the first substrate 104 to be removed by grinding, or by selective etching.

[0105] In order to illustrate the lateral etching implemented during the method described above, FIGS. 2A and 2B show images obtained by electron microscopy during such lateral etching.

[0106] FIG. 2A shows semiconductor mesa structures 10 with a geometry similar to those formed by the portions 124, 126, 128, 130 and 134 and the etching mask 118 after having etched the trenches 120. FIG. 2B shows the contact surface 136 obtained by the partial lateral removal of the etching mask 118 after having implemented an isotropic lateral etching, here by chemical method.

[0107] A description is given below of the steps of a method for producing an electronic device 100 according to a second embodiment. In the second embodiment described here, the device 100 includes a plurality of diodes 102 which are, in this second embodiment, light-emitting diodes.

[0108] The steps previously described in relation to FIGS. 1A and 1B are first of all implemented.

[0109] The dielectric spacer 132 is next produced in the trenches 120. Unlike the first embodiment in which the dielectric spacer 132 is produced by depositing a single thick layer of dielectric material, the dielectric spacer 132 is here produced by conformally depositing a layer 133 of a first dielectric material, this layer 133 in particular covering, in the trenches 120, the side walls of the portions 124, 126, 128 and 130 and of the etching mask 118. A layer 135 of a second dielectric material is next deposited by covering the layer 133. The first and second dielectric materials are chosen so that the second dielectric material has an etching speed greater than that of the first dielectric material during the lateral etching a part of the dielectric spacer that is then implemented, that is to say the anisotropic etching of the spacers and the etching of the semiconductor layers. For example, the first dielectric material of the layer 133 may be SiO.sub.2 and the second dielectric material of the layer 135 may be SiN.

[0110] The portions of the layers 133 and 135 that do not cover the side walls of the trenches 120, that is to say those located on the etching mask 118 and those located at the bottom of the trenches 120, are removed by anisotropic etching, for example a dry etching such as an RIE etching. The remaining portions of these dielectric layers 133 and 135 form the dielectric spacer 132 that covers the side walls of the remaining portions 124, 126, 128 and 130 and of the etching mask 118 (see FIG. 3A). The difference in etching speed between the first and second dielectric materials during this anisotropic etching results in a difference in height between the layer 135 and the layer 133 after the manufacture of the dielectric spacer: the remaining portion of the layer 135 is smaller than the remaining portion of the layer 133.

[0111] A selective etching step may next be performed in order to remove part of the remaining portions of the layer 135. The structure obtained in this case is shown in FIG. 3B.

[0112] Another etching is next implemented in order to extend the trenches 120 as far as the first substrate 104, through portions of the second part 123 of the first layer 106 that are not covered by the dielectric spacer 132, that is to say not covered by the portions of the layers 133 and 135. At the end of this second etching, the trenches 120 also surround remaining portions 134 of the second part 123 of the first layer 106.

[0113] Implementation of this etching also removes the remaining portions of the layer 135. At the end of this etching, the dielectric spacer 132 is then formed only by the remaining portions of the layer 133. The surfaces left clear by the removal of the portions of the layer 135 form the contact surfaces 136 intended for the electrical contacts with the semiconductor of the portions 134. The structure obtained is therefore similar to that shown in FIG. 1E.

[0114] Before implementation of this etching extending the trenches, the height of the portions of the layer 135 that have been preserved is adapted according in particular to the thickness of the etching mask 118, the thicknesses of the various etched semiconductor layers, or the selectivity of etching of the various materials, and this for the purpose that throughout the etching extending the trenches the contact surfaces 136 are properly protected by the portions of the layer 135 and that, at the end of this etching, the portions of the layer 135 are properly removed.

[0115] In a variant embodiment, part of the remaining portion of the layer 135 may remain after the etching extending the trenches, which it is then necessary to remove by means of an anisotropic etching that is selective with respect to the material of the layer 133.

[0116] The diodes 102 and the device 100 are next completed as in the first embodiment, performing the various steps previously described in relation to FIGS. 1F to 1J.

[0117] In the first and second particular embodiments described above, the semiconductor portions 130, 134 are of the n type and the second semiconductor portions 126 are of the p type. In a variant, the semiconductor portions 130, 134 may be of the p type and the second semiconductor portions 126 may be of the n type, with in this case the portions of electrically conductive material disposed in the trenches 120 forming the anodes of the diodes 102 and the portions of electrically conductive materials disposed in the openings 138 forming, with the portions 124, the cathodes of the diodes 102.

[0118] Furthermore, in the first and second embodiments described here, the previous steps performed are such that the contact surfaces 136 are substantially perpendicular to the lateral walls of the remaining portions 124, 126, 128, 130 and 134. In a variant, according to the geometry required for the diodes 102 and therefore the etchings used, it is possible for the contact surfaces 136 not to be perpendicular to these side walls.

[0119] In addition, in the first and second embodiments described above, the device 100 includes a matrix of diodes 102 that are light emitting diodes, the microelectronic device 100 being able to form part of a display device with LEDs (screens, projector, image wall, etc.). This matrix of diodes 102 includes the first electrodes 144 that form one and the same electrode common to all the diodes 102, and each diode 102 includes a second electrode 146 making it possible to perform the individual addressing of each of the diodes 102.

[0120] In a variant, the microelectronic device 100 may include a matrix of diodes 102 that are photoreceiving diodes, or photodiodes. In this variant, the electrodes 144, 146 do not serve to supply current to the diodes 102 but serve to recover the currents photogenerated by the diodes 102.

[0121] In a variant, the device 100 may include, on the top face 148, a connection structure different from the interconnection substrate 150, forming the electrical connections of the diodes 102 and including first electrically conductive elements electrically connected to the first electrodes 144 of the diodes 102 and second electrically conductive elements electrically connected to the second electrodes 146 of the diodes 102. These electrically conductive elements of such a connection structure are electrically insulated from each other by dielectric elements the dimensions of which, in the plane of the face 148, are at least equal to those of the dielectric spacer 132 and of the etching mask 118 so that the electrically conductive elements do not form a short-circuit between the electrodes of the diodes 102.

[0122] In the embodiments described above, the diodes 102 produced form a matrix of diodes serving as a matrix of pixels of the device 100. In a variant, the diodes 102 may be produced alongside each other without forming a matrix of diodes and/or without regular spacings between them.