Semiconductor device

Abstract

The present invention includes a first semiconductor chip, a second semiconductor chip, a first inductor, a second inductor, a second capacitor, protective diodes, and a third inductor. A field effect transistor includes a gate terminal, a drain terminal, and a source terminal connected to a ground terminal. The second semiconductor chip includes an input terminal and an output terminal connected in a direct current manner, and includes a first capacitor connected to the input terminal and to the ground terminal. The first inductor is connected between the output terminal and the gate terminal. The second inductor includes a first terminal connected to the input terminal. The second capacitor is connected between a second terminal of the second inductor and the ground terminal. Protective diodes are connected in series in a forward direction, and each has a cathode, and an anode connected to the ground terminal. The third inductor is connected between the cathode and the second terminal.

Claims

1. A semiconductor device comprising: a first semiconductor chip including a field effect transistor including a gate terminal, a drain terminal, and a source terminal connected to a ground terminal; a second semiconductor chip including an input terminal and an output terminal connected to each other with a wire in a direct current manner, and including a first capacitor with one end connected to the wire and another end connected to the ground terminal; a first inductor connected between the output terminal and the gate terminal; a second inductor including a first terminal connected to the wire; a second capacitor formed on the second semiconductor chip, and connected between a second terminal of the second inductor and the ground terminal, the second terminal of the second inductor being a terminal opposite to the first terminal; at least one protective diode formed on the second semiconductor chip, and having an anode connected to the ground terminal; and a third inductor connected between a cathode of the at least one protective diode and the second terminal.

2. The semiconductor device according to claim 1, wherein the field effect transistor is a GaN-based HEMT, and the second semiconductor chip is made of any one substrate of a GaAs substrate, an InP substrate, a SiC substrate, and a high-resistance Si substrate.

3. The semiconductor device according to claim 2, wherein the at least one protective diode is a Schottky junction diode or a pn junction diode.

4. The semiconductor device according to claim 2, wherein the second inductor or the third inductor is a bonding wire.

5. The semiconductor device according to claim 2, wherein the first semiconductor chip and the second semiconductor chip are mounted in one package.

6. The semiconductor device according to claim 1, wherein the at least one protective diode is a Schottky junction diode or a pn junction diode.

7. The semiconductor device according to claim 6, wherein the second inductor or the third inductor is a bonding wire.

8. The semiconductor device according to claim 6, wherein the first semiconductor chip and the second semiconductor chip are mounted in one package.

9. The semiconductor device according to claim 1, wherein the second inductor or the third inductor is a bonding wire.

10. The semiconductor device according to claim 9, wherein the first semiconductor chip and the second semiconductor chip are mounted in one package.

11. The semiconductor device according to claim 1, wherein the first semiconductor chip and the second semiconductor chip are mounted in one package.

12. The semiconductor device according to claim 1, wherein the at least one protective diode comprises a plurality of protective diodes, and the plurality of protective diodes are connected in series in a forward direction.

13. A semiconductor device comprising: a first semiconductor chip including a field effect transistor including a gate terminal, a drain terminal, and a source terminal connected to a ground terminal; a second semiconductor chip including an input terminal and an output terminal connected to each other with a wire in a direct current manner, and including a first capacitor with one end connected to the wire and another end connected to the ground terminal; a first inductor connected between the output terminal and the gate terminal; a second inductor including a first terminal connected to the gate terminal; a second capacitor formed on the second semiconductor chip, and connected between a second terminal of the second inductor and the ground terminal, the second terminal of the second inductor being a terminal opposite to the first terminal; a plurality of protective diodes formed on the second semiconductor chip, connected in series in a forward direction, and each having an anode connected to the ground terminal; and a third inductor connected between a cathode of the plurality of protective diodes and the second terminal.

14. The semiconductor device according to claim 13, wherein the field effect transistor is a GaN-based HEMT, and the second semiconductor chip is made of any one substrate of a GaAs substrate, an InP substrate, a SiC substrate, and a high-resistance Si substrate.

15. The semiconductor device according to claim 14, wherein the plurality of protective diodes are a Schottky junction diode or a pn junction diode.

16. The semiconductor device according to claim 14, wherein the first semiconductor chip and the second semiconductor chip are mounted in one package.

17. The semiconductor device according to claim 13, wherein the plurality of protective diodes are a Schottky junction diode or a pn junction diode.

18. The semiconductor device according to claim 17, wherein the first semiconductor chip and the second semiconductor chip are mounted in one package.

19. The semiconductor device according to claim 13, wherein the first semiconductor chip and the second semiconductor chip are mounted in one package.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a circuit configuration of an amplifier according to a first embodiment.

(2) FIG. 2 is a circuit configuration of an amplifier for comparison.

(3) FIG. 3A is a voltage waveform applied to protective diodes according to the first embodiment. FIG. 3B is a voltage waveform applied to protective diodes according to a comparative example.

(4) FIG. 4 is another circuit configuration of an amplifier for comparison.

(5) FIG. 5 is a diagram of components mounted inside a package of a GaN-based HEMT incorporating a pre-match circuit according to the first embodiment.

(6) FIG. 6 is a diagram of components mounted inside a package of a GaN-based HEMT incorporating a pre-match circuit according to a second embodiment.

(7) FIG. 7 is a circuit configuration of an amplifier according to a third embodiment.

(8) FIG. 8 is a diagram of components mounted inside a package of a GaN-based HEMT incorporating a pre-match circuit according to the third embodiment.

(9) FIG. 9 is a modification example of a circuit configuration of an amplifier according to the third embodiment.

(10) FIG. 10 is a circuit configuration of an amplifier for comparison.

(11) FIG. 11 is a diagram of components mounted inside a package of a GaN-based HEMT incorporating a pre-match circuit according to comparison.

(12) FIG. 12 is an equivalent circuit of a GaN-based HEMT chip incorporating protective diodes according to comparison.

DESCRIPTION OF EMBODIMENTS

(13) A semiconductor device using a GaN-based HEMT chip and a pre-matching chip according to embodiments of the present invention will be described with reference to the drawings. Including the drawings described in the above, the same or corresponding components are denoted by the same reference signs, and repeating description may be omitted.

FIRST EMBODIMENT

(14) FIG. 1 illustrates a circuit configuration of a semiconductor device using a GaN-based HEMT chip and a pre-matching GaAs chip according to the first embodiment of the present invention. The scope of the illustration of FIG. 1 corresponds to a circuit inside the package 103 of FIG. 10. The difference from FIG. 10 is that a protective circuit is provided in the pre-matching chip 102. The protective circuit includes inductors 71 and 72, a parallel capacitor 43, and diodes 81 to 84 for ESD breakdown protection (hereinafter referred to as protective diodes). The protective circuit is connected between the gate terminal 5 of the package and the GND. In the protective circuit, sequentially from the gate terminal 5 to the GND, the inductor 71 is connected in series, the capacitor 43 is connected in parallel, the inductor 72 is connected in series, and each of the diodes 81 to 84 is connected in series in a forward direction. The configuration in that the gate terminals 5 and 7 are electrically connected with wiring of the like also in a direct current manner for the purpose of conducting a DC bias voltage is the same as FIG. 10.

(15) When such a negative surge that an electric potential of the gate terminal 7 becomes lower than the source, i.e., the GND potential, is applied between the gate and the source of the GaN-based HEMT 10, and a large reverse bias is applied between the gate and the source, connection is made so that anodes of the protective diodes correspond to the GND side and cathodes of the protective diodes correspond to the gate terminal 5 or 7 side so that the protective diodes 81 to 84 are turned on. Note that, when a positive surge is applied, a surge current flows in a forward direction with respect the Schottky junction between the gate and the source. Therefore, a transistor having a relatively large gate width as in the GaN-based HEMT 10 for an electric power amplifier is rarely broken down due to ESD of approximately HBM of 1 kV that is normally required. For this reason, FIG. 1 does not illustrate protective diodes for a positive surge.

(16) When a Si-based MOSFET is used instead of the GaN-based HEMT 10, a gate oxide film is broken down also with a positive surge because there is no path through which an electric current flows between the gate and the source. Therefore, when a Si-based MOSFET (metal⋅oxide film⋅semiconductor gate structure field effect transistor), or a gate of a MIS structure of GaN-based HEMTs is used, it is sufficient that series protective diodes of a reverse polarity be added in parallel to the protective diodes 81 to 84.

(17) The inductor 71, the parallel capacitor 43, and the inductor 72 form a low-pass filter, and is set such that signals of a fundamental frequency or more at the time of operation as an amplifier attenuate in a certain degree (e.g., 6 dB). As a result, as compared to a circuit configuration of a comparative example illustrated in FIG. 2, signals of a fundamental frequency conveyed from the gate terminal 5 to the gate terminal 7 of the GaN-based HEMT are not easily affected by parasitic resistance of the protective diodes due to the low-pass filter. A circuit of FIG. 2 has a circuit configuration corresponding to Patent Document 1 for comparison. Protective diodes 81 to 86 are directly connected to a node 302. As a result, signals conveyed from the gate terminal 5 to 7 are affected by parasitic resistance of the protective diodes 81 to 86, and reduces an electric power gain at the time of amplification operation. In contrast, the configuration of FIG. 1 is not easily affected by parasitic resistance due to the low-pass filter, and can suppress reduction in an electric power gain.

(18) Note that, although the inductors 71 and 72 are connected between the protective diodes 81 to 84 and the gate terminal 5, the inductors 71 and 72 do not affect transient response characteristics of the protective diodes in consideration of the following reason: if it is assumed that the fundamental frequency is 0.8 GHz or more, inductance values of the inductors 71 and 72 are at most several nanohenries to several tens of nanohenries, and a surge of HBM is an order of MHz.

(19) The configuration of FIG. 1 also has an effect capable of reducing the number of stages of series diodes, as compared to the comparative circuit of FIG. 2. FIGS. 3A and 3B respectively illustrate a voltage waveform applied to the protective diodes in the first embodiment and the comparative circuit. As illustrated in FIG. 3A, the voltage waveform of the node 301 applied to the protective diodes 81 to 84 attenuate due to the low-pass filter, as compared to the voltage waveform of the node 302 of FIG. 1. The number of stages of the protective diodes is usually set to a smallest number of stages that does not turn the protective diodes on even with a negative peak voltage Vpn1 of FIG. 3A. Specifically, an electric current Idio does not flow also with the voltage Vpn1. For example, in FIG. 3A, when a negative bias voltage Vbias=−1.0 V, a Schottky barrier potential 0.8 V, and negative peak voltages Vpn1=−2.4 V, Vpn2=−3.8 V, four stages is selected as the number of stages that does not turn the diodes on at the node 301, based on 0.7 V×four stages=2.8 V >1-2.4 V1 >0.7 V×three stages=2.1 V.

(20) In contrast, in the comparative circuit of FIG. 2, there is no attenuation of signals due to a low-pass filter, and therefore the negative peak voltage Vpn2 of the node 301 is large (the negative peak voltage Vpn2=−3.8 V). As a result, as illustrated in FIG. 3B, six stages are required as the number of stages of the protective diodes, based on 0.7 V×six stages=4.2 V >1-3.8 VI >0.7 V×five stages=3.5 V.

(21) Therefore, the number of stages of the protective diodes can be reduced in the circuit configuration of the first embodiment. Increase in the number of stages of the series protective diodes increases parasitic resistance. The increase in the parasitic resistance reduces tolerance of the protective diodes having the same junction area to ESD breakdown. In other words, to provide the six-stage series protective diodes with tolerance to ESD breakdown equivalent to that of the four-stage series protective diodes, a junction area 1.5 times as large is required per diode, and this also leads to increase in area occupied by the protective diodes.

(22) FIG. 4 illustrates a configuration of another comparative circuit to suppress reduction in an electric power gain. This configuration is based on a concept similar to that described in Patent Document 2. In FIG. 4, an inductor 91 and a capacitor 44 connected in series are connected in parallel to the protective diodes 81 to 86 between the node 302 and the GND. The capacitor 44 is a DC blocking capacitor, and may be considered to be short-circuited for a fundamental frequency or more of the amplifier. The resistance 32 and the capacitor 45 denoted by the broken line respectively indicate an equivalent parasitic resistance and an equivalent capacitor of the protective diodes 81 to 86. When the inductance of the inductor 91 is set to resonate in parallel with the capacitor 45 for the fundamental frequency, the impedance of a path seen from the node 302 in the direction of the protective diodes becomes sufficiently higher than the impedance seen from the node 302 in the direction of the gate terminal 7. Therefore, a passing loss of an RF power conducted from the gate terminal 5 of the package toward the gate terminal 7 of the GaN-based HEMT 10 becomes smaller, and thus reduction in an electric power gain can be suppressed. However, actual protective diodes include the parasitic resistance 32, and an electric power loss occurs due to the parasitic resistance 32. Thus, the loss is larger as compared to the configuration of the first embodiment that can reduce the loss generated by the parasitic resistance due to the low-pass filter.

(23) FIG. 5 is an example of a diagram of components mounted inside the package of the GaN-based HEMT incorporating the pre-match circuit according to the first embodiment. The inductor 61 of FIG. 1 corresponds to wires 61a to 61d, the inductor 62 corresponds to wires 62a to 62d, and the inductor 63 corresponds to wires 63a to 63d. A GND of an element on the pre-matching chip 102 is a via hole 201, and is connected to a GND on a chip back surface. A source electrode of the GaN-based HEMT 10 is also similarly connected to a chip back surface through a via hole. The GaN-based HEMT 10 with a large gate width illustrated in FIG. 1 is implemented by connecting a plurality of unit gate widths in parallel, and thus as illustrated in FIG. 5, the GaN-based HEMT 10 in many cases include a plurality of gate terminal pads 7a to 7d and drain terminal pads 8a to 8d. A wire is connected to each of the plurality of pads, to thereby achieve the circuit of FIG. 1.

(24) The inductors 71 and 72 are made of spiral inductors that can be formed through a semiconductor process. The capacitors 41 and 42 are made of metal-insulator-metal (MIM) capacitors. The resistance 31 is made of a semiconductor channel resistor or a thin film resistor.

(25) It is desirable that a substrate having high-resistance characteristics be used for the pre-matching chip, considering that RF losses are reduced. It is desirable that the pre-matching chip can be formed through a semiconductor process, considering that the protective diode, inductors, capacitors, resistance, etc. can be formed on the substrate and that those components are manufactured in a small size. The substrate is further required to perform connection with an external GND. A via hole is more desirable than a bonding wire to reduce parasitic inductance occurring at the time of the connection. Thus, a process that can form a via hole is desirable. As a matter of course, a low cost is also an important index. Therefore, for the pre-matching chip, for example, a GaAs substrate, an InP substrate, a SiC substrate, and a high-resistance Si substrate are desirable. The GaAs substrate is excellent in that the GaAs substrate is easily manufactured in many of chemical compound manufacturers, and that the GaAs substrate is relatively inexpensive. The SiC substrate is excellent in that the SiC substrate has low thermal resistance, though being expensive, and that the protective diodes are not easily affected by heat generation of the GaN-based HEMT 10. The high-resistance Si substrate is excellent in that the high-resistance Si substrate is most inexpensive in mass production. The InP substrate is advantageous when a high-speed signal processing circuit or the like is also integrated in the pre-matching chip.

(26) As an example of the protective diode, an example of a GaAs-based Schottky junction diode is described above. This is because the GaAs-based Schottky junction diode is the most popular diode among GaAs-based chips. The protective diode may be a pn junction diode. When a pn junction of a GaAs-based chip is used, a junction barrier potential is approximately 1.2 V, which is higher than the Schottky junction barrier of approximately 0.7 V. Therefore, there is an effect capable of reducing the number of stages of series diodes.

(27) As an example of an amplifier transistor chip, an example of a GaN-based HEMT is described above. This is because a combination of a GaN-based HEMT chip and a pre-matching GaAs-based chip is most suitable in the present invention. Needless to say, similar effects can be achieved also with a GaAs-based FET and a Si-based or SiC-based MOSFET.

(28) As described above, to incorporate protective diodes in a pre-matching inexpensive chip, the semiconductor device according to the first embodiment provides a configuration in which increase in costs due to incorporation of a pre-match circuit and protective diodes in an amplifier GaN-based HEMT chip is reduced. In addition, by connecting the protective diodes through a low-pass filter, the semiconductor device according to the first embodiment achieves a protective function for ESD breakdown with a small number of stages of series diodes, and achieves an effect capable of suppressing reduction in an electric power gain. Therefore, the semiconductor device according to the first embodiment is suitable for an electric power amplifier for a base station for mobile phones, in which cost reduction and performance requirement are difficult.

SECOND EMBODIMENT

(29) FIG. 6 is an example of a diagram of components mounted inside the package of the GaN-based HEMT incorporating the pre-match circuit according to the second embodiment of the present invention. The difference from the diagram of mounted components of the first embodiment of FIG. 5 is that the inductors 71 and 72 of the pre-matching chip are implemented by bonding wires 71a and 72a, instead of the spiral inductors. The bonding wire usually has a cross-sectional area of a conductive part larger than that of the spiral inductor, and is thus advantageous in that parasitic resistance is small. Therefore, an electric power loss due to a low-pass filter formed by the inductors 71 and 72 and the capacitor 43 is small, and therefore reduction in an electric power gain in the first embodiment can further be suppressed. As compared to a case of using the spiral inductors occupying a surface of the pre-matching chip, it is also effective in chip area reduction. Other effects are the same as those of the first embodiment.

THIRD EMBODIMENT

(30) FIG. 7 illustrates a circuit configuration of a semiconductor device using a GaN-based HEMT chip and a pre-matching GaAs chip according to the third embodiment of the present invention, and FIG. 8 illustrates an example of a diagram of components mounted inside the package of the GaN-based HEMT incorporating the pre-match circuit according to the third embodiment. The scope of the illustration of FIGS. 3A and 3B corresponds to a circuit inside the package 103 of FIG. 9, similarly to FIG. 1 of the first embodiment. The difference from the first embodiment is that an inductor 64, other than the inductor 62, is provided from the gate terminal 7 of the GaN-based HEMT 10 toward the pre-matching chip 102, and ahead of that, the low-pass filter (71, 72, 43) and the protective diodes 81 to 84 are connected in series in a forward direction. The stabilizing resistor 31 and the capacitor 41 are not concerned with the essence of the present invention, and are not particularly illustrated. In the diagram of mounted components illustrated in FIG. 8, the inductor 64 is implemented by bonding wires 64a to 64d. Other part of FIG. 8 is similar to FIG. 5.

(31) At the time of high-efficiency operation of the electric power amplifier, the following configuration is in many cases employed; that is, input and output impedance of the amplifier element is set to certain impedance also for a harmonic in addition to a fundamental frequency. This harmonic processing range is referred to as harmonic termination. In FIG. 7, values of the inductor 64, the inductor 71, and the capacitor 43 are adjusted to set second harmonic impedance seen from the gate end 7 of the GaN-based HEMT 10 to the pre-matching chip 102 side to be sufficiently lower than a fundamental frequency impedance seeing the same direction. With this, efficiency at the time of amplification operation can be higher as compared to a case of not performing harmonic termination.

(32) At this time, influence of the parasitic resistance of the protective diodes 81 to 84 over the fundamental frequency and the second harmonic is reduced due to loading of the inductor 72. Therefore, reduction of an electric power gain due to addition of the protective diodes can be suppressed, similarly to the first embodiment. In the circuit configuration of the third embodiment, the low-pass filter (71, 72, 43) has a function of harmonic termination and also suppresses reduction in an electric power gain due to addition of the protective diodes. Therefore, as compared to a case of adding a harmonic termination circuit to the circuit configuration of the first embodiment, the circuit configuration of the third embodiment also has an effect of area reduction of the pre-matching chip 102. Note that other effects of the protective diodes are the same as those of the first embodiment.

(33) FIG. 9 is an example of a circuit configuration other than FIG. 7 according to the third embodiment. Unlike FIG. 7, the GaN-based HEMT 10 is divided into two transistors 10a and 10b, and each of the two transistors 10a and 10b is provided with pre-matching inductors 62a and 62b and capacitors 42a and 42b for a fundamental frequency. A path on the harmonic side is also similarly divided into two. Specifically, there are a path of an inductor 64a, an inductor 71a, a capacitor 43a, an inductor 72a, and protective diodes 81a to 84a, and a path of an inductor 64b, an inductor 71b, a capacitor 43b, an inductor 72b, and protective diodes 81b to 84b.

(34) In the diagram of mounted components of FIG. 8, harmonic processing paths are collected together as one by the bonding wires 64a to 64d to be connected to the inductor 71. In this case, however, a difference is generated between a path length from the wire 64a to the inductor 71 and a path length from the wire 64d to the inductor 71. When an operation frequency is high, this path length difference may expand the difference of harmonic impedances and may hinder the effect of efficiency improvement. In such a case, divided disposition of paths as in FIG. 9 reduces the difference between the harmonic impedances due to the path lengths, and can enhance the efficiency improvement effect. In FIG. 9, a path is divided into two, but may be further divided and similar effects can still be achieved.

EXPLANATION OF REFERENCE SIGNS

(35) 1: Input terminal

(36) 2: Output terminal

(37) 3: Gate bias terminal

(38) 4: Drain bias terminal

(39) 5: Gate terminal of package

(40) 6: Drain terminal of package

(41) 7: Gate terminal of GaN-based HEMT chip

(42) 8: Drain terminal of GaN-based HEMT chip

(43) 10: GaN-based HEMT

(44) 21-25: Transmission line

(45) 31-32: Resistance

(46) 41-45: Capacitor

(47) 51-55: Capacitor outside package

(48) 61-64: Inductor made of bonding wire

(49) 71-72: Inductor on pre-matching chip

(50) 81-86: Protective diode

(51) 101: GaN-based HEMT chip

(52) 102: Pre-matching chip

(53) 103: Outer frame of package

(54) 104: Base plate of package for mounting chip

(55) 301, 302: Internal node of pre-match circuit