Demodulator for an RFID circuit

Abstract

An RFID circuit and to a demodulator for an RFID circuit, the demodulator including an input and at least one output, a clock extractor connected to the input, a comparator connected to at least one output, a finite impulse response FIR filter arrangement connected to the input and connected to the comparator.

Claims

1. A demodulator for an RFID circuit, the demodulator comprising: an input and at least one output, a clock extractor connected to the input, a comparator connected to at least one output, and a finite-impulse response (FIR) filter directly connected between the input and the comparator, wherein the FIR filter is a discrete-time filter.

2. The demodulator according claim 1, wherein the FIR filter comprises at least one n-tap FIR filter having a number of n delay lines or a number of n taps.

3. The demodulator according to claim 2, wherein at least one n-tap FIR filter comprises at least 5 delay lines or taps.

4. The demodulator according to claim 2, wherein the number n of taps or delay lines is equal to or smaller than a ratio between a carrier frequency and a modulation frequency of a RF input signal provided at the input.

5. The demodulator according to claim 2, wherein at least one n-tap FIR filter comprises five taps, with each tap having a filter coefficient ci, with i=0, 1, 2, 3, or 4, wherein the coefficient c0 of the first tap equals 1 and wherein the coefficient c4 of the last tap equals −1.

6. The demodulator according to claim 5, wherein residual coefficients c1, c2, c3 of the at least one n-tap FIR filter equal 0.

7. The demodulator according to claim 2, wherein at least one n-tap FIR filter comprises numerous switched capacitors (C0, C1, C2, C3, C4).

8. The demodulator according to claim 1, wherein the FIR filter comprises a number of n n-tap FIR filters in an interleaved arrangement.

9. The demodulator according to claim 8, further comprising a multi-phase generator connected to the clock extractor and connected to the FIR filter.

10. The demodulator according to claim 9, wherein the multi-phase generator is individually connected to each n-tap FIR filter of the FIR filter.

11. The demodulator according to claim 9, wherein the multi-phase generator is configured to provide a first clock signal from the clock extractor to a first n-tap filter at a time t1, and the multi-phase generator is further configured to provide the first clock signal to at least a second n-tap filter at a time t1 plus a predefined time delay, wherein the time delay is determined by the clock frequency of the clock signal.

12. The demodulator of claim 1, wherein the FIR filter is coupled to the clock extractor.

13. A transponder front-end for an RFID circuit, the transponder front-end comprising: a first antenna node connectable to a first antenna pad, a second antenna node connectable to a second antenna pad, a clock recovery circuit connected to the first antenna node and to the second antenna node, a modulator connected to the first antenna node and to the second antenna node, and the demodulator according to claim 1, the demodulator being connected to the first antenna node and to the second antenna node.

14. An RFID circuit, comprising: a digital circuit, an antenna, and the transponder front-end according to claim 13, the transponder front-end being connected to the digital circuit and to the antenna.

15. A demodulator for an RFID circuit, the demodulator comprising: an input and at least one output, a clock extractor connected to the input, a comparator connected to at least one output, and a finite-impulse response (FIR) filter connected to the input and connected to the comparator, wherein the FIR filter is a discrete-time filter, and the FIR filter is coupled to the clock extractor.

16. A transponder front-end for an RFID circuit, the transponder front-end comprising: a first antenna node connectable to a first antenna pad, a second antenna node connectable to a second antenna pad, a clock recovery circuit connected to the first antenna node and to the second antenna node, a modulator connected to the first antenna node and to the second antenna node, and a demodulator connected to the first antenna node and to the second antenna node, wherein the demodulator includes an input and at least one output, a clock extractor connected to the input, a comparator connected to at least one output, a finite-impulse response (FIR) filter connected to the input and connected to the comparator.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) In the following an embodiment of a demodulator of a RFID circuit it is described in more detail, in which:

(2) FIG. 1 is a schematic block diagram of the RFID circuit,

(3) FIG. 2 is a schematic block diagram of the transponder front-end,

(4) FIG. 3 is a schematic block diagram of the demodulator of the transponder front-end,

(5) FIG. 4 is illustrative of a delayed clock input and the various taps of the FIR filter,

(6) FIG. 5 is a schematic illustration of a switched capacitor implementation of the FIR filter,

(7) FIG. 6 is another schematic illustration of a switched capacitor implementation of the FIR filter,

(8) FIG. 7 is a schematic illustration of numerous FIR filters in an interleaved configuration,

(9) FIG. 8 is a schematic illustration of a delayed clock input for a 5 tap FIR filter,

(10) FIG. 9 is a schematic illustration of five FIR filters in an interleaved configuration,

(11) FIG. 10 represents a specific switched capacitor implementation of a FIR filter,

(12) FIG. 11 represents a single channel FIR waveform diagram versus RF input of the FIR filter according to FIG. 10,

(13) FIG. 12 shows a single channel FIR waveform diagram versus FIR output

(14) FIG. 13 shows a normalized transfer function of the FIR filter and

(15) FIG. 14 shows the RF input versus the filtered output and the respective demodulator front-end output data.

DETAILED DESCRIPTION

(16) FIG. 1 is illustrative of an RFID circuit of an RFID tag according to the present. The RFID circuit 10 comprises an antenna 26, a transponder front-end 30, a digital circuit 12 with a memory 14, a reference circuit 16, a regulator 18, a rectifier 20, a limiter 22 and a ground generator 24. The transponder front-end 30 is a sub-circuit of the integrated tag-circuit 10 that itself is part of an RFID-tag. As shown in more detail in FIG. 2, the transponder front-end 30 comprises a first antenna-pad A1 and a second antenna pad A2, respectively. The transponder front-end 30 is furthermore provided with at least, as internal nodes, two nodes labelled aa1 and aa2 called first and second antenna nodes. The first antenna node aa1 is connected to the first antenna pad A1 and the second antenna node aa2 is connected to the second antenna pad A2.

(17) The transponder front-end 30 comprises a demodulator 100, a clock recovery circuit 200 and a modulator 300. Both antenna nodes aa1, aa2 are connected to respective first and second antenna pins a1, a2 of the demodulator 100, the clock recovery circuit 200 and the modulator 300, respectively.

(18) The transponder front-end 30 comprises some further pins, namely a transmit pin tx intended to be connected to a node driven by some other sub-circuit of the integrated tag-circuit, a receive pin rx intended to be connected to some node interfacing some other sub-circuit of the integrated tag-circuit, a clock pin ck intended to be connected to some node of the integrated tag-circuit interfacing some other sub-circuits of the integrated tag-circuit, a supply-pin labelled dd and intended to be connected to some node of the integrated tag-circuit carrying the voltage-supply and a ground pin labelled ss and connected to the node of the integrated tag-circuit carrying the reference-potential. The antenna-pads A1, A2 of the integrated tag-circuit are intended to be connected to the terminals of the tag's antenna 26.

(19) The transponder front-end 30 further comprises an internal node labelled tx′ and referred to as transmit-node, one further internal node labelled rx′ referred to as receive-node, one further internal node labelled ck′ referred to as clock-node, one further internal node labelled dd′ referred to as supply-node, one further internal node labelled ss′ referred to as ground-node, one further internal node labelled fr′ referred to as receive-freeze-node and one more internal node labelled ft′ and referred to as transmit-freeze-node.

(20) The first antenna node aa1 is connected to the transponder front-end's first antenna pin a1, the second antenna node aa2 is connected to the transponder front-end's second antenna pin a2. The said transmit-node tx′ is connected to a transponder front-end's transmit pin tx. The receive-node rx′ is connected to a transponder front-end's receive pin rx. The clock-node is connected to a transponder front-end's clock pin. The supply-node dd′ is connected to a transponder front-end's supply-pin dd and the ground-node ss′ is connected to the transponder front-end's ground pin ss.

(21) The modulator 300 has an electrical interface of at least two antenna pins labelled a1 and a2 referred to as first and second antenna pin and connected to the antenna nodes aa1 and aa2 respectively. The modulator 300 has one further pin labelled tx referred to as transmit pin and connected to the transponder front-end's transmit-node tx′. The modulator 300 comprises one further pin labelled ck referred to as clock pin and connected to the clock-node ck′. The modulator 300 comprises one further pin labelled ft referred to as transmit freeze pin and connected to the transmit-freeze-node ft′. The modulator 300 comprises one further pin labelled dd referred to as supply-pin and connected the supply-node dd′. The modulator 300 comprises one more pin labelled ss referred to as ground pin and connected the ground-node ss′.

(22) The demodulator 100 of the transponder front-end 30 comprises an electrical interface of at least the two pins labelled a1 and a2 and referred to as first and second antenna pins and connected to the antenna nodes aa1 and aa2, respectively. The demodulator 100 comprises one further pin labelled rx referred to as receive pin and connected to the receive-node rx′. The demodulator 100 comprises one further pin labelled ck referred to as clock pin and connected the clock-node ck′. The demodulator 100 comprises one further pin labelled fr referred to as receive freeze pin and connected to the receive-freeze-node fr′. The demodulator 100 comprises one further pin labelled dd referred to as supply-pin and connected to the supply-node dd′. The demodulator 100 comprises one more pin labelled ss referred to as ground pin and connected to the ground-node ss′.

(23) The transponder front-end 30 also comprises the clock recovery circuit 200 as a sub-circuit. The clock recovery circuit 200 comprises an electrical interface of at least two pins labelled a1 and a2 and referred to as first and second antenna pins and connected to the antenna nodes aa1 and aa2, respectively. The clock recovery circuit 200 comprises one further pin labelled ck referred to as clock pin and connected to the clock-node ck′. The clock recovery circuit 200 comprises one further pin labelled ft referred to as transmit freeze pin and connected to the transmit-freeze-node ft′. The clock recovery circuit 200 comprises one further pin labelled fr referred to as receive freeze pin and connected to the receive-freeze-node fr′. The clock recovery circuit 200 comprises one further pin labelled dd referred to as supply-pin and connected to the supply-node rx′. The clock recovery circuit 200 comprises one more pin labelled ss referred to as ground pin and connected to the ground-node ss′.

(24) The function of the modulator 300 is to modulate the amplitude of the signal on the tag coils during uplink communication, e.g. from a tag to a reader. Due to the mutual inductance between the reader coils and the tag coils the variation of this signal and hence of the voltage induces a variation of the induction field between the reader and the tag and produces a variation of voltage on the reader coils. The reader is able to demodulate the voltage variation on its coils and to decode the tag response. The modulator principle is based on the modulation of the impedance at the tag coils input.

(25) The function of the demodulator 100 is to extract the modulation signal sent by the reader received on the tag coils during downlink transmission. The demodulator principle is optimized for space and area reduction and performances. The entire system and hence the demodulator is not working in continuous time but is sampled. The sampling frequency is equal to the carrier frequency Fc. So the circuit is sampled every Tc=(1/Fc). Instead of comparing the absolute value of the envelope with its average or with a fix threshold, the demodulator circuit 100 detects the variation of the envelope itself. Here, three different cases are conceivable.

(26) In a first case the envelope level decreases from a first time t1 to a second time t1+Tc. In this case the output of the demodulator changes from logical ‘1’ to logical ‘0’. In a second case the envelope level increases from a first time t1 to the second time t1 +Tc. Then, the demodulator changes from logical ‘0’ to logical ‘1’. In a third case, wherein the envelope level does not change from the first time t1 to a second time t1+Tc the demodulator output is memorized.

(27) The demodulator 100 of the RFID circuit 10 as illustrated in FIG. 3 comprises an input 102, i.e. in form of two antenna nodes a1, a2 and further comprises at least one output 104, 106. The demodulator 100 comprises a comparator 130 and an FIR filter arrangement 145. The FIR filter arrangement 145 and the comparator 130 are arranged in series. An input of the FIR filter arrangement 145 is directly connected to the input 102 of the demodulator 100. An output of the FIR filter arrangement 145 is connected to a first input of the comparator 130. The comparator 130 comprises a second input connected to a reference, e.g. a voltage reference. The comparator 130 comprises an output 104 configured to provide data to a digital demodulator.

(28) The demodulator is generally not limited to the RFID circuit as shown in FIGS. 1 and 2 but can be used with many other RFID circuits as well.

(29) The demodulator 100 further comprises a clock extractor 110 and a multi phase generator 120. The clock extractor 110 and the multi phase generator 120 are arranged in series. An input of the clock extractor 110 is connected to the input 102. The clock extractor 110 and the multi phase generator 120 are arranged parallel to the FIR filter arrangement 145 and the comparator 130. The multi phase generator comprises a first output connected to the FIR filter arrangement 145. The multi phase generator 120 comprises a second output 106 forming a second output of the demodulator 100. The output 106 is configured to provide a clock signal to a digital demodulator.

(30) By means of the FIR filter arrangement 145 the variation of the envelope of the RF input signal can be measured so as to create a voltage at the first input of the comparator 130 that is proportional to the variation of the RF input signal. The comparator 130 is configured to compare the output of the FIR filter arrangement 145 with a fixed reference to generate an output signal or a data output.

(31) The FIR filter arrangement is implemented as a passive, discrete time n-tap passive FIR filter arrangement. The FIR filter arrangement 145 comprises numerous individual n-tap FIR filters 140, 141, 142, 143, 144 as schematically illustrated in FIGS. 7 and 9. The n-tap filters 140, 141, 142, 143, 144 may be arranged in parallel. As shown in FIG. 5, each n-tap FIR filter 140 comprises an input connectable to V.sub.in and hence to the input 102. The FIR filter 140 further comprises an output connected to V.sub.out and is hence connected to the first input of the comparator 130. The numerous FIR filters 140, 141, 142, 143, 144 are individually connected to the multi phase generator 120. They are driven in an interleaved mode. With the example of FIG. 9, wherein the FIR filter arrangement 145 comprises five individual n-tap FIR filters 140, 141, 142, 143, 144 each one of the n-tap FIR filters 140, 141, 142, 143, 144 is delayed to a neighboring filter 140, 141, 142, 143, 144 in the time domain by a clock cycle.

(32) For instance, the n-tap FIR filter 141 is delayed by a clock cycle compared to the n-tap FIR filter 140. The n-tap FIR filter 142 is delayed with regard to the n-tap FIR filter 141 by a clock cycle and so on. The number of n-tap FIR filters of the FIR filter arrangement 145 equals the number n of delay lines or the number n of taps of the individual n-tap FIR filters. If the n-tap FIR filter comprises for instance five taps or delay lines there are provided five individual five-tap FIR filters 140, 141, 142, 143, 144 in the FIR filter arrangement 145.

(33) In FIGS. 4 and 5 a switched capacitor implementation of a single n-tap FIR filter 140 is schematically illustrated. The FIR filter 140 comprises an input V.sub.in and an output V.sub.out. The FIR filter 140 comprises numerous condensators C.sub.0, C.sub.1 and C.sub.N-1, and hence a total number of up to N condensators. The condensators are arranged in parallel. Each condensator has a first node connectable to ground and has a second node connectable to V.sub.in and V.sub.out respectively. Each delay line or tap of the n-tap FIR filter 140 comprises one condensator and four switches altogether. Each tap comprises two input switches Φ.sub.0 and two output switches Φ.sub.sum.

(34) By closing the input switches Φ.sub.0 the first condensator C.sub.0 will be charged during a first clock cycle. Thereafter and during a second clock cycle a second condensator will be charged while the first condensator will be disconnected from the input V.sub.in. After n clock cycles each one of the available capacitors will be charged. After N clock cycles the output switches Φ.sub.SUM will be closed thus discharging all capacitors to generate a signal at the output V.sub.out.

(35) The phase diagrams 150 of FIGS. 4 and 8 illustrate the temporal behavior of the on and off phases of the individual switches Φ.sub.0 to Φ.sub.N-1 over time and the switching of the output switches Φ.sub.sum.

(36) The capacitance of the individual capacitors C.sub.0, . . . C.sub.N-1 defines so called FIR filter coefficients. In the switched capacitor implementation 146 of the FIR filter 140 as illustrated in FIG. 5 all FIR coefficients are positive.

(37) Contrary to the switched capacitor implementation 146 of FIG. 5, the configuration of FIG. 6 represents a switched capacitor implementation 148 with negative FIR coefficients. There, the output V.sub.out is connectable via the output switches Φ.sub.sum to a first node of the capacitors C.sub.0, . . . , C.sub.n-1. A second node of the capacitors C.sub.0, . . . , C.sub.n-1 is connected via the input switches Φ.sub.0, . . . , Φ.sub.n-1 to the input V.sub.in.

(38) With the positive FIR filter coefficient implementation as illustrated in FIG. 5 V.sub.in and V.sub.out are connected to one and the same node of the capacitors. With the negative FIR coefficient implementation as shown in FIG. 6 the input V.sub.in and the output V.sub.out are connected to different nodes of the capacitors C.sub.0, . . . , C.sub.n-1.

(39) In FIGS. 8 and 10 a specific implementation of an FIR filter 140 is illustrated. Here, the FIR filter 140 comprises five taps or five delay lines with filter coefficients C.sub.0=1 and C.sub.4=−1 with residual filter coefficients C.sub.1, C.sub.2, and C.sub.3 equal to 0. Here, the first delay line or tap of the FIR filter 140 is provided with a positive filter coefficient C.sub.0 and the last, hence the fifth delay line or tap is provided with a negative filter coefficient. Residual or other filter coefficients equal 0. Consequently, the switch capacitor implementation 147 of the respective FIR filter 140 only comprises two capacitors C.sub.0, C.sub.4 and respective input and output switches.

(40) As illustrated in FIG. 10, a first node of the first capacitor C.sub.0 is connectable to ground via an input switch Φ.sub.0 and Φ.sub.sum, respectively. A second node of the first capacitor C.sub.0 is connectable to the RF input via the input switch Φ.sub.0. The second node of the first capacitor C.sub.0 is connectable to the filter output FIR output via the output switch Φ.sub.sum. Here, the switched capacitor implementation of the first capacitor C.sub.0 corresponds to the switched capacitor implementation 146 as illustrated in FIG. 5. The other capacitor C.sub.4 of the switched capacitor implementation 147 is implemented to comprise a negative FIR coefficient. Accordingly, the first node of the capacitor C.sub.4 is connectable via the input switch Φ.sub.4 to ground and via a further output switch Φ.sub.sum to the FIR output. A second node of the capacitor C.sub.4 is connectable via another input switch Φ.sub.4 to the RF input and to ground via another output switch Φ.sub.sum.

(41) As illustrated by the corresponding phase diagram 150 as shown in FIG. 8 the input switches Φ.sub.4 are closed during a first clock cycle. During a subsequent second clock cycle, during a subsequent third clock cycle and during a subsequent fourth clock cycle none of the switches Φ.sub.0, Φ.sub.4 is closed. These switches remain open. During a fifth clock cycle the input switches Φ.sub.0 are closed and the capacitor Z.sub.0 will be charged. Thereafter all output switches Φ.sub.sum are closed in order to provide an output signal at and after the fifth clock cycle.

(42) With a single five-tap FIR filter 140, 141, 142, 143, 144 an output signal is provided at a reduced rate. Only every fifth clock cycle there will be provided a filtered signal at the output 104. In order to provide a signal at each clock cycle the FIR filter arrangement 145 comprises five n-tap filters 140, 141, 142, 143, 144 that are arranged and driven in an interleaved mode by the multi phase generator 120. Such an interleaved arrangement is illustrated in FIGS. 7 and 9. FIG. 7 represents a general interleaved arrangement of N individual n-tap FIR filters 140, . . . , 144. The block diagram of FIG. 9 represents an interleaved arrangement of five five-tap FIR filters 140, 141, 142, 143, 144 in the interleaved arrangement.

(43) In FIGS. 11 and 12 the single channel FIR waveforms are illustrated. In FIG. 11 a RF input 200 is illustrated as a dashed line. The voltage VC4 at the condensator C.sub.4 of the switched capacitor implementation 147 of FIG. 10 is illustrated by a bold dotted line 202 and the voltage VC0 provided at the capacitor C.sub.0 is illustrated in a bold dashed line over time 204. As illustrated in FIG. 11 the sampling of the condensator C.sub.4 starts at the first clock cycle. The respective point SP4 is indicated in FIG. 11. After the fifth clock cycle the sampling of the condensator C.sub.0 starts as indicated by sampling point SP0.

(44) In FIG. 12 the waveforms 202, 204 are voltage signals present at the capacitors C.sub.4, C.sub.0. They are again illustrated as waveforms 202, 204 respectively. In addition, the finite impulse response, hence the FIR output 206 is illustrated as a bold line. It provides a pulse of finite duration after or during the fifth clock cycle.

(45) In FIG. 13, a simulation of a transfer function of a FIR filter arrangement 145 comprising five n-tap interleaved FIR filters is illustrated. A dotted line 300 represents the normalized envelope magnitude of the down-converted input signal with Fcarrier/Fmodulation=4 over normalized frequency. The dash dotted line 302 shows a comparable output transfer function if the demodulator 100 were implemented by means of a differentiator, hence by a 2-tap FIR filter with c.sub.0=1 and c.sub.1=−1. The bold line 304 represents the output transfer function of the present 5-tap FIR filter arrangement 145. As illustrated the FIR filter arrangement 145 comprises a shape in the frequency domain that is somewhat equivalent to the down-converted input signal. Hence, the FIR filter arrangement 145 provides a rather precise and exact signal conversion. The further dash-dotted line 308 represents an output of a 4-tap FIR filter with filter coefficients c.sub.0,1,2,3=1.

(46) With the presently illustrated example the FIR filter arrangement is a band-bass filter combining the attenuation of the DC signal scope of the differentiator with the attenuation of the noise at half of the clock frequency (FS/2). The present choice of N-tap=5 is optimal for a signal with a ratio of the carrier frequency divided by the modualtion frequency Fcarrier/Fmod=4, since it minimizes the attenuation of the signal spectrum. Here, a notch of the filter at FS/4 corresponds to the notch of the down-converted signal.

(47) In FIG. 13 the spectrum of a periodic modulating signal 306 is illustrated, which may represent a possible signal in the ASK modulation for the RFID chip. Due to the minimum 4 time unit duration of the 0 the notch of the down-converted signal appears at FS/4. The 5-tap filter in this specific case is the preferred choice.

(48) Regarding the DC of the down-converted signal in the prior art it has been a common scope to attenuate it, e.g. with a differentiator, since it varies with the tag to reader distance and making the result of the demodulation dependent on it. The noise components at FS/2 are the most critical once since they are contributing to sample-to-sample noise, which is an unwanted variation between one signal sample and the following. Without the low-pass filtering this sample-to-sample noise would increase the error rate of the demodulator.

(49) In FIG. 14, the RF input 400 is shown in the time domain in comparison to the output 402 of the FIR filter arrangement 145. As the derivative of the envelope of the RF input 400 changes sign, the FIR output 402 switches from positive values to negative values. Accordingly and in the lower diagram 404 of FIG. 14 the demodulator front end output data as provided at the output of the comparator 130 is illustrated in the time domain. As shown there in comparison to the envelope of the RF input 400 the demodulator front and output data changes as the derivative of the envelope of the RF input is subject to a change.

LIST OF REFERENCE NUMERALS

(50) 10 RFID circuit 12 digital circuit 14 memory 16 reference circuit 18 regulator 20 rectifier 22 limiter 24 ground generator 26 antenna 30 transponder front-end 100 demodulator 102 input 104 data output 106 clock output 110 clock extractor 120 multi phase generator 130 comparator 140 FIR filter 141 FIR filter 142 FIR filter 143 FIR filter 144 FIR filter 145 FIR filter arrangement 146 switched capacitor implementation 147 switched capacitor implementation 148 switched capacitor implementation 150 input phase diagram 200 RF input signal 202 voltage waveform 204 voltage waveform 206 FIR output 300 down-converted input signal envelope 302 comparative differentiator output 304 FIR filter output 306 periodic signal 308 FIR filter output 400 RF input 402 FIR output 404 demodulator front end output data SP0 sampling point SP4 sampling point a1, a2 antenna pin aa1, aa2 antenna node A1, A2 antenna pad ss ground pin ss′ ground-node dd supply pin dd′ supply-node cke clock extraction pin cke′ clock-extraction-node ck clock pin ck′ clock node ckf fed-back clock pin ckf′ fed-back clock-node fc frequency control pin fc′ frequency-control-node ft transmit freeze pin ft′ transmit-freeze-node fr receive freeze pin fr′ receive-freeze-node