Active matrix display and method for driving an active matrix display

Abstract

A method for driving an active matrix display comprising a plurality of pixels, wherein each pixel comprises a drive transistor having a driver gate, is disclosed. The method comprises: receiving information of a desired image to be displayed; determining a compensated voltage for the driver gate for each pixel based on calibration data, wherein the calibration data comprises a set of individual calibration values applying to different pixels, and wherein the compensated voltage compensates for differences between pixels affecting a relation of an intensity of light output by the pixel as function of a difference between the voltage applied to the driver gate and a threshold voltage of the drive transistor; and outputting the compensated voltage for the driver gate for each of the pixels.

Claims

1. A method for driving an active matrix display, the display comprising a plurality of pixels arranged in an array, wherein each pixel comprises a drive transistor having a driver gate, and wherein a current through the drive transistor for causing an intensity of light output by the pixel is controlled as a function of a difference between a voltage applied to the driver gate and a threshold voltage of the drive transistor, the method comprising: receiving information of a desired image to be displayed, the information defining a light intensity to be output by each pixel of the active matrix display; determining, for each pixel, a compensated voltage for the driver gate as a function of a β of the drive transistor and a calibration value, wherein the calibration value is specified in calibration data stored in a memory and that is associated with the active matrix display, wherein the calibration data comprises sets of individual calibration values, wherein each set of calibration values is associated with a different pixel in the array and calibration values within each set of calibration values facilitate relating different intensities of light to different voltages applied to the driver gate of the pixel, wherein the calibration values for each pixel are specified to compensate for differences in β among the pixels associated with the different voltages, wherein β is defined as: $\beta =\frac{\mu C_{ox}}{2}*\frac{W}{L},$ wherein μ is a charge carrier mobility of the drive transistor, C.sub.ox is a gate oxide capacitance per unit area of the driver gate, W is a width of the driver gate, and L is a length of the driver gate; and outputting respective compensated voltage for the driver gate for each of the pixels in the active matrix display.

2. The method according to claim 1, wherein the calibration values of each set of calibration values are stored in a look-up table in the memory.

3. The method according to claim 2, wherein the determining of the respective compensated voltage comprises interpolating between calibration values received from the look-up table.

4. The method according to claim 1, wherein the sets of individual calibration values comprise respective values of β for each pixel of the plurality of pixels.

5. The method according to claim 4, wherein the sets of individual calibration values further comprise respective threshold voltage values, wherein each respective threshold voltage value defines a respective threshold voltage for a respective drive transistor of a respective pixel.

6. The method according to claim 4, wherein the determining of the respective compensated voltage comprises calculating the respective compensated voltage based at least on a desired light intensity to be output by the respective pixel and one of the respective values of β.

7. The method according to claim 6, wherein, when driving the drive transistor in a saturation region, the respective compensated voltage is calculated by the following formula: $V_{\mathrm{GS}}=\sqrt{\frac{I_{\mathrm{DS}}}{\beta }}+V_T,$ wherein V.sub.GS is the respective compensated voltage with respect to a source of the drive transistor, I.sub.DS is the current through the drive transistor causing the desired light intensity to be output by the pixel, and V.sub.T is the threshold voltage.

8. The method according to claim 1, wherein each pixel is formed by a two-transistor, one-capacitor (2T1C) circuit, comprising (i) the drive transistor, (ii) a select transistor for selectively connecting a dataline to the driver gate of the drive transistor, and (iii) a storage capacitor connected between the driver gate of the drive transistor and a source of the drive transistor for maintaining data provided to the driver gate.

9. The method according to claim 8, wherein the determining of the respective compensated voltage compensates for a variation of the threshold voltage.

10. The method according to claim 1, wherein each pixel is formed by a three-transistor, two-capacitor (3T2C) circuit, comprising (i) the drive transistor having the driver gate and a calibration gate, (ii) a first select transistor for selectively connecting a first dataline to the driver gate of the drive transistor, (iii) a calibrate transistor for selectively connecting a second dataline to the calibration gate of the drive transistor, (iv) a first storage capacitor connected between the driver gate of the drive transistor and a source of the drive transistor for maintaining data provided to the driver gate, and (v) a second storage capacitor connected between the calibration gate of the drive transistor and the source of the drive transistor for maintaining data provided to the calibration gate.

11. The method according to claim 10, further comprising measuring a threshold voltage for each pixel and storing a calibration gate voltage value for each pixel, wherein the calibration gate voltage value is set so that applying a voltage to the calibration gate in accordance with the calibration gate voltage value compensates for a variation of the threshold voltage.

12. The method according to claim 11, wherein the determining of the compensated voltage comprises calculating the compensated voltage based only on the light intensity to be output by the pixel and a constant value.

13. An active matrix display, comprising: a plurality of pixels arranged in an array, wherein each pixel comprises a drive transistor having a driver gate, and wherein a current through the drive transistor for causing an intensity of light output by the pixel is controlled as a function of a difference between a voltage applied to the driver gate and a threshold voltage of the drive transistor; a data storage unit configured to store calibration data, wherein the calibration data comprises a set of individual calibration values, and wherein respective individual calibration values in the set apply to different pixels in the array; and a controller unit configured to: receive information of a desired image to be displayed, the information defining a light intensity to be output by each pixel of the active matrix display; determine, for each, a compensated voltage for the driver gate as a function of a β of the drive transistor, and a calibration value, wherein the calibration value is specified in calibration data stored in a memory and that is associated with the active matrix display, wherein the calibration data comprises sets of calibration values, wherein each set of calibration values is associated with a different pixel in the array and calibration values within each set of calibration values facilitate relating different intensities of light to different voltages applied to the driver gate of the pixel, wherein the calibration values for each pixel are specified to compensate for differences in β among the pixels associated with the different voltages, wherein β is define as: $\beta =\frac{\mu C_{ox}}{2}*\frac{W}{L},$ wherein μ a charge carrier mobility of the drive transistor, C.sub.ox is a gate oxide capacitance per unit area of the driver gate, W is a width of the driver gate, and L is a length of the driver gate; and output respective compensated voltage for the driver gate for each of the pixels in the active matrix display.

14. The active matrix display according to claim 13, wherein each pixel comprises a light emitting diode, an organic light emitting diode, or a quantum dot light emitting diode for emitting light.

15. The active matrix display according to claim 13, wherein the drive transistors of the pixels are formed as thin-film transistors (TFT).

16. The active matrix display according to claim 13, wherein the calibration values of each set of calibration values is stored in a look-up table in the memory.

17. The active matrix display according to claim 13, wherein the sets of individual calibration values comprise respective values of β for each pixel of the plurality of pixels.

18. The active matrix display according to claim 17, wherein the sets of individual calibration values further comprise respective threshold voltage values, wherein each respective threshold voltage value defines a respective threshold voltage for a respective drive transistor of a respective pixel.

19. The active matrix display according to claim 17, wherein the determining of the respective compensated voltage comprises calculating the respective compensated voltage based at least on a desired light intensity to be output by the respective pixel and one of the respective values of β.

20. The active matrix display according to claim 19, wherein, when driving the drive transistor in a saturation region, the respective compensated voltage is calculated by the following formula: $V_{\mathrm{GS}}=\sqrt{\frac{I_{\mathrm{DS}}}{\beta }}+V_T,$ wherein V.sub.GS is the respective compensated voltage with respect to a source of the drive transistor, I.sub.DS is the current through the drive transistor causing the desired light intensity to be output by the pixel, and V.sub.T is the threshold voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic view of a cross-section of technology in an active matrix display according to an example embodiment.

(2) FIG. 2 is a top view of a drive transistor of a pixel.

(3) FIG. 3 is a schematic view of pixel circuitry according to a first example embodiment.

(4) FIG. 4 is a schematic view of pixel circuitry according to a second example embodiment.

(5) FIG. 5 is a schematic view of an active matrix display according to an example embodiment.

(6) FIG. 6 is a flow chart of a method according to an example embodiment.

DETAILED DESCRIPTION

(7) FIG. 1 illustrates a cross-section, illustrating technology which may at least partially make up a pixel 110 in an active matrix display. The pixel 110 comprises a drive transistor 120, having a driver gate 122, a source 124, and a drain 126. The drain 126 is connected to a cathode 132 of an organic light emitting diode (OLED) 130. The OLEDs of the pixels of an array may have a common anode 134. A voltage applied to the driver gate 122 may control a drain-to-source current and, hence, a current through the OLED 130 for controlling the light emitted by the OLED 130.

(8) It should be realized that the drive transistor 120 may be connected in alternative manners to the OLED. For instance, the source 124 may be connected to an anode of the OLED 130 and the OLEDs of the pixels of an array may then have a common cathode.

(9) In examples where light emission by the pixels is provided by OLEDs, an active matrix OLED (AMOLED) display is provided. Although OLEDs are mainly discussed here, it should be realized that the active matrix display may be applied to other types of light emitting elements arranged in an array and controlled by an active matrix. Light emitting elements driven by a current may be provided in a number of different manners, e.g., using light-emitting diodes (LEDs) or quantum dot light emitting diode (QLED), although an AMOLED display may provide faster switching speeds of the pixels.

(10) A topology for driving the OLEDs 130 of the pixels 110 may be arranged on a backplane of the display using thin film transistors. This may enable the AMOLED display to be flexible and to exhibit low power consumption, which makes use of the AMOLED display to be an interesting option in many applications.

(11) The transistors for controlling the light output by the pixels 110 may be p-type as well as n-type transistors. The backplane may comprise a thin-film transistor (TFT), for instance hydrogenated amorphous Si (a-Si:H), polycrystalline silicon, organic semiconductor, (amorphous) indium-gallium zinc oxide (a-IGZO, IGZO) TFT.

(12) The present disclosure may be applied to displays using active matrix, not being limited by a particular type of display. For instance, it may be applied to AMOLED displays, for instance RGB or RGBW AMOLED displays, which may comprise fluorescent or phosphorescent OLED, polymer or polydendrimers, high power efficiency phosphorescent polydendrimers, etc.

(13) FIG. 2 is a top view of the drive transistor 120, illustrating the driver gate 122, the source 124, and the drain 126.

(14) When manufacturing an array of pixels 110, the pixels 110 may be designed to have specific geometric dimensions. The array of pixels 110 may be designed to have identical characteristics so as to provide identical functionality.

(15) However, the manufacturing of the array of pixels 110 may not be perfect, such that process variations may cause pixels 110 to have geometric variations in the structure of the pixel 110. For instance, as illustrated in FIG. 2, a width W of the gate 122 may vary, and a length L of the gate 122 may vary. Further, a thickness t.sub.ox of a gate insulator 128 (see FIG. 1) may vary, and a dielectric constant ε.sub.ox may vary. This implies that a gate oxide capacitance per unit area C.sub.ox, given by:

(16) $C_{\mathrm{ox}}=\frac{{\mathrm{.Math.}}_{\mathrm{ox}}}{t_{\mathrm{ox}}}$
may also vary.

(17) When driving the drive transistor 120 in a saturation region, the drain-to-source current I.sub.DS may be expressed as:

(18) $I_{\mathrm{DS}}=\mu *C_{\mathrm{ox}}*\frac{W}{L}\frac{{\left(V_{\mathrm{GS}}-V_T\right)}^2}{2},$
where μ is a mobility of a charge carrier, V.sub.GS is a gate-to-source bias as controlled by an applied voltage to the driver gate 122 of the drive transistor 120, and V.sub.T is a threshold voltage of the drive transistor 120.

(19) When there is a variation in pixel characteristics, e.g., due to process variations in manufacturing of the array of pixels 110, a factor (herein denoted β) controlling a relation of the intensity of light output by the pixel 110 as a function of the difference between the voltage applied to the driver gate 122 and the threshold voltage of the drive transistor 120 may vary, wherein the factor β may be expressed as:

(20) $\beta =\frac{\mu *C_{\mathrm{ox}}}{2}*\frac{W}{L}.$

(21) In particular, when using TFT technology for the drive transistors 120, the threshold voltage of the drive transistor 120 may be changed over time and may be differently changed for different pixels 110, e.g., depending on light output by each pixel 110. The drive transistors 120 of the pixels 110 may experience a bias-stress effect, i.e., a time-dependent trapping of charges from the channel of the drive transistor 120 into localized defect states in a semiconductor substrate, in the gate dielectric, or at an interface between semiconductor and dielectric. The trapped charges do not contribute to the current through the drive transistor 120 but affect a charge balance of the drive transistor 120. Thus, in use of the drive transistor 120, there may be a time-dependent shift of the threshold voltage due to bias stress.

(22) Therefore, a threshold voltage may need to be estimated at regular intervals, e.g., by determining the drain-to-source current I.sub.DS based on a voltage V.sub.GS applied to the driver gate 122. However, according to the present disclosure, it is realized that if the β-factor varies for different pixels 110, estimation of the threshold voltage for threshold voltage compensation will only be relevant for a single level of the applied voltage V.sub.GS.

(23) Hence, according to the present disclosure, a result of a calibration measurement may be used. The calibration measurement may be quite extensive, as a plurality of measurements may be performed for each pixel 110 of the display. The calibration measurement may be performed after manufacturing of the display. This implies that the calibration measurement may be performed before the display is delivered to an end customer, and the results of the calibration measurement may be stored so as to allow the display to be correctly driven when in use. Alternatively or additionally, the calibration measurement may be regularly performed, e.g., once a week or once a month, so as to take into account any changes in behavior of driving the pixels 110.

(24) The calibration measurement may measure the drain-to-source current I.sub.DS based on a voltage V.sub.GS applied to the driver gate 122 for a plurality of different voltage levels.

(25) In one example embodiment, the drain-to-source current I.sub.DS is measured for each possible level of the voltage V.sub.GS. This implies that the voltage V.sub.GS for different drain-to-source currents I.sub.DS is determined. These results may be stored as a look-up-table (LUT), which may be used to determine which voltage V.sub.GS is required for a certain desired current I.sub.DS for each pixel 110. When driving the display, the voltage to be applied to a pixel 110 may be simply selected from the LUT.

(26) The LUT need not necessarily store data for each possible level of the voltage V.sub.GS. This implies that a memory space required by the LUT may be limited. When driving the display, the voltage to be applied to a pixel 110 may be based on selecting at least two voltage values from the LUT and performing an interpolation operation to find a suitable voltage between the values selected from the LUT.

(27) If a limited-size LUT is used, the calibration measurement need also not be performed for each possible level of the voltage V.sub.GS. Rather, calibration measurements may be performed only for the data points stored in the LUT.

(28) If fewer values are provided in the LUT, accuracy of the voltage to be applied to the pixel 110 may be decreased. Thus, a size of the LUT may be selected based on available memory capacity and a desired accuracy in applying a correct voltage to the driver gate 122 for achieving the desired intensity of light.

(29) When using the calibration measurements to form a LUT, it is not necessary to know a reason of variation between pixels 110 of the relation of the intensity of light output by the pixel 110 as a function of the voltage applied to the driver gate 122. Rather, the LUT may just be used as an information source for determining the voltage to be applied to the driver gate 122.

(30) However, according to an alternative example, the calibration measurements may be performed in order to determine the β-factor and the threshold voltage V.sub.T of each pixel 110. The calibration measurements may be performed for a number of different levels of the voltage V.sub.GS. The more levels used, the more accurate determination of the β-factor and the threshold voltage V.sub.T may be made.

(31) Based on the performed calibration measurements, an estimate of the β-factor and the threshold voltage V.sub.T may be determined for each pixel 110. The estimated β-factor and the estimated threshold voltage V.sub.T may be stored and used when determining the voltage to be applied to the driver gate 122. Then, the desired current I.sub.DS for a pixel 110 may be used as input, and the stored β-factor and threshold voltage V.sub.T may be used in calculation of the voltage to be applied to the driver gate 122.

(32) The voltage may be calculated as:

(33) $V_{\mathrm{GS}}=\sqrt{\frac{I_{\mathrm{DS}}}{\beta }}+V_T.$

(34) As mentioned above, the threshold voltage may vary over time. Thus, updated calibration measurements may be periodically performed in order to determine a threshold voltage V.sub.T of the drive transistor 120 of each pixel 110.

(35) Such updated calibration measurement may involve only a single measurement for each pixel 110, wherein a drain-to-source current I.sub.DS may be measured for a single level of the voltage V.sub.GS. The measurement may then be used in order to estimate the threshold voltage V.sub.T.

(36) If the threshold voltage is stored for each pixel 110, the stored value may be updated based on the updated calibration measurement. If a LUT is used relating drain-to-source currents I.sub.DS to levels of the voltage V.sub.GS, the LUT may be updated based on a fixed offset based on a change of the threshold voltage V.sub.T that may be determined using the updated calibration measurement.

(37) Referring now to FIG. 3, an example embodiment of pixel circuitry will be described. In FIG. 3, the pixel 110 is formed by a two-transistor, one-capacitor (2T1C) circuit. The pixel circuitry comprises the drive transistor 120 and a select transistor 140 for selectively connecting a dataline 150 to the driver gate 122 of the drive transistor 120.

(38) A signal on the dataline 150 may be provided through the select transistor 140 to the driver gate 122 of the drive transistor 120. The signal on the dataline 150 may thus provide data for opening a channel in the drive transistor 120 and hence driving a current through the OLED 130, which is connected to the drain 126 or source 124 of the drive transistor 120. Here, the OLED 130 is illustrated as connected to the source 124 and being connected between the drive transistor 120 and ground. However, it should be realized that the OLED 130 may alternatively be connected between a supply voltage (Vac) and the drive transistor 120. A light output by the OLED 130 may depend on a current level through the OLED 130, such that control circuitry may control the light output by the pixel 110 by controlling data provided on the dataline 150.

(39) The pixel circuitry may further comprise a storage capacitor 160, which is connected between the driver gate 122 of the drive transistor 120 and the source 124 of the drive transistor 120. This implies that data provided to the driver gate 122 may be maintained by the storage capacitor 160, e.g., to maintain an output by the pixel 110 in the display while driving data is provided to other pixels. The storage capacitor 160 may alternatively be connected to the drain 126 of the drive transistor 120.

(40) Although such a storage capacitor 160 may ensure a well-controlled driving of the pixel 110, use may alternatively be made of parasitic capacitance between the driver gate 122 and the source 124 or drain 126 of the drive transistor 120 to maintain data on the driver gate 122.

(41) Using the pixel circuitry illustrated in FIG. 3, a circuitry using a small number of components may be used for each pixel 110. This implies that each pixel 110 may be achieved in a small area, such that a large resolution of the display may be provided.

(42) Referring now to FIG. 4, another embodiment of a pixel circuitry will be described. In FIG. 4, the pixel circuitry is formed by a three-transistor, two-capacitor (3T2C) circuit. The pixel circuitry comprises the drive transistor 120 having the driver gate 122 and a calibration gate 129, a first select transistor 140 for selectively connecting a first dataline 150 to the driver gate 122 of the drive transistor 120, a calibrate transistor 170 for selectively connecting a second dataline 180 to the calibration gate 129 of the drive transistor 120.

(43) A signal on the first dataline 150 may be provided through the select transistor 140 to the driver gate 122 of the drive transistor 120. The signal on the first dataline 150 may thus provide data for opening a channel in the drive transistor 120 and hence driving a current through the OLED 130, which is connected to the drain 126 or source 124 of the drive transistor 120. Here, the OLED 130 is illustrated as being connected to the source 124 and being connected between the drive transistor 120 and ground. However, it should be realized that the OLED 130 may alternatively be connected between a supply voltage (Vac) and the drive transistor 120. A light output by the OLED 130 may depend on a current level through the OLED 130, such that control circuitry may control the light output by the pixel 110 by controlling data provided on the first dataline 150.

(44) A signal on the second dataline 180 may be provided through the calibrate transistor 170 to the calibration gate 129 of the drive transistor 120. The signal on the second dataline 180 may thus provide data for setting a voltage at the calibration gate 129 of the drive transistor 120. This voltage at the calibration gate 129 may be adapted to compensate for a variation in threshold voltage of the drive transistor 120, such that the data provided on the first dataline 150 may disregard variations in the threshold voltage for controlling the light output by the pixel 110. The current driven through the OLED 130 may thus depend on the voltage difference between the voltage at the driver gate 122 and the source 124 of the drive transistor 120 and depend also on the voltage difference between the voltage at the calibration gate 129 and the source 124 of the drive transistor 120, wherein the voltage level at the calibration gate 129 is provided in relation to a default threshold voltage assumed by the data provided on the first dataline 150.

(45) The pixel 110 may further comprise a first storage capacitor 160, which is connected between the driver gate 122 of the drive transistor 120 and the source 124 of the drive transistor 120. This implies that data provided to the driver gate 122 may be maintained by the storage capacitor 160, e.g., to maintain an output by the pixel 110 in the display while driving data is provided to other pixels. The first storage capacitor 160 may alternatively be connected to the drain 126 of the drive transistor 120.

(46) Although such a first storage capacitor 160 may help provide a well-controlled driving of the pixel 110, use may alternatively be made of parasitic capacitance between the driver gate 122 and the source 124 or drain 126 of the drive transistor 120 to maintain data on the driver gate 122.

(47) The pixel 110 may further comprise a second storage capacitor 190, which may be connected between the calibration gate 129 of the drive transistor 120 and the source 124 of the drive transistor 120. This implies that data provided to the calibration gate 129 may be maintained by the storage capacitor 190, e.g., to help ensure that calibration data is held on the calibration gate 129 for a substantial period of time without requiring that a new calibration signal is provided on the second dataline 180 to the calibration gate 129. The second storage capacitor 190 may alternatively be connected to the drain 126 of the drive transistor 120.

(48) Although such a second storage capacitor 190 may help ensure that the calibration data is held for a substantial period of time at the calibration gate 129, use may alternatively be made of parasitic capacitance between the calibration gate 129 and the source 124 or drain 126 of the drive transistor 120 to maintain data on the calibration gate 129. Also, if no second storage capacitor 190 is provided, calibration data may instead be provided more frequently to the calibration gate 129 to refresh the calibration data and maintain the pixel 110 calibrated to the threshold voltage of the drive transistor 120 of the pixel 110.

(49) Using the pixel circuitry illustrated in FIG. 4, a circuitry using a relatively small number of components may be used for each pixel 110. This implies that each pixel 110 may be achieved in a small area, such that a large resolution of the display may be provided.

(50) Further, the pixel circuitry illustrated in FIG. 4 may actively compensate for threshold voltage variation by providing a voltage at the calibration gate 129. This implies that, for calculation of the voltage to be applied to the driver gate 122 of the drive transistor 120 of a pixel 110, the threshold voltage need not be taken into account and the calculation may correspond to:

(51) $V_{\mathrm{GS}}=\sqrt{\frac{I_{\mathrm{DS}}}{\beta }}.$

(52) Also, if a LUT is used for determining the voltage to be applied to the driver gate 122, the LUT need not be updated or adjusted even if the threshold voltage of the pixel 110 is changed. Rather, the voltage at the calibration gate 129 may be changed and the same relation between the applied voltage and the source-to-drain current as provided in the LUT may be used.

(53) Referring now to FIG. 5, an active matrix display 200 comprising an array of pixels 110 arranged in rows and columns is schematically illustrated. The display 200 may comprise datalines 150 (and optionally datalines 180 depending on the pixel circuitry used), which run along a direction of the columns of the array. The display 200 further comprises control circuitry 202, which is connected to the datalines 150, 180. The control circuitry 202 may be arranged to provide data on the datalines 150, 180.

(54) The control circuitry 202 may be provided as a data driver integrated circuit, which provides components for generating data signals to the datalines 150, 180.

(55) The control circuitry 202 may be part of a controller unit 210, which may be configured to determine the data to be provided on the datalines 150, 180. Alternatively, the control circuitry may be connected to the controller unit 210 for receiving the data from the controller unit 210.

(56) The controller unit 210 may further be connected to a data storage unit 220 for storing calibration data of the pixels 110. Alternatively, the data storage unit 220 may be formed as an integrated memory in the controller unit 210.

(57) The display 200 may further comprise select lines 204 (and optionally calibrate lines 206 depending on the pixel circuitry used), which run along a direction of the rows of the array, perpendicular to the datalines 150, 180. The select lines 204 may provide signals for selectively activating the select transistors 140 in a row of pixels 110. Similarly, the calibrate lines 206 may provide signals for selectively activating the calibrate transistors 170 in a row of pixels 110.

(58) The display 200 may further comprise a driver circuitry 208 for driving the select lines 204 and the calibrate lines 206. The driver circuitry 208 may for instance be arranged as an integrated Gate-In-Panel (GIP) on the backplane of the display 200. According to an alternative, the driver circuitry 208 may be provided as dedicated silicon drivers.

(59) The controller unit 210 may have access to calibration data in the data storage unit 220. The calibration data may comprise a set of individual calibration values, wherein individual calibration values apply to different pixels 110 in the array.

(60) As explained above, the calibration data may be stored as a LUT, wherein a plurality of data values are provided for each pixel 110 for relating a desired intensity of light to be output by the pixel 110 to corresponding voltages to be applied to the driver gate 122.

(61) According to an alternative, the calibration data may be stored as one or more constant values for the pixel 110, which may be used in calculating the voltage to be applied to the driver gate 122 for achieving a desired intensity of light to be output by the pixel 110.

(62) The controller unit 210 may be configured to receive information of a desired image to be displayed. The controller unit 210 may, based on this information, determine a light intensity to be output by each pixel 110, e.g., in the form of the drain-to-source current I.sub.DS to be provided in the pixel 110.

(63) The controller unit 210 may use the drain-to-source current I.sub.DS as input to a process for determining the voltage to be applied to the driver gate 122 of the drive transistor 120 of the pixel 110. The process may be implemented as performing a look-up in a LUT, possibly in combination with a calculation of an interpolation value, or by directly calculating the voltage based on a known relation between the voltage to be applied and the drain-to-source current I.sub.DS.

(64) The determined voltage may be called a compensated voltage, since it takes into account variations between pixels 110 of the relation of the intensity of light output by the pixel as a function of the difference between the voltage applied to the driver gate and the threshold voltage of the drive transistor.

(65) When using a 2T1C pixel circuit, two parameters (1/β and V.sub.T) may be stored in the data storage unit 220 for every pixel 110. The calculation by the controller unit 210 may then comprise taking the desired drain-to-source current I.sub.DS as input and performing one multiplication (*1/β), followed by a square root and finally an addition (+V.sub.T).

(66) When using a 3T2C pixel circuit, two parameters (1/β and V.sub.BG) may be stored in the data storage unit 220 for every pixel 110. The back-gate voltage (V.sub.BG) may be applied to the calibration gate 120 and may hence be used for compensating threshold voltage variations. The calculation by the controller unit 210 may then comprise taking the desired drain-to-source current I.sub.DS as input and performing one multiplication (*1/β), followed by a square root.

(67) It should be realized that the compensated voltage value need not be directly used as the voltage applied to the driver gate 122. For instance, further processing of the data to be output on the datalines 150 may be provided, such as performing gamma correction.

(68) However, the gamma correction may in fact be combined with the calculation of the compensated voltage value in order to further decrease the number of operations to be performed by the controller unit. Thus, if a gamma correction, with y=2, is to be performed, the calculation by the controller unit 210 may be reduced to only one multiplication (*1/β).

(69) The controller unit 210 may be implemented in hardware or as any combination of software and hardware. For instance, the controller unit 210 may comprise a central processing unit (CPU) comprising software for providing functionality of the controller unit 210 in a general-purpose processor. Alternatively, the controller unit 210 may be implemented as firmware arranged in an embedded system of the display 200. As a further alternative, the controller unit 210 may be implemented as a special-purpose circuitry for providing specific logical operations. Thus, the controller unit 210 may, e.g., be provided in the form of an application-specific integrated circuit (ASIC), an application-specific instruction-set processor (ASIP), or a field-programmable gate array (FPGA).

(70) The data storage unit 220 may be implemented as any type of unit for storing data information, which may suitably be accessed and read by the controller unit 210. Thus, the data storage unit 220 may be implemented as a random access memory (RAM) a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, or the like.

(71) Referring now to FIG. 6, a method for driving an active matrix display 200 will be briefly described.

(72) At step 302, the method comprises receiving information of a desired image to be displayed. The information may be provided in any suitable manner, e.g., using any type of protocol for coding image information. Also, it should be realized that a video or a stream of sequential images to be displayed may be received, such that the display 200 may be controlled to output a sequence of images.

(73) The information may define a light intensity to be output by each pixel 110 of the active matrix display 200. However, the received information may first be decoded or processed in order to determine the light intensity to be output by each pixel 110 based on the received information.

(74) At step 304, the method further comprises determining a compensated voltage for the driver gate 122 for each pixel 110 based on calibration data. The compensated voltage may be determined as a voltage to be applied to the driver gate 122 in order for the desired light intensity to be output. The compensated voltage may be determined, e.g., by look-up in a LUT or by calculation using stored calibration data, as explained above.

(75) At step 306, the method further comprises outputting the compensated voltage for the driver gate 122 for each of the pixels 110 in the active matrix display 200. The compensated voltage value may thus be used as data to be provided to the datalines 150. Alternatively, further processing of the compensated voltage for the driver gate 122 may be provided in order to determine the data to be output on the datalines 150.

(76) In the above, the present disclosure has mainly been described with reference to a limited number of examples. However, as is readily appreciated, other examples than the ones disclosed above are equally possible within the scope of the present disclosure, as defined by the appended claims.