DELTA-SIGMA MODULATOR AND METHOD FOR REDUCING NONLINEAR ERROR AND GAIN ERROR

Abstract

Σ-Δ modulator and method for reducing nonlinear error and gain error. The Σ-Δ modulator includes: a plurality of sampling capacitors, configured to sample an input voltage or simultaneously sample an input voltage and a reference voltage signal; an operational amplifier; a plurality of switches, configured to select to sample the input voltage and the reference voltage signal; an integrating capacitor, configured to perform integration superposition on the input voltage and the reference voltage signal sampled by the sampling capacitors; and a control assembly, configured to control, to select to sample the reference voltage signal or simultaneously sample the input voltage and the reference voltage signal within a cycle, and to perform clock control on the sampling capacitors that simultaneously sample the input voltage and the reference voltage signal within a next cycle. During input sampling, Vref signals of two capacitors are simultaneously sampled to offset an overlarge area of the integrating capacitor, and a pseudo random number is used to control a polling timing of the capacitors to solve a problem of idle tone of a Σ-Δ modulator, so that the area of the integrating capacitor is effectively reduced, thereby reducing manufacturing costs of an integrated circuit and reducing an output swing.

Claims

1. A delta-sigma modulator, comprising: a plurality of sampling capacitors, configured to sample an input voltage or simultaneously sample an input voltage and a reference voltage signal; an operational amplifier; a plurality of switches, configured to select to sample the input voltage and the reference voltage signal; an integrating capacitor, configured to perform integration superposition on the input voltage and the reference voltage signal sampled by the sampling capacitors; and a control assembly, configured to control operation of the switches, to select to sample the reference voltage signal or simultaneously sample the input voltage and the reference voltage signal within a cycle, and to perform clock control on the sampling capacitors that simultaneously sample the input voltage and the reference voltage signal within a next cycle.

2. The delta-sigma modulator of claim 1, wherein the reference voltage signal is provided by a digital/analog converter.

3. The delta-sigma modulator of claim 2, wherein the digital/analog converter is controlled by the control assembly.

4. The delta-sigma modulator of claim 2, wherein a reference voltage provided by the digital/analog converter is distributed to any pair of sampling capacitors, or distributed to idle sampling capacitors while sampling an input voltage signal through operation of the switches.

5. The delta-sigma modulator of claim 1, wherein each sampling cycle comprises: ¼ cycle of input voltage signal sampling, ½ cycle of charge integration and ½ cycle of reference voltage signal sampling.

6. The delta-sigma modulator of claim 5, wherein the ½ cycle of charge integration comprises: ½ integration of the input voltage signal and ½ integration of the reference voltage signal, and the integration of the reference voltage signal is superimposed during the integration of the input voltage signal.

7. A method for sampling by the delta-sigma modulator of claim 1, comprising following steps of: S1. operating the switches to simultaneously sample the input voltage and the reference voltage signal by the sampling capacitors; S2. performing integration superposition on the input voltage and the reference voltage signal by the integrating capacitor; S3. operating the switches to input the reference voltage signal by the sampling capacitors for sampling; S4. performing integration superposition on the reference voltage signal by the integrating capacitor; and S5. repeating step S1 to step S4.

8. The method for sampling by delta-sigma modulator of claim 7, wherein at step S1, the input voltage is sampled by a capacitor pair, and the reference voltage signal is collected by idle capacitors.

9. The method for sampling by the delta-sigma modulator of claim 8, wherein at step S1, the control assembly controls any pair of switches in an input sampling circuit to be switched off to sample the input voltage; and controls any switch in a reference voltage signal sampling circuit to be switched off to sample the reference voltage signal.

10. The method for sampling by the delta-sigma modulator of claim 7, wherein at step S3, any pair of switches for the reference voltage signal are switched off to sample the reference voltage signal by a corresponding sampling capacitor pair.

11. The method for sampling by the delta-sigma modulator of claim 9, wherein at step S3, any pair of switches corresponding to the sampling of the reference voltage signal comprise or do not comprise any switch in the reference voltage signal sampling circuit at step S1.

12. The method for sampling by the delta-sigma modulator of claim 7, wherein the control assembly controls switching of the switches at step S1 to step S4 by using timing control to realize periodic sampling and integral coupling.

13. The method for sampling by the delta-sigma modulator of claim 12, wherein the control assembly controls the switching of the switches by controlling a pseudo-random number generation timing.

14. The method for sampling by the delta-sigma modulator of claim 7, wherein the control assembly controls a proportion of an operating cycle at step S1 to step S4.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0042] FIG. 1 is a technical principle diagram of the existing common Σ-Δ ADC:

[0043] FIG. 2 is a principle diagram of the Σ-Δ ADC in the existing patent:

[0044] FIG. 3 is a principle diagram of a circuit of the present application;

[0045] FIG. 4 is a diagram of a control timing of the present application;

[0046] FIG. 5 is a diagram of distribution of sampling capacitor pairs corresponding to FIG. 4;

[0047] FIG. 6 is a diagram of a control timing of the present application;

[0048] FIG. 7 is a diagram of distribution of sampling capacitor pairs corresponding to FIG. 6;

[0049] FIG. 8 is a diagram of a control timing of the present application;

[0050] FIG. 9 is a diagram of distribution of sampling capacitor pairs corresponding to FIG. 8;

[0051] FIG. 10 is a diagram of a control timing of the present application; and

[0052] FIG. 11 is a diagram of distribution of sampling capacitor pairs corresponding to FIG. 10.

DETAILED DESCRIPTION OF THE INVENTION

[0053] FIG. 1 shows an existing common Σ-Δ ADC, which adopts a most traditional oversampling technology with a principle of noise shaping, so that low-frequency noise is relatively small, thereby achieving a requirement of high precision, but the nonlinear problem is difficult to be solved.

[0054] With reference to FIG. 2, based on the Σ-ΔADC shown in FIG. 1, an input signal and a feedback signal are periodically changed at a fixed frequency, so that the nonlinear problem is basically solved. However, control is slightly complicated, and requirement on the integrator is very high due to the equalized timing, resulting in a large chip area, and meanwhile, the problem of Idle Tone is introduced.

[0055] In the present application, based on a common Σ-Δ ADC, the input signal and the feedback signal are specially processed to solve the nonlinear problem.

[0056] Specifically, in the present application, a Σ-Δ modulator includes:

[0057] a plurality of sampling capacitors, configured to sample an input voltage or simultaneously sample an input voltage and a reference voltage signal;

[0058] an operational amplifier;

[0059] a plurality of switches, configured to select to sample the input voltage and the reference voltage signal;

[0060] an integrating capacitor, configured to perform integration superposition on the input voltage and the reference voltage signal sampled by the sampling capacitors; and a control assembly, configured to control operation of the switches, to select to sample the reference voltage signal or simultaneously sample the input voltage and the reference voltage signal within a cycle, and to perform clock control on the sampling capacitors that simultaneously sample the input voltage and the reference voltage signal within a next cycle.

[0061] Preferably, the reference voltage signal is provided by a digital/analog converter. Preferably, the above digital/analog converter is controlled by the control assembly. Preferably, the reference voltage provided by the digital/analog converter is distributed to any pair of sampling capacitors or distributed to idle sampling capacitors while sampling an input voltage signal through operation of the switches.

[0062] Preferably, each sampling cycle includes: ¼ cycle of input voltage signal sampling, ½ cycle of charge integration and ½ cycle of reference voltage signal sampling.

[0063] Preferably, the ½ cycle of charge integration includes: ½ integration of the input voltage signal and ½ integration of the reference voltage signal, and the integration of the reference voltage signal is superimposed during the integration of the input voltage signal.

[0064] FIG. 3 shows a principle diagram of the application. The Σ-Δ modulator includes sampling capacitor pairs X, Y and Z, and the six capacitors are the same, configured to sample the input voltage or simultaneously sample the input voltage and the reference voltage signal.

[0065] The Σ-Δ modulator includes switch pairs S1X, S1Y, S1Z, S2X, S2Y, S2Z, S3X, S3Y and S3Z9, and each switch pair is switched off to control charging sampling of one pair of sampling capacitors.

[0066] The Σ-Δ modulator includes the operational amplifier. In the switch pairs S1X, S1Y, S1Z, S2X, S2Y, S2Z, S3X, S3Y and S3Z9, each switch pair is symmetrically distributed at a forward input end and a reverse input end of the operational amplifier. In the sampling capacitor pairs X, Y and Z, each sampling capacitor pair is also symmetrically connected with the forward input end and the reverse input end of the operational amplifier.

[0067] The Σ-Δ modulator includes a pair of integrating capacitors, one of which is connected with an output end and the forward input end, the other one of which is connected with the output end and the reverse input end.

[0068] The Σ-Δ modulator includes the control assembly, configured to control switching of the switch pairs S1X, S1Y, S1Z, S2X, S2Y, S2Z, S3X, S3Y and S3Z9, thereby switching the sampling capacitor pairs X, Y and Z.

[0069] A method for sampling by the Σ-Δ modulator includes the following steps of: S1. operating the switches to simultaneously sample the input voltage and the reference voltage signal by the sampling capacitors; S2. performing integration superposition on the input voltage and the reference voltage signal by the integrating capacitor; S3. operating the switches to input the reference voltage signal by the sampling capacitors for sampling; S4. performing integration superposition on the reference voltage signal by the integrating capacitor; and S5. repeating step S1 to step S4.

[0070] Preferably, at step S1, the input voltage is sampled by a capacitor pair, and the reference voltage signal is collected by idle capacitors.

[0071] Preferably, at step S1, the control assembly controls any pair of switches in an input sampling circuit to be switched off to sample the input voltage; and controls any switch in a reference voltage signal sampling circuit to be switched off to sample the reference voltage signal.

[0072] Preferably, at step S3, when any pair of switches for the reference voltage signal are switched off, the reference voltage signal is sampled by the corresponding sampling capacitor pair.

[0073] Preferably, at step S3, any pair of switches corresponding to the sampling of the reference voltage signal include or do not include any switch in the reference voltage signal sampling circuit at step S1.

[0074] Preferably, the control assembly controls switching of the switches at step S1 to step S4 by using timing control to realize periodic sampling and integral coupling.

[0075] Preferably, the control assembly controls the switching of the switches by controlling a pseudo-random number generation timing.

[0076] Preferably, the control assembly controls a proportion of an operating cycle of step S1 to step S4.

[0077] With reference to FIG. 4 to FIG. 11, one operating cycle is introduced. Input sampling and Vref sampling are performed at the same time. Specifically, switches No. 11 and No. 12 are switched off during the input sampling, and switch No. 33 is switched off at the same time, so that the sampling of input and signal feedback Vref are performed at clock term S1 at the same time, and then charges are integrated to the integrating capacitor at clock term I1. Next, the switches No. 31 and No. 32 are switched off at clock term S2, and the remaining feedback signal Vref is completely sampled, and then the charges are re-integrated to the integrating capacitor at clock 12. Sampling and integration are completed once. In FIG. 4, switches 11, 12 and 13 are switched off. In FIG. 6, switches 31 and 32 are switched off. In FIG. 8, switches 12, 13 and 21 are switched off. In FIG. 10, switches 22 and 23 are switched off.

[0078] Actual operation is not limited to the above operating timing and the above operating mode. Only one distribution of sampling capacitor pairs is given in the present application.

[0079] The sampling and the integration of the Vref are realized separately, thereby solving a problem of excessively high requirement on an amplifier. Meanwhile, a cycle of sampling and integration is controlled in a pseudo random number mode, so as to control a cycle timing of the switches, thereby controlling a whole process. The pseudo random number is generated by the control assembly.

[0080] The above embodiments only illustrate a principle and an effect of the present application, and are not used to limit the present application. Those skilled in the art may make modifications or changes on the above embodiments without violating the principle and scope of the present application. Therefore, all equivalent modifications or changes made by those of ordinary skills in the art without departing from the principle and technical ideas disclosed in the present application should still be included in the claims of the patent application.