Bonded body and insulating circuit substrate

Abstract

A bonded body is formed to configured to join a ceramic member formed of a Si-based ceramic and a copper member formed of copper or a copper alloy, in which, in a joint layer formed between the ceramic member and the copper member, a crystalline active metal compound layer formed of a compound including an active metal is formed on the ceramic member side.

Claims

1. A bonded body formed to configure to join a ceramic member formed of a Si-based ceramic and a copper member formed of copper or a copper alloy, wherein, a joint layer is formed between the ceramic member and the copper member, the joint layer includes a crystalline active metal compound layer and an alloy layer, the crystalline active metal compound layer, formed of a compound including an active metal, is formed on a ceramic member side, the alloy layer is formed between the active metal compound layer and the copper member, and the alloy layer containing, an alloy or an intermetallic compound including Cu—P based brazing material, is formed on a copper member side.

2. The bonded body according to claim 1, wherein a thickness of the active metal compound layer is in a range of 1.5 nm or more and 150 nm or less.

3. The bonded body according to claim 2, wherein the active metal compound layer contains one of an active metal nitride and an active metal oxide.

4. An insulating circuit substrate comprising: the bonded body according to claim 3, a ceramic substrate formed of the ceramic member; and a circuit layer formed of the copper member formed on one surface of the ceramic substrate.

5. The insulating circuit substrate according to claim 4, wherein a metal layer is formed on a surface of the ceramic substrate on an opposite side to the circuit layer.

6. The insulating circuit substrate according to claim 5, wherein the metal layer is formed of copper or a copper alloy.

7. The insulating circuit substrate according to claim 5, wherein the metal layer is formed of aluminum or an aluminum alloy.

8. An insulating circuit substrate comprising: the bonded body according to claim 2, a ceramic substrate formed of the ceramic member; and a circuit layer formed of the copper member formed on one surface of the ceramic substrate.

9. The insulating circuit substrate according to claim 8, wherein a metal layer is formed on a surface of the ceramic substrate on an opposite side to the circuit layer.

10. The insulating circuit substrate according to claim 9, wherein the metal layer is formed of copper or a copper alloy.

11. The insulating circuit substrate according to claim 9, wherein the metal layer is formed of aluminum or an aluminum alloy.

12. The bonded body according to claim 1, wherein the active metal compound layer contains one of an active metal nitride and an active metal oxide.

13. An insulating circuit substrate comprising: the bonded body according to claim 12, a ceramic substrate formed of the ceramic member; and a circuit layer formed of the copper member formed on one surface of the ceramic substrate.

14. The insulating circuit substrate according to claim 13, wherein a metal layer is formed on a surface of the ceramic substrate on an opposite side to the circuit layer.

15. The insulating circuit substrate according to claim 14, wherein the metal layer is formed of copper or a copper alloy.

16. The insulating circuit substrate according to claim 14, wherein the metal layer is formed of aluminum or an aluminum alloy.

17. An insulating circuit substrate comprising: the bonded body according to claim 1, a ceramic substrate formed of the ceramic member; and a circuit layer formed of the copper member formed on one surface of the ceramic substrate.

18. The insulating circuit substrate according to claim 17, wherein a metal layer is formed on a surface of the ceramic substrate on an opposite side to the circuit layer.

19. The insulating circuit substrate according to claim 18, wherein the metal layer is formed of copper or a copper alloy.

20. The insulating circuit substrate according to claim 18, wherein the metal layer is formed of aluminum or an aluminum alloy.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a schematic explanatory view of a power module using an insulating circuit substrate (bonded body) which is a first embodiment of the present invention.

(2) FIG. 2 is a schematic view of a joint interface between a circuit layer and a metal layer (copper member) and a ceramic substrate (ceramic member) of the insulating circuit substrate (bonded body) which is the first embodiment of the present invention.

(3) FIG. 3 is a flowchart showing a method for manufacturing an insulating circuit substrate (bonded body) which is the first embodiment of the present invention and a method for manufacturing a power module.

(4) FIG. 4 is an explanatory view showing a method for manufacturing an insulating circuit substrate (bonded body) which is the first embodiment of the present invention.

(5) FIG. 5 is a schematic explanatory view of a power module using an insulating circuit substrate (bonded body) which is a second embodiment of the present invention.

(6) FIG. 6 is a schematic view of a joint interface between a circuit layer (copper member) and a ceramic substrate (ceramic member) of an insulating circuit substrate (bonded body) which is the second embodiment of the present invention.

(7) FIG. 7 is a flowchart showing a method for manufacturing an insulating circuit substrate (bonded body) which is the second embodiment of the present invention and a method for manufacturing a power module.

(8) FIG. 8 is an explanatory view showing a method for manufacturing an insulating circuit substrate (bonded body) which is the second embodiment of the present invention.

(9) FIG. 9 shows observation results in the vicinity of the ceramic substrate of Example 1 of the present invention in the Examples.

(10) FIG. 10 shows line analysis results in the vicinity of the ceramic substrate in Examples. (a) is Comparative Example 1 and (b) is Example 1 of the present invention.

DESCRIPTION OF EMBODIMENTS

(11) A description will be given below of a bonded body and an insulating circuit substrate which are embodiments of the present invention with reference to the accompanying drawings. Here, each embodiment shown below is specifically described in order to facilitate understanding of the gist of the invention, and does not limit the invention unless otherwise specified. In addition, for convenience, in the drawings used in the following description, portions which are main parts may be enlarged and the dimensional ratios of each constituent component may not be the same as in practice, in order to make the features of the present invention easy to understand.

First Embodiment

(12) A description will be given below of a first embodiment of the present invention with reference to FIG. 1 to FIG. 4.

(13) The bonded body according to the embodiment of the present invention is an insulating circuit substrate 10 configured by joining a ceramic substrate 11 as a ceramic member formed of Si-based ceramics and a copper sheet 22 (circuit layer 12) as a copper member formed of copper or a copper alloy. Here, the Si-based ceramics refer to ceramics formed of a compound including an Si element.

(14) FIG. 1 shows the insulating circuit substrate 10 which is an embodiment of the present invention and a power module 1 using the insulating circuit substrate.

(15) The power module 1 is provided with the insulating circuit substrate 10, a semiconductor element 3 joined via a first solder layer 2 to one side (upper side in FIG. 1) of the insulating circuit substrate 10, and a heat sink 51 arranged via a second solder layer 8 on the other side (the lower side in FIG. 1) of the insulating circuit substrate 10.

(16) Here, the first solder layer 2 and the second solder layer 8 are, for example, Sn—Ag based, Sn—In based, or Sn—Ag—Cu based solder material.

(17) As shown in FIG. 1, the insulating circuit substrate 10 is provided with a ceramic substrate 11, a circuit layer 12 disposed on one surface (the upper surface in FIG. 1) of the ceramic substrate 11, and a metal layer 13 disposed on the other surface (the lower surface in FIG. 1) of the ceramic substrate 11.

(18) The ceramic substrate 11 is formed of an Si-based ceramic, for example, silicon nitride (Si.sub.3N.sub.4) having excellent heat dissipation.

(19) The thickness of the ceramic substrate 11 is set, for example, in the range of 0.2 to 1.5 mm and, in the present embodiment, 0.635 mm is used.

(20) The circuit layer 12 is formed to configured to join a copper sheet 22 formed of copper or a copper alloy to one surface of the ceramic substrate 11 as shown in FIG. 4. In the present embodiment, a rolled plate of oxygen-free copper is used as the copper sheet 22 forming the circuit layer 12. A circuit pattern is formed on the circuit layer 12 and one surface thereof (the upper surface in FIG. 1) is a mounting surface on which the semiconductor element 3 is mounted. Here, the thickness of the circuit layer 12 (copper sheet 22) is set in a range of 0.1 mm or more and 4.0 mm or less, and is set to 0.6 mm in the present embodiment.

(21) As shown in FIG. 4, the metal layer 13 is formed to configured to join a copper sheet 23 formed of copper or a copper alloy to the other surface of the ceramic substrate 11. In the present embodiment, a rolled plate of oxygen-free copper is used as the copper sheet 23 forming the metal layer 13. Here, the thickness of the metal layer 13 (the copper sheet 23) is set in a range of 0.1 mm or more and 4.0 mm or less, and is set to 0.6 mm in the present embodiment.

(22) The heat sink 51 is for cooling the insulating circuit substrate 10 described above and is a heat dissipating plate in the present embodiment. The heat sink 51 is desirably formed of a material having good thermal conductivity and is formed of A6063 (aluminum alloy) in the present embodiment.

(23) In the present embodiment, the heat sink 51 is joined via the second solder layer 8 to the metal layer 13 of the insulating circuit substrate 10.

(24) Here, an enlarged view of a joint interface between the circuit layer 12 (copper sheet 22) and the ceramic substrate 11 and between the metal layer 13 (copper sheet 23) and the ceramic substrate 11 is shown in FIG. 2.

(25) As shown in FIG. 2, a joint layer 30 is formed at the joint interface between the ceramic substrate 11 and the circuit layer 12 (copper sheet 22) and the joint interface between the ceramic substrate 11 and the metal layer 13 (copper sheet 23).

(26) As shown in FIG. 2, the joint layer 30 is provided with an active metal compound layer 31 formed of a compound including an active metal formed on the ceramic substrate 11 side and an alloy layer 32 formed between the active metal compound layer 31 and the circuit layer 12 (copper sheet 22) and the metal layer 13 (copper sheet 23).

(27) In the present embodiment, as described below, since the circuit layer 12 (copper sheet 22) and the metal layer 13 (copper sheet 23) are joined to the ceramic substrate 11 using a Cu—P-based brazing material 24 and a titanium material 25 including Ti as an active metal, the active metal compound layer 31 is formed of a titanium compound.

(28) The active metal compound layer 31 is formed of a crystalline titanium compound (titanium oxide or titanium nitride). It is possible to confirm the crystallinity of the active metal compound layer 31 by observing an electron diffraction pattern with a transmission electron microscope. In the present embodiment, the active metal compound layer 31 is formed of titanium oxide and a rutile-type electron diffraction pattern is observed.

(29) Here, in the present embodiment, the thickness of the active metal compound layer 31 is preferably in the range of 1.5 nm or more and 150 nm or less.

(30) In addition, the alloy layer 32 contains an alloy or an intermetallic compound including any of the components of the brazing material used during the joining. In the present embodiment, as described below, since the Cu—P-based brazing material 24, specifically, a Cu—P—Sn—Ni brazing material, is used, the alloy layer 32 has an alloy or an intermetallic compound including any of Cu, P, Sn, or Ni.

(31) Next, a description will be given of a method for manufacturing the insulating circuit substrate 10 according to the present embodiment described above with reference to FIG. 3 and FIG. 4.

(32) First, as shown in FIG. 4, the Cu—P-based brazing material 24, a titanium material 25, and the copper sheet 22 to be the circuit layer 12 are sequentially laminated on one surface (the upper surface in FIG. 4) of the ceramic substrate 11, while, the Cu—P-based brazing material 24, the titanium material 25, and the copper sheet 23 to be the metal layer 13 are sequentially laminated on the other surface (the lower surface in FIG. 4) of the ceramic substrate 11 (laminating step S01).

(33) In the present embodiment, as the Cu—P-based brazing material 24, a Cu—P—Sn—Ni brazing material is used which includes P in the range of 3 mass % or more and 10 mass % or less, which includes Sn, which is a low-melting point element, in the range of 7 mass % or more and 50 mass % or less, and which includes Ni in a range of 2 mass % or more and 15 mass % or less.

(34) Here, the thickness of the Cu—P-based brazing material 24 is in a range of 10 μm or more and 50 μm or less.

(35) In addition, in the present embodiment, the thickness of the titanium material 25 including Ti as an active metal element is in a range of 0.05 μm or more and 2 μm or less. Here, the titanium material 25 is preferably formed by vapor deposition or sputtering in a case where the thickness thereof is 0.1 μm or more and 1.0 μm or less, and a foil material is preferably used in a case where the thickness thereof is 1.0 μm or more.

(36) Next, the ceramic substrate 11, the Cu—P-based brazing material 24, the titanium material 25, the copper sheet 22, and the copper sheet 23 are charged into a vacuum heating furnace in a state of being pressed (pressure: 1 to 35 kgf/cm.sup.2 (0.1 MPa to 3.5 MPa)) in the laminating direction, heated, and joined (joining step S02).

(37) In the present embodiment, the pressure inside the vacuum heating furnace is in a range of 10.sup.−6 Pa or more and 10.sup.−3 Pa or less.

(38) In addition, the heating temperature is set in a range of 770° C. or higher and 980° C. or lower and the holding time at the heating temperature is set in a range of 5 minutes or more and 150 minutes or less. Furthermore, the heating rate from 600° C. to 730° C. is set in a range of 5° C./min or more and 20° C./min or less.

(39) Here, in a case where the thickness of the titanium material 25 including Ti which is an active metal element is less than 0.05 μm, there is a concern that the joining between the ceramic substrate 11 and the copper sheets 22 and 23 may be insufficient. On the other hand, in a case where the thickness of the titanium material 25 exceeds 2 μm, there is a concern that decomposition of the ceramic substrate 11 will be promoted and cracks may be generated during joining with ultrasonic waves.

(40) From the above, in the present embodiment, the thickness of the titanium material 25 is set in a range of 0.05 μm or more and 2 μm or less.

(41) In order to reliably join the ceramic substrate 11 and the copper sheets 22 and 23, the lower limit of the thickness of the titanium material 25 is preferably 0.3 μm or more, and more preferably 0.5 μm or more. On the other hand, in order to suppress the decomposition of the ceramic substrate 11, the upper limit of the thickness of the titanium material 25 is preferably 1.8 μm or less, and more preferably 1.5 μm or less.

(42) In a case where the thickness of the Cu—P-based brazing material 24 is less than 10 μm, there is a concern that the joining between the ceramic substrate 11 and the copper sheets 22 and 23 may be insufficient. On the other hand, in a case where the thickness of the Cu—P-based brazing material 24 exceeds 50 μm, there is a concern that decomposition of the ceramic substrate 11 will be promoted and cracks may be generated during joining with ultrasonic waves.

(43) From the above, in the present embodiment, the thickness of the Cu—P-based brazing material 24 is set in the range of 10 μm to 50 μm.

(44) In order to securely join the ceramic substrate 11 and the copper sheets 22 and 23, the lower limit of the thickness of the Cu—P-based brazing material 24 is preferably 15 μm or more, and more preferably 20 μm or more. On the other hand, in order to suppress the decomposition of the ceramic substrate 11, the upper limit of the thickness of the Cu—P-based brazing material 24 is preferably 40 μm or less, and more preferably 35 μm or less.

(45) In a case where the heating temperature is less than 770° C. in the joining step S02, there is a concern that the joining between the ceramic substrate 11 and the copper sheets 22 and 23 may be insufficient. On the other hand, in a case where the heating temperature exceeds 980° C. in the joining step S02, there is a concern that microcracks may be generated due to thermal deterioration of the ceramic substrate 11 and that cracking may be generated in the ceramic substrate 11 during joining with ultrasonic waves.

(46) From the above, in the present embodiment, the heating temperature is set in a range of 770° C. or higher and 980° C. or lower in the joining step S02.

(47) In order to securely join the ceramic substrate 11 and the copper sheets 22 and 23, the lower limit of the heating temperature in the joining step S02 is preferably 810° C. or higher, and more preferably 850° C. or higher. On the other hand, in order to suppress thermal deterioration of the ceramic substrate 11, the upper limit of the heating temperature in the joining step S02 is preferably 950° C. or lower, and more preferably 930° C. or lower.

(48) In a case where the holding time at the heating temperature is less than 5 minutes in the joining step S02, there is a concern that the joining between the ceramic substrate 11 and the copper sheets 22 and 23 may be insufficient. On the other hand, in a case where the holding time at the heating temperature exceeds 150 minutes in the joining step S02, there is a concern that decomposition of the ceramic substrate 11 will be promoted and cracks may be generated during joining with ultrasonic waves.

(49) From the above, in the present embodiment, the holding time at the heating temperature is set in a range of 5 minutes or more and 150 minutes or less.

(50) In order to securely join the ceramic substrate 11 and the copper sheets 22 and 23, the lower limit of the holding time at the heating temperature in the joining step S02 is preferably 15 minutes or more, and more preferably 30 minutes or more. On the other hand, in order to suppress decomposition of the ceramic substrate 11, the upper limit of the holding time at the heating temperature in the joining step S02 is preferably 120 minutes or less, and more preferably 100 minutes or less.

(51) In a case where the heating rate from 600° C. to 730° C. in the joining step S02 is less than 5° C./min, there is a concern that decomposition of the ceramic substrate 11 will be promoted and cracks may be generated during joining with ultrasonic waves. On the other hand, in a case where the heating rate from 600° C. to 730° C. in the joining step S02 exceeds 20° C./min, there is a concern that microcracks may be generated in the ceramic substrate 11 due to thermal shock and cracking may be generated in the ceramic substrate 11 during joining with ultrasonic waves.

(52) From the above, in the present embodiment, the heating rate from 600° C. to 730° C. in the joining step S02 is set in the range of 5° C./min or more to 20° C./min or less.

(53) In order to suppress the decomposition of the ceramic substrate 11, the lower limit of the heating rate from 600° C. to 730° C. in the joining step S02 is preferably 7° C./min or more, and more preferably 10° C./min or more. On the other hand, in order to suppress the generation of microcracks due to thermal shock, the upper limit of the heating rate from 600° C. to 730° C. in the joining step S02 is preferably 15° C./min or less, and more preferably 13° C./min or less.

(54) The insulating circuit substrate 10 according to the present embodiment is manufactured by the laminating step S01 and the joining step S02 above.

(55) Next, the heat sink 51 is soldered and joined to the other surface side of the metal layer 13 of the insulating circuit substrate 10 (heat sink joining step S03).

(56) Furthermore, the semiconductor element 3 is joined by soldering to one surface of the circuit layer 12 of the insulating circuit substrate 10 (semiconductor element joining step S04).

(57) Through the above steps, the power module 1 shown in FIG. 1 is produced.

(58) According to the insulating circuit substrate 10 (bonded body) of the present embodiment having the above configuration, since the active metal compound layer 31 formed of crystalline titanium oxide is formed on the ceramic substrate 11 side of the joint layer 30 formed between the ceramic substrate 11 and the circuit layer 12 and the metal layer 13, it is possible to suppress the generation of cracks starting from the active metal compound layer 31 and to suppress the ceramic substrate 11 from peeling from the circuit layer 12 and the metal layer 13 even in a case where ultrasonic waves are applied thereto.

(59) In addition, in the present embodiment, since the thickness of the active metal compound layer 31 is 1.5 nm or more, the strength in the vicinity of the joint interface of the ceramic substrate 11 is appropriately improved by the active metal compound layer 31 and it is possible to suppress the generation of cracking of the ceramic substrate 11 during loading of the thermal cycle. On the other hand, since the thickness of the active metal compound layer 31 is 150 nm or less, it is possible to suppress the thermal strain generated in the ceramic substrate 11 during loading of the thermal cycles without excessively forming the hard active metal compound layer 31 and to suppress the generation of cracking in the ceramic substrate 11 during loading of the thermal cycles. The lower limit of the thickness of the active metal compound layer 31 is preferably 3 nm or more, and more preferably 5 nm or more. On the other hand, the upper limit of the thickness of the active metal compound layer 31 is preferably 60 nm or less, and more preferably 20 nm or less.

(60) Further, in the present embodiment, since the ceramic substrate 11 is formed of silicon nitride (Si.sub.3N.sub.4), it is possible to manufacture the insulating circuit substrate 10 having excellent insulation and heat resistance.

(61) Furthermore, since the active metal compound layer 31 is formed of titanium oxide, the joining property between the ceramic substrate 11 and the circuit layer 12 and the metal layer 13 is improved and it is possible to further suppress the ceramic substrate 11 from peeling from the circuit layer 12 and the metal layer 13.

(62) Furthermore, in the present embodiment, since the metal layer 13 is formed on the surface of the ceramic substrate 11 on the side opposite to the circuit layer 12, it is possible to efficiently dissipate the heat generated in the semiconductor element 3. In addition, it is possible to suppress the generation of warpage of the ceramic substrate 11.

(63) In addition, since the metal layer 13 is formed of copper or a copper alloy, it is possible to realize the insulating circuit substrate 10 having excellent heat dissipation.

Second Embodiment

(64) Next, a description will be given of a second embodiment of the present invention. In addition, the same reference numerals are used in the description where the configuration is the same as the first embodiment and detailed description thereof is omitted.

(65) FIG. 5 shows a power module 101 provided with an insulating circuit substrate 110 according to the second embodiment of the present invention.

(66) The power module 101 is provided with the insulating circuit substrate 110, the semiconductor element 3 joined via the solder layer 2 to one surface (the upper surface in FIG. 5) of the insulating circuit substrate 110, and the heat sink 51 joined to a lower side of the insulating circuit substrate 110.

(67) As shown in FIG. 8, a circuit layer 112 is formed to configured to join a copper sheet 122 formed of copper or a copper alloy to one surface of the ceramic substrate 11. In the present embodiment, a rolled plate of oxygen-free copper is used as the copper sheet 122 forming the circuit layer 112. A circuit pattern is formed on the circuit layer 112, and one surface thereof (the upper surface in FIG. 5) is a mounting surface on which the semiconductor element 3 is mounted. Here, the thickness of the circuit layer 112 (copper sheet 122) is set in a range of 0.1 mm or more and 1.0 mm or less and is set to 0.6 mm in the present embodiment.

(68) As shown in FIG. 8, a metal layer 113 is formed to configured to join an aluminum sheet 123 formed of aluminum or an aluminum alloy to the other surface of the ceramic substrate 11. In the present embodiment, a rolled plate of aluminum (4N aluminum) having a purity of 99.99 mass % or more is used as the aluminum sheet 123 forming the metal layer 113. Here, the thickness of the metal layer 113 (aluminum sheet 123) is set in the range of 0.2 mm or more and 6 mm or less and is set to 2.0 mm in the present embodiment.

(69) In the present embodiment, the heat sink 51 is joined to the metal layer 113 of the insulating circuit substrate 110 using an Al—Si-based brazing material or the like.

(70) Here, an enlarged view of the joint interface between the circuit layer 112 (copper sheet 122) and the ceramic substrate 11 is shown in FIG. 6.

(71) As shown in FIG. 6, a joint layer 130 is formed at a joint interface between the ceramic substrate 11 and the circuit layer 112 (copper sheet 122).

(72) As shown in FIG. 6, the joint layer 130 is provided with an active metal compound layer 131 formed of a compound including an active metal formed on the ceramic substrate 11 side, and an alloy layer 132 formed between the active metal compound layer 131 and the circuit layer 112 (copper sheet 122).

(73) In the present embodiment, as described below, since the circuit layer 112 (copper sheet 122) and the ceramic substrate 11 are joined using the Cu—P-based brazing material 24 and the titanium material 25 containing Ti as an active metal, the active metal compound layer 131 is formed of a titanium compound.

(74) The active metal compound layer 131 is formed of a crystalline titanium compound (titanium oxide or titanium nitride). Here, it is possible to confirm the crystallinity of the active metal compound layer 131 by observing an electron diffraction pattern with a transmission electron microscope. In the present embodiment, the active metal compound layer 131 is formed of titanium oxide and a rutile-type electron diffraction pattern is observed.

(75) Here, in the present embodiment, the thickness of the active metal compound layer 131 is preferably in the range of 1.5 nm or more and 150 nm or less.

(76) In addition, the alloy layer 132 contains an alloy or an intermetallic compound including any of the components of the brazing material used during the joining. In the present embodiment, since the Cu—P-based brazing material 24, specifically, the Cu—P—Sn—Ni brazing material, is used, the alloy layer 132 has an alloy or an intermetallic compound including any of Cu, P, Sn, and Ni.

(77) Next, a description will be given of a method for manufacturing the insulating circuit substrate 110 according to the present embodiment described above with reference to FIG. 7 and FIG. 8.

(78) First, as shown in FIG. 8, the Cu—P-based brazing material 24, the titanium material 25, and the copper sheet 122 to be the circuit layer 112 are sequentially laminated on one surface (the upper surface in FIG. 8) of the ceramic substrate 11 (copper sheet laminating step S101).

(79) The same conditions as in the first embodiment apply to the thickness and the like of the Cu—P-based brazing material 24 and the titanium material 25.

(80) Next, the ceramic substrate 11, the Cu—P-based brazing material 24, the titanium material 25, and the copper sheet 122 are charged into a vacuum heating furnace in a state of being pressed (pressure: 1 to 35 kgf/cm.sup.2 (0.1 MPa to 3.5 MPa)) in the laminating direction, heated, and joined (copper sheet joining step S102).

(81) In the present embodiment, the pressure inside the vacuum heating furnace is in a range of 10.sup.−6 Pa or more and 10.sup.−3 Pa or less.

(82) In addition, the heating temperature is set in a range of 770° C. or higher and 980° C. or lower and the holding time at the heating temperature is set in a range of 5 minutes or more and 150 minutes or less. Furthermore, the heating rate from 600° C. to 730° C. is set in a range of 5° C./min or more to 20° C./min or less.

(83) Next, as shown in FIG. 8, on the other surface (the lower surface in FIG. 8) of the ceramic substrate 11, an Al—Si-based brazing material 27 and an aluminum sheet 123 to be the metal layer 113 are sequentially laminated (aluminum sheet laminating step S103).

(84) Here, in the present embodiment, a brazing material foil formed of an aluminum alloy containing Si in a range of 7 mass % or more and 12 mass % or less is used as the Al—Si-based brazing material 27 and the thickness of the Al—Si-based brazing material 27 is set in a range of 5 μm or more and 30 μm or less.

(85) Next, the ceramic substrate 11, the Al—Si-based brazing material 27, and the aluminum sheet 123 are charged into a vacuum heating furnace in a state of being pressed (pressure: 1 to 35 kgf/cm.sup.2 (0.1 MPa to 3.5 MPa)) in the laminating direction, heated, and joined (aluminum sheet joining step S104).

(86) In the present embodiment, the pressure inside the vacuum heating furnace is in a range of 10.sup.−6 Pa or more and 10.sup.−3 Pa or less.

(87) In addition, the heating temperature is in a range of 580° C. or higher and 650° C. or lower and the holding time at the heating temperature is in the range of 1 minute or more and 180 minutes or less.

(88) The insulating circuit substrate 110 which is the present embodiment is manufactured by the copper sheet laminating step S101, the copper sheet joining step S102, the aluminum sheet laminating step S103, and the aluminum sheet joining step S104 above.

(89) Next, the heat sink 51 is joined to the other surface of the metal layer 113 of the insulating circuit substrate 110 using an Al—Si-based brazing material (heat sink joining step S105).

(90) Furthermore, the semiconductor element 3 is joined by soldering to one surface of the circuit layer 112 of the insulating circuit substrate 110 (semiconductor element joining step S106).

(91) Through the above steps, the power module 101 shown in FIG. 5 is produced.

(92) According to the insulating circuit substrate 110 (bonded body) of the present embodiment having the configuration described above, since the active metal compound layer 131 formed of crystalline titanium oxide is formed on the ceramic substrate 11 side of the joint layer 130 formed between the ceramic substrate 11 and the circuit layer 112, it is possible to suppress the generation of cracks starting from the active metal compound layer 131 and to suppress peeling of the ceramic substrate 11 and the circuit layer 112 even when ultrasonic waves are applied thereto.

(93) In addition, in the present embodiment, since the thickness of the active metal compound layer 131 is in the range of 1.5 nm or more and 150 nm or less, it is possible to suppress the generation of cracking in the ceramic substrate 11 during loading of the thermal cycles.

(94) Here, the lower limit of the thickness of the active metal compound layer 131 is preferably 3 nm or more, and more preferably 5 nm or more. On the other hand, the upper limit of the thickness of active metal compound layer 131 is preferably 60 nm or less, and more preferably 20 nm or less.

(95) In addition, in the present embodiment, since the ceramic substrate 11 is formed of silicon nitride (Si.sub.3N.sub.4), it is possible to manufacture the insulating circuit substrate 110 having excellent insulation and heat resistance.

(96) Furthermore, since the active metal compound layer 131 is formed of titanium oxide, the joining property between the ceramic substrate 11 and the circuit layer 112 is improved and it is possible to further suppress peeling of the ceramic substrate 11 and the circuit layer 112.

(97) Furthermore, in the present embodiment, since the metal layer 113 is formed on the surface of the ceramic substrate 11 on the side opposite to the circuit layer 112, it is possible to efficiently dissipate the heat generated in the semiconductor element 3. In addition, it is possible to suppress the generation of warpage of the ceramic substrate 11.

(98) In addition, since the metal layer 113 is formed of aluminum or an aluminum alloy, it is possible to absorb thermal stress in the metal layer 113 and to suppress the load on the ceramic substrate 11 during the thermal cycle.

(99) A description was given above of the embodiments of the present invention, but the present invention is not limited thereto, and it is possible to make appropriate changes thereto without departing from the technical idea of the present invention.

(100) For example, in the present embodiment, a description was given in which a metal layer was formed on the surface of the ceramic substrate on a side opposite to the circuit layer; however, the present invention is not limited thereto and the metal layer may not be provided.

(101) In addition, the heat sink is not limited to the heat sink shown in the present embodiment, and the structure of the heat sink is not particularly limited.

(102) Furthermore, a buffer layer formed of aluminum, an aluminum alloy, or a composite material including aluminum (for example, AlSiC or the like) may be provided between the heat sink and the metal layer.

(103) In addition, in the present embodiment, a description was given in which a power module is configured by mounting a semiconductor element on an insulating circuit substrate; however, the present invention is not limited thereto. For example, an LED module may be configured by mounting an LED element on a circuit layer of an insulating circuit substrate, or a thermoelectric module may be configured by mounting a thermoelectric element on a circuit layer of an insulating circuit substrate.

(104) Furthermore, in the present embodiment, a description was given in which Ti is used as the active metal; however, the present invention is not limited thereto, and one type or two or more types of active metals selected from Ti, Nb, Hf, and Zr may be used.

(105) In addition, in the present embodiment, a description was given of the active metal compound layer as being formed of titanium oxide; however, the present invention is not limited thereto, and the active metal compound layer may be formed of titanium nitride.

(106) Furthermore, as a brazing material used when joining a ceramic substrate and a copper sheet, a description was given of a Cu—P—Sn—Ni brazing material as an example; however, the brazing material is not limited thereto, and other brazing materials may be used.

(107) Furthermore, in the present embodiment, a description was given in which the alloy layer has an alloy or an intermetallic compound including any of Cu, P, Sn, and Ni; however, the present invention is not limited thereto and any alloy or intermetallic compound including any of the components of the brazing materials used during joining is sufficient. For example, in a case where the brazing material contains Zn, an alloy or an intermetallic compound including Zn may be contained.

EXAMPLES

Example 1

(108) A copper sheet (6 mm×6 mm×0.3 mm thickness) formed of oxygen-free copper is sequentially laminated using a brazing material and an active metal material described in Table 1 on one surface of a ceramic substrate (26 mm×26 mm×0.32 mm thickness) formed of the material shown in Table 1 to form a laminate.

(109) Then, the laminate was put into a vacuum heating furnace in a state of being pressed under the load shown in Table 2, and heated to join a copper sheet to one surface of the ceramic substrate. The heating temperature and time were as shown in Table 2.

(110) In the manner described above, the joint bodies of the Examples of the present invention and the Comparative Examples were obtained. For the obtained joint bodies, the “Material and Crystallinity of Active Metal Compound Layer” and the “Ultrasonic Wave Joining Property” were evaluated.

(111) (Material and Crystallinity of Active Metal Compound Layer)

(112) Measurement was carried out using a transmission electron microscope (Titan ChemiSTEM, manufactured by FEI, accelerating voltage: 200 kV) at a magnification of 80,000 times to acquire element mapping of the N, O, and active metal element using the energy dispersive X-ray analysis method (NSS7 manufactured by Thermo Scientific). It was determined that an active metal compound layer was present in a case where the active metal element and N or O existed in the same region.

(113) Furthermore, in a case where lattice fringes were observed in the high-resolution image of the active metal compound layer and diffraction spots were confirmed in a diffraction image obtained by carrying out a fast Fourier transform on the high-resolution image, the active metal compound layer was determined to be crystalline.

(114) Table 2 shows the evaluation results.

(115) In addition, FIG. 9 shows a “transmission electron microscope observation of the joint interface between the ceramic substrate and the copper sheet” of Example 1 of the present invention and FIG. 10 shows the “line analysis results in the vicinity of the ceramic substrate”.

(116) (Presence or Absence of Peeling after Ultrasonic Wave Joining)

(117) Using an ultrasonic wave metal joining machine (60C-904, manufactured by Ultrasonic Engineering Co., Ltd.), a copper terminal (10 mm×5 mm×1 mm thick) was joined to the obtained bonded body by ultrasonic waves under the condition of a Co-plus amount of 0.3 mm.

(118) After joining, a product in which peeling occurred at the joint interface between the copper sheet and the ceramic substrate was evaluated as “C”. In addition, for products in which clear peeling was not confirmed, the joint interface between the copper sheet and the ceramic substrate was further inspected using an ultrasonic flaw detector (FineSAT200 manufactured by Hitachi Solutions, Ltd.), products where peeling was observed were evaluated as “B”, and products where peeling was not confirmed at either stage were evaluated as “A”. Table 2 shows the evaluation results.

(119) TABLE-US-00001 TABLE 1 Brazing Ceramic material Active metal substrate Thickness material Material Material (μm) Material Thickness Invention Si.sub.3N.sub.4 Cu-6.3 mass 20 Ti 0.3 Example 1 % P-9.3 mass % Sn-7 mass % Ni Invention Si.sub.3N.sub.4 Cu-6.3 mass 50 Ti 0.05 Example 2 % P-9.3 mass % Sn-7 mass % Ni Invention Si.sub.3N.sub.4 Cu-7 mass 20 Ti 2 Example 3 % P-15 mass % Sn-10 mass % Ni Invention Si.sub.3N.sub.4 Cu-7 mass 35 Zr 1.5 Example 4 % P-15 mass % Zn-3 mass % Mn Invention Si.sub.3N.sub.4 Cu-7 mass 10 Zr 1.8 Example 5 % P-15 mass % Sn-3 mass % Mn Invention Si.sub.3N.sub.4 Cu-7 mass 20 Ti 1.5 Example 6 % P-15 mass % Sn-10 mass % Ni Invention Si.sub.3N.sub.4 Cu-7 mass 35 Nb 1.8 Example 7 % P-15 mass % Zn-5 mass % Cr Invention Si.sub.3N.sub.4 Cu-7 mass 40 Hf 0.5 Example 8 % P Invention Si.sub.3N.sub.4 Cu-7 mass 15 Zr 0.3 Example 9 % P-15 mass % Sn-5mass % Cr Compara- Si.sub.3N.sub.4 Cu-7 mass 20 Ti 1.5 tive % P-15 mass Example % Sn-10 mass % Ni

(120) TABLE-US-00002 TABLE 2 Bonding conditions Evaluation Heating Active metal Pressing load temperature Heating rate Holding time compound layer Ultrasonic wave (MPa) (° C.) (° C./min) (min) Material Crystallinity bonding property Invention 5 950 15 120 Ti-0 Crystalline A Example 1 Invention 15 850 5 150 Ti-0 Crystalline A Example 2 Invention 1 770 13 15 Ti-0 Crystalline A Example 3 Invention 5 980 10 100 Zr-N Crystalline A Example 4 Invention 35 850 5 100 Zr-N Crystalline A Example 5 Invention 5 930 20 120 Ti-N Crystalline A Example 6 Invention 1 810 10 30 Nb-N Crystalline A Example 7 Invention 15 930 7 5 Hf-0 Crystalline A Example 8 Invention 3 950 13 120 Zr-0 Crystalline A Example 9 Comparative 5 930 3 120 Ti-0 Amorphous B Example

(121) In the Comparative Examples in which the active metal compound layer was amorphous, no peeling was observed at the joint interface between the copper sheet and the ceramic substrate after the joining with ultrasonic waves; however, peeling was confirmed as a result of performing an inspection with the ultrasonic flaw detector.

(122) On the other hand, in Example 1-9 of the present invention in which the active metal compound layer was crystalline, no peeling was observed at the joint interface of the copper sheet and the ceramic substrate after ultrasonic wave joining and peeling was not confirmed as a result of inspection using an ultrasonic flaw detector.

(123) In addition, referring to FIG. 9, in Example 1 of the present invention, it was confirmed that a crystalline active metal compound layer (rutile-type Ti—O layer) was formed at the interface portion of the ceramic substrate.

(124) Further, referring to FIG. 10, in Example 1 of the present invention, it was confirmed that the active metal concentration (Ti concentration) at the interface portion of the ceramic substrate was higher than in Comparative Example 1.

(125) From the above, according to the Examples of the present invention, it was confirmed that it is possible to provide a bonded body which is able to suppress peeling of a ceramic member and a copper member even when joining with ultrasonic waves is performed, and an insulating circuit substrate.

Example 2

(126) Using the brazing material and active metal material shown in Table 3, copper sheets formed of oxygen-free copper (37 mm×37 mm×0.8 mm thickness) are sequentially laminated on both surfaces of a ceramic substrate (40 mm×40 mm×0.32 mm thickness) formed of the material shown in Table 3 to form a laminate.

(127) Then, the laminate was put into a vacuum heating furnace in a state of being pressed with the load shown in Table 4 and heated to join the respective copper sheets to both surfaces of the ceramic substrate. The heating temperature and time were as shown in Table 4.

(128) As described above, the joint bodies of the Examples of the present invention were obtained. For the obtained joint bodies, the “Material and Crystallinity of Active Metal Compound Layer”, the “Thickness of Active Metal Compound Layer”, and the “Thermal Cycle Reliability” were evaluated. The “Material and Crystallinity of Active Metal Compound Layer” was evaluated in the same manner as in Example 1.

(129) (Thickness of Active Metal Compound Layer)

(130) Measurement was carried out using a transmission electron microscope (Titan ChemiSTEM, manufactured by FEI, accelerating voltage: 200 kV) at a magnification of 80,000 times to acquire element mapping of the N, O, and active metal element using the energy dispersive X-ray analysis method (NSS7 manufactured by Thermo Scientific). It was determined that an active metal compound layer was present in a case where the active metal element and N or O existed in the same region.

(131) The observation was performed in five visual fields, and the average value obtained by dividing the area of the range where the active metal element and N or O existed in the same region by the measured width was defined as the “Thickness of Active Metal Compound Layer”.

(132) (Thermal Cycle Reliability)

(133) Using a thermal shock tester (TSA-72ES manufactured by ESPEC CORP.), a thermal cycle of −50° C.×10 min.Math.175° C.×10 min in the gas phase was carried out for up to 2000 cycles.

(134) Every 200 cycles, the presence or absence of cracking in the ceramic substrate was determined by an interface inspection using an ultrasonic flaw detector (FineSAT200 manufactured by Hitachi Power Solutions Co., Ltd.).

(135) TABLE-US-00003 TABLE 3 Active metal Ceramic Brazing material material substrate Thickness Thickness Material Material (μm) Material (μm) Invention Si.sub.3N.sub.4 Cu-6.3 mass 20 Ti 0.3 Example % P-9.3 mass 11 % Sn-7 mass % Ni Invention Si.sub.3N.sub.4 Cu-6.3 mass 20 Ti 0.3 Example % P-9.3 mass 12 % Sn-7 mass % Ni Invention Si.sub.3N.sub.4 Cu-6.3 mass 20 Ti 0.3 Example % P-9.3 mass 13 % Sn-7 mass % Ni Invention Si.sub.3N.sub.4 Cu-7 mass 15 Zr 0.3 Example % P-15 mass 14 % Zn-5 mass % Cr Invention Si.sub.3N.sub.4 Cu-7 mass 15 Zr 0.3 Example % P-15 mass 15 % Zn-5 mass % Cr Invention Si.sub.3N.sub.4 Cu-7 mass 15 Zr 0.3 Example % P-15 mass 16 % Zn-5 mass % Cr Invention Si.sub.3N.sub.4 Cu-7 mass 40 Hf 0.5 Example % P 17 Invention Si.sub.3N.sub.4 Cu-7 mass 40 Hf 0.5 Example % P 18 Invention Si.sub.3N.sub.4 Cu-7 mass 40 Hf 0.5 Example % P 19 Invention Si.sub.3N.sub.4 Cu-7 mass 35 Nb 1.8 Example % P-15 mass 20 % Sn-5 mass % Cr Invention Si.sub.3N.sub.4 Cu-7 mass 35 Nb 1.8 Example % P-15 mass 21 % Sn-5 mass % Cr Invention Si.sub.3N.sub.4 Cu-7 mass 35 Nb 1.8 Example % P-15 mass 22 % Sn-5 mass % Cr

(136) TABLE-US-00004 TABLE 4 Bonding conditions Evaluation Heating Active metal compound layer Ceramic cracking Pressing load temperature Heating rate Holding Thickness cycle number (MPa) (° C.) (° C./min) time (min) Material Crystallinity (nm) (times) Invention 5 950 15 5 Ti-0 Crystalline 6.3 >2000 Example 11 Invention 5 950 15 20 Ti-0 Crystalline 14.5 >2000 Example 12 Invention 5 950 15 120 Ti-0 Crystalline 37.2 2000 Example 13 Invention 3 950 13 30 Zr-0 Crystalline 18.4 >2000 Example 14 Invention 3 950 13 90 Zr-0 Crystalline 37.3 1800 Example 15 Invention 3 950 13 120 Zr-0 Crystalline 45.5 1800 Example 16 Invention 15 850 7 5 Hf-0 Crystalline 1.5 >2000 Example 17 Invention 15 890 7 5 Hf-0 Crystalline 3.2 >2000 Example 18 Invention 15 930 7 5 Hf-0 Crystalline 6.8 >2000 Example 19 Invention 1 810 10 30 Nb-0 Crystalline 58.7 1600 Example 20 Invention 1 890 10 30 Nb-N Crystalline 99.5 1200 Example 21 Invention 1 970 10 30 Nb-N Crystalline 147.4 800 Example 22

(137) In Examples 11 to 22 of the present invention in which the thickness of the active metal compound layer was in the range of 1.5 nm or more and 150 nm or less, it was confirmed that the number of the thermal cycle at which ceramic cracking was generated was 800 or more and that the thermal cycle reliability was excellent. In particular, in Examples 11, 12, 14, 17, 18, and 19 of the present invention in which the thickness of the active metal compound layer was in the range of 1.5 nm or more and 20 nm or less, cracking of the ceramic substrate was not confirmed even after loading of 2000 thermal cycles and it was confirmed that the thermal cycle reliability was particularly excellent.

(138) From the above, in a case where greater thermal cycle reliability is required, the thickness of the active metal compound layer is preferably in a range of 1.5 nm or more and 150 nm or less, and more preferably in a range of 1.5 nm or more and 20 nm or less.

INDUSTRIAL APPLICABILITY

(139) According to the present invention, it is possible to provide a bonded body which is able to suppress peeling of a ceramic member and a copper member even in a case where joining with ultrasonic waves is performed, and an insulating circuit substrate.

REFERENCE SIGNS LIST

(140) 1, 101 Power module 3 Semiconductor element (electronic component) 10, 110 Insulating circuit substrate (bonded body) 11 Ceramic substrate (ceramic member) 12, 112 Circuit layer 13, 113 Metal layer 22, 23, 122 Copper sheet (copper member) 30, 130 Joint layer