Matrix-array detector with controlled-impedance row conductors

Abstract

A matrix-array detector includes an array of pixels that are sensitive to a physical effect and arranged in a matrix along rows and down columns, each pixel generating a signal according to the physical effect; row conductors, each allowing the pixels of one row to be driven; driver modules delivering selection signals to the row conductors, the driver modules being configured to deliver signals according to either of two levels, one being a high level allowing one of the rows of pixels to be selected and the other being a low level not allowing it to be selected. The detector further comprises impedance modules that are connected to each of the row conductors and configured to decrease the impedance of each row conductor and to keep the impedance of each row conductor low in a phase of reading the array of pixels as long as the corresponding selection signal is at the low level, the impedance modules being separate from the driver modules.

Claims

1. A matrix-array detector comprising: an array of pixels (P) that are sensitive to a physical effect and arranged in a matrix along rows and down columns, each pixel (P) generating a signal according to the physical effect; row conductors (L), each allowing the pixels (P) of one row to be driven; driver modules delivering selection signals (VG) to the row conductors (L), the driver modules being configured to deliver signals according to either of two levels, one being a high level (VGon) allowing one of the rows of pixels to be selected and the other being a low level (VGoff) not allowing it to be selected; wherein it further comprises impedance modules that are connected to each of the row conductors (L) and configured to decrease the impedance of each row conductor (L) and to keep the impedance of each row conductor (L) low in a phase of reading the array of pixels (P) as long as the corresponding selection signal (VG) is at the low level (VGoff), the impedance modules being separate from the driver modules.

2. The matrix-array detector according to claim 1, wherein each row conductor (L) comprises two ends, in that the driver modules are connected to the row conductors (L) at a first of the ends and in that the impedance modules are connected to each of the row conductors (L) at a second of the ends.

3. The matrix-array detector according to claim 1, wherein the array of pixels (P), the driver modules and the impedance modules are formed on the same substrate.

4. The matrix-array detector according to claim 1, wherein the impedance modules each comprise a transistor (T1) that is able to connect the corresponding row to a voltage source (Voff) corresponding to the low level (VGoff) of the selection signal when the row (L) is not selected, thus decreasing the impedance of the row (L) through the transistor (T1).

5. The matrix-array detector according to claim 1, wherein the array of pixels (P), the driver modules and the impedance modules comprise thin-film transistors.

6. The detector according to claim 5, wherein it comprises two impedance modules per row conductor (L), the two impedance modules being able to be used in alternation.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The invention will be better understood and further advantages will become apparent upon reading the detailed description of one embodiment provided by way of example, which description is illustrated by the attached drawing, in which:

(2) FIG. 1 shows an exemplary matrix-array of pixels that may be employed in a detector according to the invention;

(3) FIG. 2 shows an exemplary detector according to the invention;

(4) FIG. 3 illustrates one advantage of the invention when row conductors of the detector are broken;

(5) FIG. 4 shows an exemplary impedance module that may be employed in a detector according to the invention;

(6) FIG. 5 illustrates, in the form of a timing diagram, the operation of the impedance module of FIG. 4;

(7) FIG. 6 shows a variant impedance module that may be employed in a detector according to the invention.

(8) For the sake of clarity, the same elements will bear the same references in the various figures.

DETAILED DESCRIPTION

(9) The following description is provided with reference to a matrix-array detector comprising a plurality of elementary electronic circuits referred to as pixels, each comprising an element that is sensitive to a physical quantity. The elementary electronic circuits are, in the example described, pixels that are sensitive to light radiation. It is clear that the invention may be employed for other detectors sensitive to any form of physical quantity, allowing for example pressure or temperature maps to be produced.

(10) FIG. 1 schematically shows the detection zone 10 of a matrix-array detector. This zone comprises a matrix of two rows and two columns to facilitate understanding. Four pixels P are formed, each at the intersection of one row and one column. Of course, actual matrix arrays are generally much larger and feature a large number of rows and columns. The matrix array of pixels belongs to a matrix-array detector 12 allowing digitized images to be produced.

(11) Each pixel P comprises a photosensitive zone, represented here by a photodiode D, and an electronic processing circuit formed, in the example of FIG. 1, by a single transistor T. The references for the components D and T are followed by two coordinates specifying the rank of the row, i and i+1, respectively, and that of the column, j and j+1, respectively. The pixels shown are also known as 1T pixels since they each possess one transistor, the function of which will be described further below.

(12) In general, it is common practice to produce matrix arrays of pixels comprising thin-film field-effect transistors, known as TFTs for “thin-film transistors”. TFTs may be based on metal oxides such as for example transistors based on amorphous or crystalline indium, gallium and zinc oxide, which are known by the abbreviation IGZO. Other families of TFTs may be employed such as for example organic TFTs, amorphous silicon TFTs or polycrystalline silicon TFTs. In this last type of TFT, some have been synthesized at low temperature. They are known by the acronym LTPS for “low-temperature polycrystalline silicon”.

(13) The invention is not limited to this type of transistor. It may for example be employed for matrix arrays comprising CMOS transistors, where CMOS stands for “complementary metal-oxide-semiconductor”.

(14) The pixels P of one and the same column are connected to a column conductor Col. This conductor allows information from the pixels connected thereto to be collected. The pixels P of one and the same row are connected to a row conductor L carrying a signal VG allowing the corresponding row of pixels to be controlled.

(15) In an image capture phase, which takes place after a reset operation, the illumination received by the photodiode D decreases the potential on its cathode. This image capture phase is followed by a read phase in which the potential of the photodiode D is read. To do this, the transistor T is turned on, which therefore acts as a switch controlled by the control signal VG applied to its gate.

(16) The column conductor Col is used to collect information from a pixel in the corresponding column when it is selected by the signal VG.

(17) It is possible to implement the invention in a detector in which the pixels are simpler, in particular by replacing the transistor T with a simple diode which is turned on by the signal VG. It is also possible to implement the invention in a detector in which the pixels comprise a plurality of transistors. In particular, it is known practice to employee 3T pixels comprising, in addition to the read transistor described above, a reset transistor for the photodiode and a follower transistor. In this type of 3T pixel, a second row conductor carries a reset signal allowing the reset transistor to be controlled.

(18) FIG. 2 schematically shows the overall detector 12. The detector 12 comprises a plate 14 forming the substrate on which the components of the detection zone 10 are produced. Driver modules 16 delivering control signals to all of the row conductors L are also arranged on this same plate 14. The driver modules 16 comprise example shift registers allowing the control signals to be generated. Alternatively, the driver modules 16 may be produced on a substrate distinct from the plate 14. However, producing the driver modules 16 on the same substrate as the pixel P makes it possible to limit the connections connecting the plate 14 to its surroundings.

(19) The detector 12 comprises read circuits 18 that are connected to the column conductors Col. The read circuits 18 are generally produced on substrates distinct from the plate 14. The read circuits 18 are connected to the plate 14 by means of ribbon cables.

(20) The detector 12 comprises a circuit 20 allowing the driver modules 16 to be driven and allowing the signals from the read circuits 18 to be retrieved, in particular in order to multiplex them.

(21) According to the invention, the detector 12 comprises impedance modules 22 that are connected to each of the row conductors L. Like for the driver modules 16, the impedance modules 22 are advantageously produced on the plate 14 so as to limit the external connections to the plate 14.

(22) The invention is described with reference to a matrix array of 1T pixels having just one conductor L per pixel row. It is also possible to implement the invention for matrix arrays in particular formed of 3T pixels, and having a plurality of control conductors per row of pixels. In this case, impedance modules could be associated with all of the row conductors.

(23) To drive the read transistors T, the driver modules 16 generate binary signals including a high level allowing a pixel row to be read and the low level not allowing the row to be read. The terms “high level” and “low level” are completely arbitrary and used only to differentiate the voltages applied to the row conductor. These terms may of course be switched. The driver modules 16 employ components such as transistors, and when the high level is applied to the row L it exhibits lower impedance than when the low level is applied to the row L. As mentioned above, the high-level impedance may result in local variations in potential on the row. These variations may be the source of interference in the image from the detector 12.

(24) The impedance modules 22 are configured to decrease the impedance of the row conductors L during the transmission of the low-level signals. More specifically, for each row i, for as long as the corresponding driver module 16 is transmitting a row selection signal at the low level, the impedance module 22 keeps the corresponding row at low impedance. The impedance modules 22 are separate from the driver modules.

(25) The impedance modules 22 are advantageously arranged on the opposite side with respect to that occupied by the driver modules 16. In other words, each row conductor L has two ends. The driver modules 16 are connected to the row conductors L at a first of the ends and the impedance modules 22 are connected to each of the row conductors at a second of the ends.

(26) FIG. 3 illustrates this arrangement and its advantages. More specifically, FIG. 3 shows a detector comprising six rows and eight columns of pixels P. The driver modules 16 are located in the left-hand portion of the detection zone 10 in which the pixels P are arranged and the impedance modules 22 are located in the right-hand portion. During the manufacture or use of the detector, row L breaks may appear.

(27) These breaks may be unintentional, in the case of a manufacturing defect, or intentional when the break is used to repair a defect or to minimize the impact thereof on the overall quality of the image from the detector 12. In FIG. 3, three breaks are shown. A first break 24 appears on the first row between a driver module 16 and the detection zone 10. Breaks 26 and 28 appear inside the detection zone 10.

(28) In the absence of an impedance module 22, the broken row portion opposite the driver module 16 is electrically floating and its potential is not fixed. The potential of this floating portion may in turn interfere with the potential of the adjacent rows, columns and pixels through capacitive coupling and hence negatively affect the image quality from the detector. With the impedance modules 22 arranged on the side opposite the driver modules 16, the row portions that are isolated from the driver modules 16 are no longer floating and their potential is fixed at a value determined by the impedance modules 22, for example a value corresponding to an absence of row selection. This results in an improvement to the image quality from the detector through the reduction of artefacts due to the risk of coupling between these floating portions and neighbouring elements such as rows, columns of pixels. Consequently, the pixels in a broken row are either driven by the driver module 16 associated with the row conductor or set to low impedance by the impedance module 22 which is also associated with the row regardless of the location of the break along the row.

(29) FIG. 2 shows the implementation of the invention in a detector comprising a plate 14 on which, in addition to the pixels, the driver modules 16 and the impedance modules 22 are incorporated. Such a level of integration dictates the use of the same transistor technology both for the pixels P and for the driver 16 and impedance 22 modules.

(30) It is also possible to implement the invention even if the driver modules 16 are not incorporated on the plate 14. In this variant, it is possible to produce driver modules 16 including the low-impedance holding function for the two signal levels VGon et VGoff using different transistor technologies. This variant is of interest for stabilizing the impedance of broken rows, which commonly occurs in detectors featuring a large number of pixels.

(31) In FIG. 2, the impedance modules 22 are arranged on the opposite side with respect to that occupied by the driver modules 16. Alternatively, the impedance modules 22 may be located in the vicinity of the driver modules 16, i.e. on the same side of the detection zone 10, and more specifically between driver modules 16 and the detection zone 10. This arrangement has the advantage of grouping all of the driver and impedance components together on one and the same edge of the detector 12. The advantage related to holding the impedance of broken rows is lost. However for certain applications, such as mammography or nondestructive testing, it may be advantageous to position the last column of pixels, the one furthest away from the driver module 16, as close to the outer edge of the detector 12 is possible.

(32) FIG. 4 shows an example of an impedance module 22 formed on the basis of three thin-film transistors T1, T2 and T3. The drain of the transistor T1 is connected to the row L and its source is connected to a voltage source Voff corresponding to the low level VGoff of the signal VG.

(33) In the read phase of the detector, the driver module 16 applies the signal VG to the row L either at the high level VGon when the row L is selected or at the low level VGoff when the row L is not selected. The driver module 16, in particular when it is formed on the plate 14, may also employ thin-film transistors for applying the signal VG. The high level VGon is applied through a transistor placing the row L at low impedance while the low level VGoff is applied by turning this same transistor off, placing the row L at high impedance.

(34) The impedance module 22 connects the row L to the voltage Voff when the row L is not selected, thereby lowering the impedance of the row conductor L through the transistor T1.

(35) The transistors T2 and T3 allow the transistor T1 to be driven. The drains of the transistors T2 and T3 are connected to the gate of the transistor T1 forming a node A inside the impedance module 22. The row L is connected to the gate of the transistor T2. The source of the transistor T2 is connected to the voltage source Voff. The source of the transistor T3 is connected to a command LZA allowing the level of the node A to be set. The gate of the transistor T3 is connected to a command CMDLZ allowing the node to A to be connected to the command LZA.

(36) FIG. 5 illustrates, in the form of a timing diagram, the operation of the impedance module 22. The row selection signals VG for five consecutive rows, from i−2 to i+2, are shown. The signal VG(i−2) is at the high level VGon between times t0 and t1. After time t1, the signal VG(i−2) is at the low level VGoff. The following rows are then selected one after the other in the same way. The signal VG(i−1) is at the high level VGon between times t2 and t3. The signal VG(i) is at the high level VGon between times t4 and t5. The signal VG(i+1) is at the high level VGon between times t6 and t7. Lastly, the signal VG(i+2) is at the high level VGon between times t8 and t9. The signal CMDLZ transitions to the high level for a short duration before the selection of each row L, in particular between times t3 and t4 for the row i. Throughout the read phase, i.e. between times t0 and t11, the signal LZA is at the high level. Out of the read phase, after time t11 in the example shown, the signal LZA is at the low level.

(37) When the row i is not selected, the node A remains in the high state, the transistor T1 is on and the impedance module 22 holds the row conductor L(i) at low impedance, which remains at the voltage Voff.

(38) When the signal CMDLZ transitions to the high level before the selection of the row i, between times t3 and t4, the transistor T3 turns off, thereby placing the node A at high impedance.

(39) When the row i is selected, the voltage VGon is applied to the row conductor L(i) which turns the transistor T2 on, causing the node A to drop to the low level. The transistor T1 turns off between times t4 and t5. The impedance module 22 no longer modifies the impedance of the row conductor L(i).

(40) The signal CMDLZ may be common to all of the rows and rise to the high level before each row selection. The turning off of the transistor T1 of a row takes effect only when the conductor of the row in question receives the signal VG in the high state.

(41) Once the read phase has ended, after time t11, in the acquisition phase of the detector, the signal LZA is held at the low level. A last transition of the signal CMDLZ through the high level, between times t11 and t12, allows the node A at the low level to be placed at high impedance, which allows the three transistors T1, T2 and T3 to be placed at the voltage Voff.

(42) As seen above, it is advantageous to produce the assembly 10 of pixels P, the driver modules 16 and the impedance modules 22 on the same plate 14 so as to limit the connections from the plate 14 to its surroundings. In the exemplary impedance module 22 of FIG. 4, one module is required per row of pixels. All of the impedance modules 22 may be driven by the circuit 20. Therefore, to drive all of the impedance modules 22, only the three signals Voff, CMDLZ and LZA have to pass through the circuit 20 the plate 14, which simplifies the connections from the plate 14.

(43) The pixels and the two types of modules 16 and 22 are advantageously produced on one and the same plate 14 by using just one transistor technology, in particular TFTs (thin-film transistors). TFTs produced on a glass plate find it difficult to remain in the on state for a long time. This leads to their threshold voltage drifting and hence to the detector ageing prematurely. For this reason, out of the read phase, the transistors are placed at the voltage Voff. When using a detector for x-ray imaging, the phase of reading all of the pixels of the detector takes up about 1%, or even less, of the service life of the detector. This ratio may be enough to avoid premature ageing of the detector due to switching of the TFTs.

(44) It is possible to decrease the rate of use of the TFTs still further by doubling the number of impedance modules 22. FIG. 6 shows an example in which two impedance modules 22a and 20b are connected to one and the same row conductor L. The two modules 22a and 22b are used alternately. For example, the module 22a is used in the reading of one image and the module 22b in the reading of the next image. This embodiment allows the times for which the transistors are in the on state to be divided by two. The service life of the detector is thus increased correspondingly.

(45) The impedance modules 22 shown in FIGS. 4 and 6 are well suited for being produced on the same TFT plate as the detection zone 10. It is of course possible to implement the invention using other transistor technologies or to produce the detection zone 10 and the impedance modules 22 on different plates.

(46) The impedance modules 22 may for example be produced using AND logic gates receiving the signal CMDLZ, the signal VG and possibly the signal LZA. The output of the impedance modules 22 controlling the termination of the operation of placing the corresponding row at low impedance is obtained when the signal VG is at the high level and when the signal CMDLZ is at the low level. Other ways in which the impedance modules 22 may be produced, such as for example by employing shift registers, are of course possible.