Sensor for the acquisition of an optical signal modulated at an acoustic frequency

Abstract

The present disclosure concerns a sensor for the acquisition of an optical signal modulated at an acoustic frequency, including a plurality of pixels, each including: a photodiode; an integration circuit configured to, at each period of the modulated optical signal, integrate a photocurrent delivered by the photodiode successively into K capacitors, K being an integer greater than or equal to 2; and a phase detection circuit configured to detect an order in the crossing of a predetermined voltage threshold by the K capacitors and to generate, according to the detected order, a signal representative of the phase of the modulated optical signal.

Claims

1. A sensor for the acquisition of an optical signal modulated at an acoustic frequency, comprising a plurality of pixels, each comprising: a photodiode; an integration circuit configured to, at each period of the modulated optical signal, integrate a photocurrent delivered by the photodiode successively into K capacitors, K being an integer greater than or equal to 2; and a phase detection circuit configured to detect an order in the crossing of a predetermined voltage threshold by the K capacitors and to generate, according to the detected order, a signal representative of the phase of the modulated optical signal.

2. The sensor according to claim 1, wherein in each pixel the phase detection circuit is capable of detecting the rank of the first one of the K capacitors to have crossed the voltage threshold and of assigning to the signal representative of the phase of the modulated optical signal one among K predetermined phase values according to the detected rank.

3. The sensor according to claim 1, wherein, in each pixel, the phase detection circuit is capable of detecting the rank of the first P capacitors to have crossed the voltage threshold and the order of the crossing of the voltage threshold by said P first capacitors, P being an integer greater than or equal to 2 and smaller than K, and of assigning to the modulated optical signal one among K.sup.P predetermined phase values according to the detected ranks and order.

4. The sensor according to claim 1, wherein K=4.

5. The sensor according to claim 1, wherein each pixel further comprises a charge injection circuit controlled to, at the end of each period of the modulated optical signal during which at least one of the K capacitors crosses the voltage threshold, inject a same counter-charge into each of the K capacitors of the integration circuit.

6. The sensor according to claim 1, wherein, in each pixel, at each modulation period, the photocurrent is successively integrated into the K capacitors in an order selected according to a binary signal representative of a phase jump sequence applied to a signal for modulating the optical signal.

7. The sensor according to claim 1, wherein each pixel comprises a phase control device capable of remitting a portion of the modulated light beam received by the pixel, by introducing into the reemitted light beam a phase shift which is a function of the value of the signal representative of the phase of the modulated optical signal, generated by the pixel phase detection circuit.

8. The sensor according to claim 7, wherein, in each pixel, the phase control device comprises a liquid crystal layer arranged between first and second electrodes.

9. The sensor according to claim 8, wherein, in each pixel, the first electrode of the phase control device is connected to a node for delivering the signal representative of the phase of the modulated optical signal, generated by the pixel phase detection circuit.

10. The sensor according to claim 1, wherein, in each pixel, the signal representative of the phase of the modulated optical signal is adapted, according to a calibration signal, by a compensation circuit.

11. The sensor according to claim 10, wherein each pixel comprises its own compensation circuit.

12. The sensor according to claim 10, wherein the sensor pixels are distributed into a plurality of sub-assemblies of neighboring pixels, a same compensation circuit being shared by all the pixels of a same sub-assembly and distinct compensation circuits being provided for distinct sub-assemblies.

13. The sensor according to claim 1, wherein, in each pixel, the photodiode is a pinned photodiodes, and each of the K capacitors comprises a doped conductive region juxtaposed to the photodiode, and separated from the photodiode by a transfer gate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The foregoing features and advantages, as well as others, will be described in detail in the following description of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

(2) FIG. 1 schematically shows an example of an acousto-optic imaging system;

(3) FIG. 2 is a diagram illustrating an example of operation of the system of FIG. 1;

(4) FIG. 3 is a diagram illustrating another example of operation of the system of FIG. 1;

(5) FIG. 4 schematically shows another example of an acousto-optic imaging system;

(6) FIG. 5 is a perspective view schematically showing an embodiment of a pixel of a sensor of an acousto-optic imaging system;

(7) FIG. 6 is a simplified electric diagram of an embodiment of a pixel of a sensor of an acousto-optic imaging system;

(8) FIG. 7 is a diagram illustrating the operation of the pixel of FIG. 6;

(9) FIG. 8 is another diagram illustrating the operation of the pixel of FIG. 6;

(10) FIG. 9 is a simplified electric diagram of another embodiment of a pixel of a sensor of an acousto-optic imaging system; and

(11) FIG. 10 is a simplified electric diagram of an alternative embodiment of a pixel of an acousto-optic imaging system.

DETAILED DESCRIPTION OF THE PRESENT EMBODIMENTS

(12) Like features have been designated by like references in the various figures. In particular, the structural and/or functional features that are common among the various embodiments may have the same references and may dispose identical structural, dimensional and material properties.

(13) For the sake of clarity, only the operations and elements that are useful for an understanding of the embodiments described herein have been illustrated and described in detail. In particular, the imaging applications capable of being implemented based on the described sensors have not been detailed, the described embodiments being compatible with usual acousto-optic imaging applications in the medical field or in other fields.

(14) Unless indicated otherwise, when reference is made to two elements connected together, this signifies a direct connection without any intermediate elements other than conductors, and when reference is made to two elements coupled together, this signifies that these two elements can be connected or they can be coupled via one or more other elements.

(15) In the following description, when reference is made to terms qualifying absolute positions, such as terms “front”, “rear”, “top”, “bottom”, “left”, “right”, etc., or relative positions, such as terms “above”, “under”, “upper”, “lower”, etc., or to terms qualifying directions, such as terms “horizontal”, “vertical”, etc., unless otherwise specified, it is referred to the orientation of the drawings, it being understood that, in practice, the described devices may be oriented differently.

(16) Unless specified otherwise, the expressions “around”, “approximately”, “substantially” and “in the order of” signify within 10%, and preferably within 5%.

(17) FIG. 1 schematically shows an example of an acousto-optic imaging system.

(18) The system of FIG. 1 comprises a light source 101 (L) capable of generating a coherent light beam of frequency f.sub.L, for example, a laser source. The system further comprises a separator 103, for example, a beam splitter 103 placed with a 45-degree angle with respect to the emission direction of source 101, enabling to divide the beam generated by source 101 into an object beam O and a reference beam R. The system is arranged so that object beam O illuminates an object or a sample 105 to be analyzed, and so that reference beam R does not cross object 105. The reference beam and the object beam reflected or transmitted by object 105 are then projected onto an image sensor 109 comprising an array of pixels (not detailed in FIG. 1), to generate an interference pattern in the acquisition plane of the sensor.

(19) In the system of FIG. 1, a portion of object or sample 105 is excited by a sinusoidal acoustic wave of frequency F.sub.US, for example, in the range from 1 to 15 MHz. As a result, the frequency of the rays of the object beam crossing the excited portion of the sample is shifted to value f.sub.L+F.sub.US or f.sub.L-F.sub.US while the frequency of the rays of the object beam crossing the non-excited portions of the sample remains at value f.sub.L. Such a frequency shift enables to “mark” the photons of the object beam having crossed the excited portion of the sample, called marking area, with respect to the other photons of the object beam. It is then desired to measure the energy carried by the marked photons, to deduce therefrom information relative to light absorption in the marking area.

(20) FIG. 2 is a diagram illustrating in further detail the operating principle of the system of FIG. 1.

(21) The diagram of FIG. 2 comprises a curve 201 showing the variation over time t (in abscissa) of the light intensity I (in ordinate) received by a pixel of sensor 109 of the system of FIG. 1, when sensor 109 is illuminated by the combination of the object beam and of the reference beam.

(22) In operation, sensor 109 sees an interference pattern having a beat frequency equal to acoustic modulation frequency F.sub.US. Thus, as shown in FIG. 2, the intensity I received by each pixel varies in sinusoidal fashion around an average value or DC component a.sub.0, with a peak amplitude of value a.sub.1, at a frequency equal to the acoustic modulation frequency F.sub.US of the system. The light intensities received by different pixels of sensor 109 may have different DC components a.sub.0 and/or different amplitudes a.sub.1, but all fluctuate in sinusoidal fashion at beat frequency F.sub.US, with specific phase shifts.

(23) Each pixel of sensor 109 comprises a photodiode delivering a current representative of the light intensity received by the pixel.

(24) In this example, the measurement of the marked portion of the object beam is performed during an acquisition period T.sub.acq of duration N*T.sub.US, where T.sub.US designates the period of acoustic modulation of the system, equal to 1/F.sub.US, and where N is an integer, greater than or equal to 1, for example, in the range from 100 to 10,000.

(25) Each pixel comprises an integration circuit configured to, at each period of acoustic modulation T.sub.US of acquisition period T.sub.acq, integrate the photocurrent delivered by the photodiode successively into K=4 different capacitors C0, C1, C2, and C3 (not shown in FIG. 2). Such a four-phase integration and sampling cycle is successively repeated N times during period T.sub.acq, it being understood that the integration capacitors C0, C1, C2, and C3 of the pixel are not reset between the beginning and the end of period T.sub.acq. The accumulation of the samples over a high number N of periods of the acoustic modulation signal enables to improve the signal-to-noise ratio of the measurement. Number N is preferably selected so that the duration of acquisition phase T.sub.acq remains shorter than a characteristic duration of decorrelation of the medium, for example, in the range from 0.1 to 5 ms, for example, in the order of 1 ms, corresponding to the time beyond which the amplitude and the phase of the measured signal risk varying due to physiological variations of the observed medium (for example, due to a blood platelet movement).

(26) In FIG. 2, for each of the N periods T.sub.US of acquisition phase T.sub.acq, references i0.sub.j, i1.sub.j, i2.sub.j, and i3.sub.j, designate the four successive periods of integration of the photocurrent delivered by the pixel photodiode, respectively in the four capacitors C0, C1, C2, and C3 of the pixel, where j is an integer in the range from 1 to N designating the rank of the considered acoustic modulation period T.sub.US in acquisition phase T.sub.acq. In this example, integration periods i0.sub.j, i1.sub.j, i2.sub.j, and i3.sub.j all substantially have the same duration, in the order of T.sub.US/4.

(27) At the end of acquisition phase T.sub.acq, each pixel of the sensor delivers four values I0, I1, I2, and I3 respectively representative of the voltages across capacitors C0, C1, C2, and C3 of the pixel.

(28) Based on these four values, the complex field E.sub.OM of the portion of the object beam marked by the acoustic modulation may be determined, for each pixel of the sensor, by formula E.sub.OM=(I0-I2)+j(I1-I3). Component I0-I2 corresponds to the real part of field E.sub.OM, and component I1-I3 corresponds to the imaginary part of field E.sub.OM. The phase P.sub.OM and the amplitude A.sub.OM of the marked object beam received by each pixel of the sensor may be determined by the following formulas:

(29) $\begin{array}{cc}{P}_{\mathrm{OM}}=\arctan \left(\frac{I1-I3}{I0-I2}\right)\mathrm{and}& \left[\mathrm{Eq}.1\right]\\ A_{\mathrm{OM}}=\sqrt{{\left(I0-I2\right)}^2+{\left(I1-I3\right)}^2}& \left[\mathrm{Eq}.2\right]\end{array}$

(30) Knowing the amplitude A.sub.OM of the marked object beam enables, in particular, to obtain information relative to the light absorption in the acoustic marking area, for example, to detect the possible presence of an absorbing body, for example, a tumor, in the marking area.

(31) It should be noted that the acquisition technique described in relation with FIGS. 1 and 2 only enables to determine the average absorption within the marking area, but does not enable to obtain information relative to the absorption in local regions of the marking area.

(32) To determine the absorption in local regions of the marking area, a solution comprises applying phase jumps to the acoustic marking wave, for example, according to a random or pseudo-random pattern. As an example, at each new acoustic modulation period T.sub.US, a phase jump of value 0 or π, randomly or pseudo-randomly selected, is applied to the acoustic marking wave. At the level of sensor 109, after the interference of the object beam with the reference beam, the signal is sampled according to the four-phase demodulation method discussed in relation with FIG. 2, taking into account, during the demodulation, the phase jump pattern Φ applied to the acoustic marking wave.

(33) FIG. 3 is a diagram illustrating this operating principle in further detail.

(34) The diagram of FIG. 3 comprises a curve 301 representing the variation, over time t, in abscissa, of the contribution I(Z.sub.target), in ordinate, of a local position Z.sub.target of the marking area, to the object optical signal received by sensor 109 after the interference with the reference signal.

(35) Intensity I(Z.sub.target) varies in sinusoidal fashion around an average value or DC component a.sub.0, with a peak amplitude of value a.sub.1, at a frequency equal to the acoustic modulation frequency F.sub.US of the system. However, in the example of FIG. 3, at each new period T.sub.US of acquisition phase T.sub.acq, intensity I(Z.sub.target) is submitted to a 0 or π phase jump corresponding to the phase jump pattern Φ applied to the acoustic marking wave, delayed by a delay Δt=Z.sub.target/V.sub.US, V.sub.US designating the propagation speed of the acoustic marking wave in the observed medium.

(36) In each pixel of the sensor, the integration circuit is configured to, at each acoustic modulation period T.sub.US of acquisition period T.sub.acq, integrate the photocurrent delivered by the photodiode successively into the four capacitors C0, C1, C2, and C3 (not shown in FIG. 3), taking into account the delayed phase jump pattern Φd=Φ(t-Δt) to determine the order in which capacitors C0, C1, C2, and C3 are connected to the photodiode. More particularly, in this example, for each acoustic modulation period T.sub.US of acquisition period T.sub.acq, if the current phase shift value in the sequence of phase jumps Φd is zero, the photocurrent is successively integrated into capacitors C0, C1, C2, and C3 in the same order as at the previous period T.sub.US. If, however, the current phase shift value in the sequence of phase jumps Φd is equal to π, the order of integration of the photocurrent into capacitors C0 and C2, on the one hand, and C1 and C3, on the other hand, is inverted.

(37) At the end of acquisition phase T.sub.acq, each pixel of the sensor delivers four values I0, I1, I2, and I3 respectively representative of the voltages across capacitors C0, C1, C2, and C3 of the pixel. Values I0, I1, I2, and I3 are mainly representative of the contribution to the object optical signal received by the pixel, of the position of the marking area for which phase jump pattern Φd is correlated to the acoustic modulation signal, that is, position Z.sub.target=V.sub.US*Δt.

(38) Based on these four values, the complex field E.sub.OM of the portion of the object beam marked by the acoustic modulation at position Z.sub.target of the marking area may be determined, for each pixel of the sensor, by formula E.sub.OM=(I0-I2)+j(I1-I3). Component I0-I2 corresponds to the real part of field E.sub.OM, and component I1-I3 corresponds to the imaginary part of field E.sub.OM. The phase P.sub.OM and the amplitude A.sub.OM of the marked object beam received from position Z.sub.target may be determined by the same formulas Eq. 1 and Eq. 2 as in the example of FIG. 2.

(39) The measurement may be repeated by modifying the delay Δt between the phase jump sequence Φ applied to the acoustic modulation signal and the sequence Φd applied to the sensor, to measure the field E.sub.OM from another target position Z.sub.target in the marking area.

(40) In the above-described examples, the average of the amplitudes A.sub.OM measured by the different sensor pixels enables to obtain information relative to the average absorption of the marking area (FIG. 2) or to the absorption of a local area of the marking area (FIG. 3).

(41) In certain applications, it is further desirable to measure, in each pixel, the phase P.sub.OM of the portion of the object beam measured by the pixel.

(42) As an example, each pixel may comprise a phase control device capable of remitting a portion of the light beam received by the pixel, with a phase shift selected according to the phase P.sub.OM of the incident beam. As an example, each pixel comprises a phase conjugation mirror capable of reflecting a portion of the incident beam towards the observed medium, with a phase shift P.sub.OM*=−P.sub.OM corresponding to the conjugate of the phase P.sub.OM of the incident beam measured by the pixel. This enables to refocus a portion of the light received on the sensor at the level of the marking area. Such a refocusing of the object beam in the marking area may in particular enable to improve the signal-to-noise ratio of the measurement and/or to activate photosensitive molecules in the refocusing area and/or to destroy pathogenic cells by local heating of the medium.

(43) FIG. 4 schematically shows a variant of the acousto-optic imaging system of FIG. 1, where each pixel of the sensor comprises a phase control device capable of reflecting a portion of the light beam received by the pixel, with a phase shift controlled according to the value of the phase POM of the incident beam measured by the pixel.

(44) In FIG. 4, the beam B reflected towards sample 105 and refocused by sensor 109 has been shown in dashed lines.

(45) FIG. 5 is a perspective view schematically showing an embodiment of a pixel of sensor 109 of FIG. 4.

(46) The pixel of FIG. 5 comprises a semiconductor substrate 50 having a photodetection area 52, for example, a photodiode, defined in an upper portion thereof.

(47) Substrate 50 is topped with a stack of metallization layers comprising conductive tracks 54 separated by an insulating material 56. For clarity, the conductive tracks of the first metallization levels are not shown in the perspective view of FIG. 5.

(48) A conductive track 54′, at least partly reflective at the emission wavelength of light source 101, which at least partly covers a portion of the pixel, is defined in an upper level of the interconnection stack. In the shown example, region 54′ is made of an opaque material, for example, of the same material as the conductive tracks of the lower interconnection levels, for example, a metal such as aluminum or copper. An opening 58 is defined in region 54′ opposite photodetection area 52. Thus, incident light beams which arrive at the level of opening 58 reach the surface of photodetection area 52, while incident light beams which arrive onto region 54′ are reflected by said region. The relative surface areas of region 54′ and of opening 58 are selected to reflect a desired proportion of the incident beam, for example, from 40 to 50% of the incident light flow of the incident beam.

(49) A stack of a liquid crystal layer 62 and of a transparent conductive layer 66 is formed at the surface of the interconnection stack. In the shown example, the stack further comprises a first alignment layer 60 (bonding and alignment layer for liquid crystals) arranged between the upper surface of the interconnection stack and the lower surface of liquid crystal layer 62, and a second alignment layer 64 arranged between the upper surface of liquid crystal layer 62 and the lower surface of transparent conductive layer 66. The stack further comprises as an example an upper glass plate 68. Transparent conductive layer 66 forms a first electrode for controlling the liquid crystals of layer 62, while region 54′ forms the second control electrode. Transparent conductive layer 66 is made of a conductive material transparent at the wavelength of light source 101. As an example, transparent conductive layer 66 may be made of indium tin oxide (ITO).

(50) The elements of application of control voltages to electrodes 54′ and 66 are not detailed herein, the forming of tracks and/or vias of access to electrodes such as electrodes 54′ and 66 being well known in integrated circuit techniques.

(51) The application of a voltage between electrodes 54′ and 66 enables to modify the structure of the liquid crystals of layer 62, and thus the phase of the reflected light beam. It should be noted that such an adjustment is performed pixel by pixel, a counter-electrode 54′ being independently defined in each of the pixels. The control voltage applied to liquid crystal layer 62, and thus the phase shift introduced by layer 62, are selected according to a measurement of the phase of the incident light beam detected by photodiode 52, said phase measurement being formed by a readout circuit internal to the pixel, not detailed in FIG. 5.

(52) To measure the phase of the incident light beam within each pixel, a possibility is to apply the above-mentioned mathematical formula Eq. 1. However, the implementation of an arc tangent calculation requires relatively complex circuits, which are difficult to integrate within a pixel.

(53) Thus, it is here desired to form a simple and compact pixel capable of delivering a signal representative of the phase of an optical signal modulated at an acoustic frequency.

(54) FIG. 6 is a simplified electric diagram of an embodiment of a pixel of a sensor of an acousto-optic imaging system, for example, of the type described in relation with FIGS. 4 and 5. In practice, the sensor may comprise a plurality of identical or similar pixels, for example, arranged in an array of rows and columns.

(55) The pixel of FIG. 6 is capable of implementing a four-phase demodulation of the type described in relation with FIGS. 2 and 3.

(56) The pixel of FIG. 6 comprises a photodiode 52 capable of delivering a photocurrent according to a received light intensity.

(57) The pixel of FIG. 6 further comprises an integration stage 70 configured to, at each period T.sub.US of phase T.sub.acq of acquisition of the modulated optical signal, integrate the photocurrent delivered by the photodiode successively into four different capacitors C0, C1, C2, and C3. The capacitors C0, C1, C2, and C3 of integration stage 70 for example have the same value.

(58) In this example, the integration stage comprises an operational amplifier 71 having an inverting input (−) coupled to the cathode of photodiode 52 via a switch S1, and a non-inverting input (+) coupled to a node of application of a reference voltage V.sub.ref, for example, a fixed DC voltage Switch S1 has a first conduction node coupled, for example, connected, to the cathode of photodiode 52, and a second conduction node coupled, for example, connected, to the inverting input (−) of operational amplifier 71. It should be noted that in the rest of the disclosure, the switches of the described circuits and the signals for controlling such switches will be designated with the same reference numerals. For example, it will be spoken of signal S1 to designate the signal for controlling switch S1.

(59) In the example of FIG. 6, integration stage 70 comprises four switches ϕ0, ϕ1, ϕ2, and ϕ3 series-coupled with capacitors C0, respectively C1, respectively C2, respectively C3, between the inverting input and the output of operational amplifier 71. More particularly, in the present example, each of capacitors C0, C1, C2, and C3 has a first electrode connected to the output node of operational amplifier 71 and a second electrode coupled to the inverting input of operational amplifier 71 via switch ϕ0, respectively ϕ1, respectively ϕ2, respectively ϕ3. Each of switches ϕ0, ϕ1, ϕ2, and ϕ3 has a first conduction node coupled, for example, connected, to the inverting input of operational amplifier 71, and a second conduction node coupled, preferably connected, respectively to the second electrode of capacitor C0, to the second electrode of capacitor C1, to the second electrode of capacitor C2, and to the second electrode of capacitor C3.

(60) Integration stage 70 further comprises a reset switch ϕrst having a first conduction node coupled, for example, connected, to the inverting input of operational amplifier 71, and a second conduction node coupled, for example, connected, to the output of operational amplifier 71.

(61) The pixel of FIG. 6 further comprises a charge injection circuit 72 controllable to inject a fixed predetermined quantity of compensation charges, called counter-charge, into each of capacitors C0, C1, C2, and C3 of integration stage 70. As an example, charge injection circuit 72 comprises three transistors MOS ϕFB1, ϕFB2, and REF2, for example, P-channel MOS transistors, series-coupled between a node of application of a reference voltage REF1 and the end of switch S1 opposite to the inverting input of operational amplifier 71. As an example, transistor ϕFB1 has a first conduction node connected to the node of application of voltage REF1 and a second conduction node connected to a first conduction node of transistor ϕFB1, and transistor REF2 has a first conduction node connected to switch S1 and a second conduction node connected to the second conduction node of transistor ϕFB2. For simplification, MOS transistors ϕFB1, ϕFB2, and REF2 and the gate control signals of the transistors are here designated with the same references. Signals REF1 and REF2 are for example fixed DC bias voltages, signals ϕFB1 and ϕFB2 being control voltages of transistors ϕFB1 and ϕFB2, each of voltages ϕFB1 and ϕFB2 having a low level and a high level defining a two-level potential barrier, it being understood that the low, respectively high, level, of voltage ϕFB1 may be different from the low, respectively high, level, of voltage ϕFB2.

(62) The pixel of FIG. 6 further comprises a voltage comparator 74 having a positive input (+) coupled, for example, connected, to an output node of integration stage 70. More particularly, in this example, the positive input (+) of voltage comparator 74 is coupled, for example, connected, to the output node of the operational amplifier 71 of integration stage 70. Comparator 74 further has a negative input (−) coupled, for example, connected, to a node of application of a threshold voltage TH, for example, a fixed DC voltage. Comparator 74 has an output node delivering a signal UP, for example, a voltage, having a first state, for example, a low state, when the output voltage VOUT of integration stage 70 is smaller than voltage TH, and a second state, for example, a high state, when the output voltage VOUT of integration stage 70 is greater than threshold TH.

(63) The pixel of FIG. 6 further comprises a first D flip-flop (DFF) 76 having a d data input node coupled, for example, connected, to a node of application of a fixed DC reference voltage Vdd, for example corresponding to a high power supply voltage of the pixel and seen as a high logic state by flip-flop 76, and a c control input node coupled, for example, connected, to the output node of comparator 74. Flip-flop 76 further comprises a reset input node rst. Flip-flop 76 further comprises an s output node delivering a Q binary data signal representative of the high or low binary value stored in flip-flop 76.

(64) The pixel of FIG. 6 further comprises a second D flip-flop 77 having a d data input node coupled, for example, connected, to the s output of flip-flop 76 and a c control input node coupled, for example, connected, to a node of application of a sampling signal ech. Flip-flop 77 further comprises an s output node delivering a signal FB representative of the high or low binary value stored in flip-flop 77. The output signal FB of flip-flop 77 is applied to the reset input node rst of flip-flop 76, for example, by direct connection of the s output node of flip-flop 77 to the reset input node rst of flip-flop 76.

(65) The pixel of FIG. 6 further comprises, at the output of flip-flop 77, a logic circuit 78 generating control signals ϕFB1 and ϕFB2 of charge injection circuit 72 according to the state of the binary output signal FB of flip-flop 77.

(66) The pixel of FIG. 6 further comprises a phase detection circuit 80 capable of generating a signal V.sub.PH, for example, a voltage, representative of the phase of the modulated optical signal received by photodiode 52. As an example, signal V.sub.PH is representative of the phase shift to be applied to the reflected signal, which depends on the phase of the modulated optical signal received by photodiode 52. In the example of FIG. 6, phase detection circuit 80 comprises four D flip-flops 82.sub.i being an integer in the range from 0 to 3. Each of flip-flops 82.sub.i has a d data input node receiving the signal ϕi for controlling the switch ϕi of same rank i of integration stage 70. As an example, each flip-flop 82.sub.i has its d data input node connected to the control node of the switch ϕi of same rank i. Each of flip-flops 82.sub.i further has a c control node receiving the Q output signal of flip-flop 76. As an example, each flip-flop 82.sub.i has its c input node connected to the output node of flip-flop 76. Each flip-flop 82.sub.i further comprises an s output node delivering a binary data signal Phz<i> representative of the high or low binary value stored in the flip-flop. The signal Phz<0:3> formed by the four output bits of flip-flops 82.sub.i is used to control a four-path-one-path switch 84 of phase detection circuit 80. In this example, switch 84 is configured to apply to the node for supplying phase signal V.sub.PH one among four predetermined bias voltages Vpol<0>, Vpol<1>, Vpol<2>, and Vpol<3>, for example, fixed or variable voltages having distinct levels, according to the state of signal Phz<0:3>. More particularly, in this example, switch 84 comprises four switches 84.sub.i, each having a first conduction node coupled, for example, connected, to a node of application of the bias voltage Vpol<i> of same rank i, a second conduction node coupled, for example, connected, to the node for supplying voltage V.sub.PH, and a control node coupled, for example, connected, to the s output node of the flip-flop 82.sub.i of same rank i. In this example, the output signals of flip-flops 82.sub.i are mutually exclusive, that is, at a given time, only one of switches 84.sub.i may be on (in other words, two switches 84.sub.i cannot be simultaneously on). Thus, the output voltage V.sub.PH of phase detection circuit 80 can only take one of the four voltage values Vpol<0>, Vpol<1>, Vpol<2>, and Vpol<3>, according to the state of signal Phz<0:3>. As an example, in a pixel structure of the type described in relation with FIG. 55, voltage V.sub.PH may be directly used to control the liquid crystal layer 62 of the pixel. In this case, the node for delivering output voltage V.sub.PH may be connected to the bias electrode 54′ of the pixel.

(67) The operation of the pixel of FIG. 6 will now be described in further detail in relation with FIGS. 7 and 8.

(68) FIGS. 7 and 8 are diagrams illustrating the time variation of various internal signals and/or signals for controlling the pixel of FIG. 6 during a phase of measurement of an optical signal modulated at an acoustic frequency, for example, a signal of the type previously described in relation with FIG. 2 (optical signal modulated at an acoustic frequency with no random phase jumps) or in relation with FIG. 3 (optical signal modulated at an acoustic frequency with random phase jumps).

(69) FIG. 7 more particularly shows the variation, over time t (in abscissa), of the output voltage VOUT of integration circuit 70, of the control voltages ϕ0 and ϕ2 of switches ϕ0 and ϕ2 of integration circuit 70, of the output voltage UP of comparator 74, of the Q output voltage of flip-flop 76, of the output voltage FB of flip-flop 77, of the control voltages ϕFB1 and ϕFB2 of charge injection circuit 72, and of the control voltage ech of flip-flop 77.

(70) For simplification, the control voltages ϕ1 and ϕ3 of switches ϕ1 and ϕ3 of integration circuit 70 have not been shown in FIG. 7.

(71) FIG. 7 shows an operation in demodulation mode with no phase jump, for example, to measure a modulated optical signal of the type described in relation with FIG. 2.

(72) FIG. 8 shows the variation, over time t (in abscissa), of the output voltage VOUT of integration circuit 70, and of the control voltages ϕ0, ϕ1, ϕ2, and ϕ3 of switches ϕ0, ϕ1, ϕ2, and ϕ3 of integration circuit 70. FIG. 8 further shows the time variation of the light intensity (Z.sub.target) which is desired to be measured.

(73) FIG. 8 shows a demodulation operation with random phase jumps, for example, to measure a modulated optical signal of the type described in relation with FIG. 3.

(74) During the entire optical signal measurement phase, switch S1 of the pixel is maintained on (conductive). At the beginning of the measurement phase, the voltages across the capacitors C0, C1, C2, and C3 of integration stage 70 are all taken down to zero by the simultaneous turning on of switches ϕ0, ϕ1, ϕ2, ϕ3, and ϕrst, during an initialization phase T.sub.init (FIG. 8). At the end of initialization phase T.sub.init, the actual phase of acquisition of the modulated optical signal (phase T.sub.acq of FIGS. 2 and 3) starts.

(75) All along acquisition phase T.sub.acq, the photonic current generated by the photodiode is sequentially integrated into capacitors C0, C1, C2, and C3, according to the four-phase demodulation method described in relation with FIG. 2 or 3. For this purpose, in the example of FIG. 7, for each acoustic modulation period T.sub.US of phase T.sub.acq, control signals ϕ0, ϕ1, ϕ2, and ϕ3 are successively set to the high state (corresponding to a state where switches ϕ0, ϕ1, ϕ2, and ϕ3 are controlled to the on state), in this order during a period in the order of T.sub.US/4. Signals ϕ0, ϕ1, ϕ2, and ϕ3 are non-overlapping so that, during the entire acquisition phase T.sub.acq, two of switches ϕ0, ϕ1, ϕ2, and ϕ3 are never simultaneously on. In the example of FIG. 8, for each modulation period T.sub.US of phase T.sub.acq, control signals ϕ0, ϕ1, ϕ2, and ϕ3 are successively set to the high state in an order selected according to the current phase value of the delayed phase jump pattern Φd used for the demodulation. The delayed phase jump pattern Φd applied during the acquisition phase may be common to all the sensor pixels, and the switching order of switches ϕ0, ϕ1, ϕ2, and ϕ3 may be determined in common fashion for all the sensor pixels.

(76) In practice, the object light beam received by each pixel comprises photons marked by the acoustic modulation and photons non-marked by the acoustic modulation. The optical signal received by the photodiode thus comprises the sinusoidal component of frequency F.sub.US, corresponding to the marked photons, but also an offset. The optical energy associated with this offset may be much higher, for example, more than 100 times higher, than the energy of the marked portion of the beam.

(77) Thus, the voltages across capacitors C0, C1, C2, and C3 progressively increase for each new acoustic modulation period T.sub.US of acquisition phase T.sub.acq. The integration of the photonic current into the four capacitors C0, C1, C2, and C3 of integration circuit 70 may then result in a very fast saturation of the pixel with, in the end, a very low quantity of collected useful signal (low signal-to-noise ratio).

(78) Comparator 74, flip-flops 76 and 77, and charge injection circuit 72 form an offset compensation circuit. Comparator 74 enables to detect the crossing of a predetermined voltage threshold TH, for example, in the order of 2 volts, by one of capacitors C0, C1, C2, and C3 during a phase of integration of the photocurrent in the capacitor. As soon as threshold TH has been crossed by one of capacitors C0, C1, C2, and C3, the output signal UP of comparator 74 switches to the high state, which immediately causes the switching to the high state of the Q output signal of flip-flop 76 (previously initialized to the low state).

(79) Signal ech for controlling flip-flop 77 is a periodic square pulse signal of frequency F.sub.US having a rising edge at the beginning of each period T.sub.US of acquisition phase T.sub.acq. Thus, the output signal FB of flip-flop 77 switches to the high state at the beginning of the acoustic modulation period T.sub.US following the period T.sub.US having led to the crossing of threshold TH by one of capacitors C0, C1, C2, and C3. Signal FB being applied to the reset node of flip-flop 76, this leads to resetting flip-flop 76. The Q signal then switches back to the low state.

(80) During the period T.sub.US following the switching to the high state of signal FB, logic circuit 78 controls charge injection circuit 72 (via signals ϕFB1 and ϕFB2) and integration circuit 70 (via signals ϕ0, ϕ1, ϕ2, and ϕ3) to inject into each of the capacitors C0, C1, C2, and C3 of the integration circuit a same counter-charge Δq, of predetermined value. For this purpose, control signals ϕ0, ϕ1, ϕ2, and ϕ3 are, as previously described, successively controlled to the on state for a period in the order of T.sub.US/4. At each of the four conduction periods of a switch ϕi, voltages ϕFB1 and ϕFB2, initially in their respective low states, are successively set to their respective high states with an interval of a few nanoseconds (for example, with an interval in the range from 1 to 20 ns), starting with voltage ϕFB1, and then maintained in their respective high levels during a first part of the conduction period of switch ϕi, for example, during the first part of the conduction period of switch ϕi. The setting to the high state of voltage ϕFB1 acts as a potential barrier for the counter-charge Δq stored in the channel of transistor ϕFB2 so that, at the switching of voltage ϕFB2 to its high level, the charges of counter-charge Δq cross potential barrier REF2 (with REF2>Vref), and migrate towards the capacitor Ci connected to switch ϕi. Voltages ϕFB1 and then ϕFB2 are then switched to their respective low levels and then maintained in their respective low levels during the second part of the conduction period of switch ϕi, to precharge again the channel region of transistor ϕFB2 for the injection of the next counter-charge Δq.

(81) Thus, a common contribution which may be seen, in average, as a current for compensating the offset photonic current is added to each of the four output samples I0, I1, I2, and I3 of the pixel. At the end of acquisition phase T.sub.acq, each of samples I0, I1, I2, and I3 will carry the previously-described integration of the N phases i0.sub.j, respectively i1.sub.j, respectively i2.sub.j, respectively i3, as well as of a common residual offset. The residual offset will be taken down to zero on calculation of the real and imaginary portions of the object signal, by differentiation of samples I0-I2 and I1-I3.

(82) During acquisition phase T.sub.acq, the offset being common to all samples I0, I1, I2, and I3, the order in which threshold TH is crossed by the samples provides information relative to the relative magnitudes of the energies carried by the photocurrent in each of integration periods i0.sub.j, i1.sub.j, i2.sub.j, and i3.sub.j. Thus, knowing the rank of the sample having crossed the threshold first, the phase of the modulated optical signal measured by the pixel can be traced back.

(83) In practice, during a same acoustic modulation period T.sub.US of acquisition phase T.sub.acq, threshold TH may be crossed by a plurality of capacitors C0, C1, C2, and C3 of the pixel. In this case, with the above-described operation, it is not possible, at the end of modulation period T.sub.US, to know which of samples I0, I1, I2, and I3 has the highest value. In the pixel of FIG. 6, the four flip-flops 82.sub.i have, as a sampling signal or control signal, the Q signal. This signal being only reset after application of counter-charge Δq, if two samples or more were to cross the threshold before the activation of signal FB, only the first signal ϕi in the high state upon crossing of threshold TH will be taken into account. Such an assembly guarantees that only one of the switches 84.sub.i is on at the same time, signals ϕi being non-overlapping. For the above-described object beam refocusing application, given the low quantization resolution required on the phase for the refocusing operation, the error introduced by the selection of the first sample crossing threshold TH can be considered as tolerable. It should further be noted that during the successive modulation periods T.sub.US of acquisition phase T.sub.acq, since the interval between the values of samples I0, I1, I2, and I3 increases, the determination of the phase value will be more and more accurate. The determination on the fly of the phase value during acquisition phase T.sub.acq has the advantage, in the above-mentioned application to the refocusing of the object beam, to enable to start polarizing the liquid crystal layer without waiting for the end of the measurement. The possible readjustment of the phase value during the acquisition due to the increase in the difference between the values of the different samples will be all the faster (in terms of physical realignment of the liquid crystal molecules) as the phase estimation has a high probability of being increasingly stable during the acquisition, with potential variations of the estimated phase which only appear between neighboring quadrants, and thus increasingly small liquid crystal polarization jumps (in the example of application of FIGS. 4 and 5).

(84) In the example of FIG. 6, the pixel performs a quantization of the phase over two bits only, which is sufficient for the above-described object beam refocusing application. As an example, the value of the phase of the modulated light beam may be considered as being equal to: 0 when signal Phz<0:3> is ‘1000’; 3π/2 when signal Phz<0:3> is ‘0100’; π when signal Phz<0:3> is ‘0010’; and π/2 when signal Phz<0:3> is ‘0001’.

(85) To obtain a phase measurement quantized over more than two bits, a possibility is to search for the first two samples having crossed threshold TH are, and for the order in which it has been crossed. Such a search may be carried out over a plurality of successive modulation periods T.sub.US. The search for the rank of the second sample having crossed threshold TH should be performed before the application of counter-charge ϕq in capacitors C0, C1, C2, and C3. The sizing of integrator 70 and of threshold TH may then be selected to enable to carry on with no saturation the integration of the first sample to have crossed the threshold until the second sample crosses the threshold.

(86) FIG. 9 is a simplified electric diagram illustrating a variant of the pixel of FIG. 6, capable of enabling to search for the first two samples having crossed threshold TH, in order to deliver a phase value quantized over three bits (eight possible phase values).

(87) The pixel of FIG. 9 differs from the pixel of FIG. 6 in that, in the pixel of FIG. 9, the D flip-flop 76 of the pixel of FIG. 6 is replaced with an association of two series-cascaded D flip-flops 85 and 86 sharing the same sampling signal UP.

(88) Flip-flop 85 has a d data input node coupled, for example, connected, to node Vdd, and a c control input node coupled, for example, connected, to the output node of comparator 74. Flip-flop 85 further comprises an s output node delivering a binary data signal Q1. Flip-flop 86 has a d data input node coupled, for example, connected, to the s output node of flip-flop 85, and a c control node coupled, for example, connected, to the output node of comparator 74. Flip-flop 86 further comprises an s output node delivering a binary data signal Q2. The s output node of flip-flop 86 is coupled, for example, connected, to the d data input node of flip-flop 77. Each of flip-flops 85 and 86 further comprises a reset node rst coupled, for example, connected, to the s output node of flip-flop 77.

(89) The pixel of FIG. 9 further differs from the pixel of FIG. 6 in that, in the pixel of FIG. 9, the phase detection circuit 80 of the pixel of FIG. 6 is replaced with a phase detection circuit 90.

(90) Phase detection circuit 90 is capable of generating a signal V.sub.PH representative of the phase of the modulated optical signal received by photodiode 52. In the example of FIG. 9, phase detection circuit 90 comprises eight detection sub-circuits 91.sub.k, k being an integer in the range from 0 to 7. Each detection sub-circuit 91.sub.k comprises two D flip-flops 92.sub.k1 and 92.sub.k2, and an AND gate 93.sub.k having two inputs a1 and a2 and one output s. Each of the eight flip-flops 92.sub.k1 comprises a d input node receiving one of the four control signals ϕ0, ϕ1, ϕ2, and ϕ3, and a c control node receiving output the output signal Q1 of flip-flop 85. Each of the eight flip-flops 92.sub.k2 comprises a d input node receiving one of the four control signals ϕ0, ϕ1, ϕ2, and ϕ3, and a c control node receiving the output signal Q2 of flip-flop 85. The connections of signals ϕ0, ϕ1, ϕ2, and ϕ3 to the input nodes of the 16 flip-flops 92.sub.k1 and 92.sub.k2 are such that the 8 detection sub-circuits 91.sub.k respectively receive on the d input nodes of their flip-flops 92.sub.k1 and 92.sub.k2 the eight possible combinations of orders of the crossing of threshold TH by two of samples I0, I1, I2, and I3. More particularly, in the present example: flip-flops 92.sub.01 and 92.sub.02 receive on their d nodes respectively signals ϕ0 and ϕ1; flip-flops 92.sub.11 and 92.sub.12 receive on their d nodes respectively signals ϕ1 and ϕ0; flip-flops 92.sub.21 and 92.sub.22 receive on their d nodes respectively signals ϕ1 and ϕ2; flip-flops 92.sub.31 and 92.sub.32 receive on their d nodes respectively signals ϕ2 and ϕ1; flip-flops 92.sub.41 and 92.sub.42 receive on their d nodes respectively signals ϕ2 and ϕ3; flip-flops 92.sub.51 and 92.sub.52 receive on their d nodes respectively signals ϕ3 and ϕ2; flip-flops 92.sub.61 and 92.sub.62 receive on their d nodes respectively signals ϕ3 and ϕ0; and flip-flops 92.sub.71 and 92.sub.72 receive on their d nodes respectively signals ϕ0 and ϕ3.

(91) In each detection sub-circuit 91.sub.k, flip-flop 92.sub.k1 has an s output node coupled, for example, connected, to input node a1 of AND gate 93.sub.k and flip-flop 92.sub.k2 has an s output node coupled, for example, connected, to input node a2 of AND gate 93.sub.k.

(92) In each of phase detection sub-circuits 91.sub.k, the s output node of AND gate 93.sub.k delivers a binary data signal Phz<k> representative of the logic combination by AND gate 93.sub.k of the binary values stored in flip-flops 92.sub.k1 and 92.sub.k2. The signal Phz<0:7> formed by the eight output bits of AND gates 93.sub.k is used to control an eight-path-to-one-path switch 94 of phase detection circuit 90. In this example, switch 94 is configured to apply to the node for supplying phase signal V.sub.PH one among eight predetermined bias voltages Vpol<0>, Vpol<1>, Vpol<2>, Vpol<3>, Vpol<4>, Vpol<5>, Vpol<6>, and Vpol<7>, for example, fixed or variable voltages having distinct levels, according to the state of signal Phz<0:7>. More particularly, in the present example, switch 94 comprises eight switches 94.sub.k each having a first conduction node coupled, for example, connected, to a node of application of the bias voltage Vpol<k> of same rank k, a second conduction node coupled, for example, connected, to the node for delivering voltage V.sub.PH, and a control node coupled, for example, connected, to the s output node of the AND gate 93.sub.k of same rank k. In the present example, the output signals of AND gates 93.sub.k are mutually exclusive, that is, at a given time, only one of switches 94.sub.k may be turned on. Thus, the output voltage V.sub.PH of phase detection circuit 90 can only take one of the eight voltage values Vpol<0>, Vpol<1>, Vpol<2>, Vpol<3>, Vpol<4>, Vpol<5>, Vpol<6>, and Vpol<7>, according to the state of signal Phz<0:7>.

(93) In the pixel of FIG. 9, signal Q1 switches to the high state after the crossing of threshold TH by a first sample, and signal Q2 switches to the high state after the crossing of threshold TH by a second sample. Feedback signal FB is then activated after the sampling of the high state of signal Q2 by signal ech, in flip-flop 77. Signals Q1 and Q2 enable to sample in parallel eight pairs of control signals (ϕ0, ϕ3), (ϕ3, ϕ0), (ϕ3, ϕ2), (ϕ2, ϕ3), (ϕ2, ϕ1), (ϕ1, ϕ2), (ϕ1, ϕ0), and (ϕ0, ϕ1) in the eight detection sub-circuits 91.sub.k. At the end of the sampling, only the sub-circuit 91.sub.k having sampled two control signals in the high state on the rising edges of signals Q1 and Q2 will deliver an output signal in the high state, enabling to select a corresponding value of voltage V.sub.PH.

(94) In the example of FIG. 9, the pixel performs a phase quantization over three bits. As an example, the value of the phase of the modulated light beam is considered as being equal to: 0 when signal Phz<0:7> is ‘10000000’ (crossing of threshold TH first by sample I0 and then by sample I3); π/4 when signal Phz<0:7> is ‘01000000’ (crossing of threshold TH first by sample I3 and then by sample I0); π/2 when signal Phz<0:7> is ‘00100000’ (crossing of threshold TH first by sample I3 and then by sample I2); 3π/4 when signal Phz<0:7> is ‘00010000’ (crossing of threshold TH first by sample I2 and then by sample I3); π when signal Phz<0:7> is ‘00001000’ (crossing of threshold TH first by sample I2 and then by sample I1); 5π/4 when signal Phz<0:7> is ‘00000100’ (crossing of threshold TH first by sample I1 and then by sample I2); 3π/2 when signal Phz<0:7> is ‘000000010’ (crossing of threshold TH first by sample I1 and then by sample I0); and 7π/4 when signal Phz<0:7> is ‘00000001’ (crossing of threshold TH first by sample I0 and then by sample I1).

(95) FIG. 10 is a simplified electric diagram of an alternative embodiment of the phase detection circuit 80 of the pixel of FIG. 6. Such a variant enables, on generation of phase signal V.sub.PH, in the case of a pixel structure of the type described in relation with FIG. 5, to compensate for possible surface unevennesses of upper glass layer 68 or for thickness variations of liquid crystal layer 62. Indeed, in a structure of the type described in relation with FIG. 5, glass layer 68 may be common to all the sensor pixels. If layer 68 is not perfectly planar, or if the layer is not arranged strictly parallel to pixel array 50, the lack of uniformity of the thickness of layer 62 may introduce different phase shifts of the reflected light beam between different pixels of the sensor for a same biasing V.sub.PH. In the variant of FIG. 10, phase detection circuit 80 is configured to adjust voltage V.sub.PH according to predetermined calibration data, to compensate for phase differences due to the thickness differences of layer 68 and/or 62 between different sensor pixels.

(96) In the example of FIG. 10, phase detection circuit 80 comprises four flip-flops 81 and one switch 84 comprising four switches 84.sub.i, arranged similarly to what has been described in relation with FIG. 6, with the difference that, in the example of FIG. 10, the conduction nodes of switches 84.sub.0, 84.sub.1, 84.sub.2, and 84.sub.3 are not directly connected to the nodes of application of bias voltages Vpol<0>, respectively Vpol<1>, respectively Vpol<2>, respectively Vpol<3>, but are connected to intermediate nodes n.sub.0, respectively n.sub.1, respectively n.sub.2, respectively n.sub.3.

(97) The phase detection circuit 80 of FIG. 10 further comprises a compensation circuit 150 forming an interface between the nodes of application of bias voltages Vpol<0>, Vpol<1>, Vpol<2>, and Vpol<3> and nodes n.sub.0, n.sub.1, n.sub.2, and n.sub.3.

(98) Compensation circuit 150 comprises four switches 152.sub.i, each comprising four switches 152.sub.ii′i′ being an integer in the range from 0 to 3.

(99) Each switch 152.sub.i is configured to apply to the node n.sub.i of same rank i one among the four bias voltages Vpol<0>, Vpol<1>, Vpol<2>, and Vpol<3>. More particularly, in the present example, switch 152.sub.0 comprises four switches 152.sub.00, 152.sub.01, 152.sub.02, 152.sub.03, each having a first conduction node coupled, for example, connected, to a node of application of bias voltage Vpol<0>, respectively Vpol<1>, respectively Vpol<2>, respectively Vpol<3>, and a second conduction node coupled, for example, connected, to node no. Switch 152.sub.1 comprises four switches 152.sub.10, 152.sub.11, 152.sub.12, 152.sub.13, each having a first conduction node coupled, for example, connected, to a node of application of bias voltage Vpol<1>, respectively Vpol<2>, respectively Vpol<3>, respectively Vpol<0> and a second conduction node coupled, for example, connected, to node n.sub.1. Switch 1522 comprises four switches 152.sub.20, 152.sub.21, 152.sub.22, 152.sub.23, each having a first conduction node coupled, for example, connected, to a node of application of bias voltage Vpol<2>, respectively Vpol<3>, respectively Vpol<0>, respectively Vpol<1>, and a second conduction node coupled, for example, connected, to node n.sub.2. Switch 152.sub.3 comprises four switches 152.sub.30, 152.sub.31, 152.sub.32, 152.sub.33, each having a first conduction node coupled, for example, connected, to a node of application of bias voltage Vpol<3>, respectively Vpol<0>, respectively Vpol<1>, respectively Vpol<2>, and a second conduction node coupled, for example, connected, to node n.sub.3.

(100) Switches 152.sub.00, 152.sub.10, 152.sub.20, and 152.sub.30 have their control nodes connected to a same node of application of a control signal cfg0. Switches 152.sub.01, 152.sub.11, 152.sub.21, and 152.sub.31 have their control nodes connected to a same node of application of a control signal cfg1. Switches 152.sub.02, 152.sub.12, 152.sub.22, and 152.sub.32 have their control nodes connected to a same node of application of a control signal cfg2. Switches 152.sub.03, 152.sub.13, 152.sub.23, and 152.sub.33 have their control nodes connected to a same node of application of a control signal cfg3.

(101) Control signals cfgi are mutually exclusive, that is, a single one of the four switch assemblies {152.sub.00, 152.sub.10, 152.sub.20, 152.sub.30}, {152.sub.01, 152.sub.11, 152.sub.21, 152.sub.31}, {152.sub.02, 152.sub.12, 152.sub.22, 152.sub.32}, and {152.sub.03, 152.sub.13, 152.sub.23, 152.sub.33} may be turned on at the same time.

(102) Control signals cfgi are generated from a digital calibration value coded over two bits, calib0 and calib1, previously determined and stored in the pixel. In this example, compensation circuit 150 comprises two D flip-flops 154 and 155. D flip-flop 154 comprises a d data input node having signal calib0 applied thereto, and a control node having a signal CKcalib for sampling the calibration value applied thereto. D flip-flop 155 comprises a d data input node having signal calib1 applied thereto, and a control node having signal CKcalib applied thereto. The compensation circuit 150 of FIG. 10 further comprises a logic circuit 160 for decoding the digital calibration value capable of generating control signals cfg0, cfg1, cfg2, and cfg3 from the binary values calib0 and calib1 stored in flip-flops 154 and 155. In this example, circuit 160 comprises four AND gates 162, 163, 164, and 165, each having two inputs and one output. AND gate 162 has two complemented inputs respectively connected to an s output node of flip-flop 154 and to an s output node of flip-flop 155. AND gate 163 has a non-complemented input and a complemented input respectively connected to an s output node of flip-flop 154 and to an s output node of flip-flop 155. AND gate 164 has a complemented input and a non-complemented input respectively connected to an s output node of flip-flop 154 and to an s output node of flip-flop 155. AND gate 165 has two non-complemented inputs respectively connected to an s output node of flip-flop 154 and to an s output node of flip-flop 155. The outputs of AND gates 162, 163, 164, and 165 respectively deliver the signals cfg0, cfg1, cfg2, and cfg3 for controlling switches 152.sub.ii′.

(103) As a variation, instead of providing one compensation circuit 150 per pixel, the sensor pixels may be distributed into a plurality of sub-assemblies of neighboring pixels, a same compensation circuit being shared by all the pixels of a same sub-assembly and distinct compensation circuits being provided for distinct sub-assemblies.

(104) Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants may be combined, and other variants will occur to those skilled in the art. In particular, although examples of pixels and of operation based on a demodulation with K=4 phases of the modulated optical signal have been described hereabove, the described embodiments are not limited to this specific case. As a variation, the demodulation may be performed over any other number K of phases greater than or equal to 2. It will be within the abilities of those skilled in the art to accordingly adapt the pixel circuits, particularly to acquire a number of samples different from four at each modulation period T.sub.US of acquisition phase T.sub.acq. The formulas of reconstruction of the real and imaginary parts of the complex field of the object beam may further be adapted accordingly. It should in particular be noted that in the case of a demodulation over more than four phases, in the same spirit as what has been described in relation with FIG. 9, the order in which threshold TH is crossed by more than two samples may be detected to generate a phase value quantized over more than three bits.

(105) Further, although only examples of application to acousto-optic imaging, particularly in the medical field, have been described hereabove, the above-described solution of generation, within a pixel, of a signal representative of the phase of a modulated optical signal, by detection of an order in the crossing of a predetermined voltage threshold by a plurality of pixel integration capacitors, may be used in other applications. As an example, pixels of the above-described type may be used for applications of distance measurement by measurement of the time of flight of a modulated light beam or, more generally, for any application requiring a measurement of the phase of an optical signal having its intensity modulated at an acoustic frequency, for example, a frequency in the range from 20 kHz to 50 MHz.

(106) Further, the described embodiments are not limited to the specific embodiments of the integration circuit described in relation with FIGS. 6 and 9. In these examples, the capacitors Ci of the integration circuit are discrete capacitors coupled in parallel with an operational amplifier and switched by means of switches ϕi. As a variation, the described embodiments may be adapted to a pixel architecture of the type described in document U.S. Pat. No. 10,162,048 (and in particular with FIGS. 4A to 7 of this document), incorporated herein by reference. In this case, the photodiode is a pinned photodiode. Each integration capacitor comprises a doped semiconductor region juxtaposed to the photodiodes and separated from of the photodiode by a transfer gate enabling to open or to close a potential barrier separating a charge storage region of the photodiode from said semiconductor region. Each integration capacitor is for example a pinned diode for example having a pinch-off voltage higher than that of the photodiode. The charge transfers from the photodiode to the integration capacitors are controlled via the transfer gates. The transfer gates then replace the switches ϕi of the examples of FIGS. 6 and 9. The adaptation of the provided solution to this type of architecture is within the abilities of those skilled in the art on reading of the present disclosure. As in the examples of FIGS. 6 and 9, a charge compensation of the light offset may be provided for each switching of comparator 74. Such a compensation may be performed by means of a charge injection circuit identical or similar to the circuit 72 of FIGS. 6 and 9. As a variation, the offset compensation may be implemented by using a charge injection circuit capable of injecting a same quantity of charges into each integration capacitor, as described in the article entitled “Compact Ambient Light Cancellation Design and Optimization for 3D Time-of-Flight Image Sensors” of Yibing M. Wang et al. (2013 International Image Sensor Workshop).

(107) Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.