Circuit system having compact decoupling structure

Abstract

A circuit system having compact decoupling structure, including: a mother board; at least one circuit unit, each having a substrate, a logic-circuit die, a plurality of first metal contacts, and a plurality of second metal contacts, the substrate having a first surface and a second surface, the first metal contacts being formed on the first surface and soldered onto the mother board, the second metal contacts being formed on the logic-circuit die and soldered onto the second surface to form flip-chip pillars, and the flip-chip pillars determining a height of a gap between the die and the substrate; and at least one decoupling unit for providing an AC signals decoupling function for the at least one circuit unit; wherein each of the at least one decoupling unit is placed in the gap of one said circuit unit and includes a mother die and at least one stack-type integrated-passive-device die.

Claims

1. A circuit system having compact decoupling structure, comprising: a mother board; a substrate; the substrate comprising a first surface and a second surface opposing the first surface; a plurality of first metal contacts; the plurality of first metal contacts being formed on the first surface of the substrate; the plurality of first metal contacts being soldered onto a surface of the mother board: a logic-circuit die; a surface of the logic-circuit die facing the second surface of the substrate; a plurality of second metal contacts; the plurality of second metal contacts being formed on the surface of the logic-circuit die; the plurality of second metal contacts being soldered onto the second surface of the substrate; the plurality of second metal contacts forming a plurality of flip-chip pillars; the flip-chip pillars determining a height of a gap between the logic-circuit die and the substrate; a mother die; a surface of the mother die facing the surface of the logic-circuit die; a plurality of third metal contacts; the plurality of third metal contacts being formed on the surface of the mother die; the plurality of third metal contacts being soldered onto the surface of the logic-circuit die; at least one decoupling capacitor; the at least one decoupling capacitor being formed in a gap between the mother die and the logic-circuit die; the at least one decoupling capacitor being configured for providing a capacitance density to perform an AC signals decoupling function for the logic-circuit die; a plurality of fourth metal contacts; the plurality of fourth metal contacts being formed on a surface of the at least one decoupling capacitor; the plurality of fourth metal contacts being soldered onto the surface of the mother die; the surface of the at least one decoupling capacitor facing the surface of the mother die; and the gap between the mother die and the logic-circuit die being smaller than the gap between the logic-circuit die and the substrate.

2. The circuit system having compact decoupling structure as disclosed in claim 1, wherein the second metal contacts are controlled-collapse-chip-connection bumps.

3. The circuit system having compact decoupling structure as disclosed in claim 1, wherein the third metal contacts are controlled-collapse-chip-connection bumps.

4. The circuit system having compact decoupling structure as disclosed in claim 1, wherein the fourth metal contacts are Cu-pillar-with-solder-cap bumps.

5. The circuit system having compact decoupling structure as disclosed in claim 1, wherein the decoupling capacitor is a stack-type capacitor having multiple MIM (metal-insulator-metal) sandwich layers.

6. The circuit system having compact decoupling structure as disclosed in claim 1, wherein the first metal contacts are BGA contacts.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 illustrates a cross-sectional view of a circuit system having a decoupling structure of prior art.

(2) FIG. 2 illustrates a cross-sectional view of another circuit system having a decoupling structure of prior art.

(3) FIG. 3 illustrates a cross-sectional view of a circuit system having compact decoupling structure according to one embodiment of the present invention.

(4) FIG. 4 illustrates a cross-sectional view of a circuit system having compact decoupling structure according to another embodiment of the present invention.

(5) FIG. 5 illustrates a cross-sectional view of a circuit system having compact decoupling structure according to still another embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(6) Please refer to FIG. 3, which illustrates a cross-sectional view of a circuit system having compact decoupling structure according to one embodiment of the present invention. As illustrated in FIG. 3, the circuit system having compact decoupling structure includes a mother board 100, at least one circuit unit 110, and at least one decoupling unit 120.

(7) The mother board 100 is used for carrying the at least one circuit unit 110 and the at least one decoupling unit 120.

(8) Each circuit unit 110 has a substrate 111, at least one die 112, and a plurality of first metal contacts 113.

(9) The substrate 111 has a first surface 111a and a second surface 111b opposing the first surface 111a.

(10) The at least one die 112, which can be a logic-circuit die, has a plurality of second metal contacts 113a. The second metal contacts 113a can be C4 (controlled-collapse-chip-connection) bumps formed on the die 112 and soldered onto the second surface 111b to form flip-chip pillars, and thereby determine the height of a gap between the die 112 and the substrate 111, the gap being used for accommodating the decoupling unit 120.

(11) The first metal contacts 113, which can be BGA (ball grid array) contacts, are formed on the first surface 111a and soldered onto the mother board 100.

(12) The decoupling unit 120 is placed in the gap and soldered onto the die 112 for providing an AC signals decoupling function for the circuit unit 110. The decoupling unit 120 includes a mother die 120a, at least one stack-type integrated-passive-device die 120b, a plurality of third metal contacts 120c, and a plurality of fourth metal contacts 120d.

(13) The third metal contacts 120c, which can be C4 (controlled-collapse-chip-connection) bumps, are formed on the mother die 120a and soldered onto the die 112, and each of the at least one stack-type integrated-passive-device die 120b has the fourth metal contacts 120d, which can be C2 (Cu-pillar-with-solder-cap) bumps, formed thereon and soldered onto the mother die 120a.

(14) In a preferred embodiment, the at least one stack-type integrated-passive-device die 120b includes at least one decoupling capacitor, which is preferred to be stack-type capacitor to provide a high capacitance density. In addition, the stack-type capacitor can have multiple MIM (metal-insulator-metal) sandwich layers stacked in a small volume to provide sufficient capacitance for the AC signals decoupling function.

(15) Accordingly, the circuit system of FIG. 3 can have a compact decoupling structure to provide a low profile form factor. In addition, due to the high capacitance density of the stack-type capacitor and close proximity of the decoupling unit 120 to the die 112, the compact decoupling structure can provide low parasite resistance and low parasite inductance to optimize the AC signals decoupling function.

(16) Please refer to FIG. 4, which illustrates a cross-sectional view of a circuit system having compact decoupling structure according to another embodiment of the present invention. As illustrated in FIG. 4, the circuit system having compact decoupling structure includes a mother board 100, at least one circuit unit 110, and at least one decoupling unit 120.

(17) The mother board 100 is used for carrying the at least one circuit unit 110 and the at least one decoupling unit 120.

(18) Each circuit unit 110 has a substrate 111, at least one die 112, and a plurality of metal contacts 113, the substrate 111 having a first surface 111a and a second surface 111b opposing the first surface 111a, the at least one die 112 being formed on the first surface 111a, the metal contacts 113 being formed on the second surface 111b and soldered onto the mother board 100. A gap is formed between the substrate 111 and the mother board 100 and has a height less than 50 micrometers. In a possible embodiment, the metal contacts are BGA (ball grid array) contacts.

(19) The at least one decoupling unit 120 is placed in the gap and soldered onto the substrate 111 for providing an AC signals decoupling function for the at least one circuit unit 110.

(20) In a preferred embodiment, the decoupling unit 120 includes a discrete capacitor having a height less than 30 micrometers, and the discrete capacitor is preferred to be a stack-type capacitor to provide a high capacitance density. The stack-type capacitor can have multiple MIM (metal-insulator-metal) sandwich layers stacked in a small volume to provide sufficient capacitance for the AC signals decoupling function.

(21) Accordingly, the circuit system of FIG. 4 can have a compact decoupling structure to provide a low profile form factor. In addition, due to the high capacitance density of the stack-type capacitor and close proximity of the decoupling unit 120 to the circuit unit 110, the compact decoupling structure can provide low parasite resistance and low parasite inductance to optimize the AC signals decoupling function.

(22) Please refer to FIG. 5, which illustrates a cross-sectional view of a circuit system having compact decoupling structure according to still another embodiment of the present invention. As illustrated in FIG. 5, the circuit system having compact decoupling structure includes a mother board 100, at least one circuit unit 110, and at least one decoupling unit 120.

(23) The mother board 100 is used for carrying the at least one circuit unit 110 and the at least one decoupling unit 120.

(24) Each circuit unit 110 has a substrate 111, at least one first die 112a, at least one second die 112b, and a plurality of metal contacts 113, the substrate 111 having a first surface 111a and a second surface 111b opposing the first surface 111a.

(25) The at least one first die 112a is formed on the first surface 111a, and the at least one second die 112b is embedded in an inner region 1111 of the substrate 111, the inner region 1111 having a height less than 50 micrometers.

(26) The metal contacts 113 are formed on the second surface 111b and soldered onto the mother board 100, and a gap is formed between the substrate 111 and the mother board 100 and has a height less than 50 micrometers. In a possible embodiment, the metal contacts 113 are BGA (ball grid array) contacts.

(27) The at least one decoupling unit 120 is placed in the inner region 1111 and connected electrically with the at least one second die 112b in close proximity, or placed in the gap and soldered onto the substrate 111 for providing an AC signals decoupling function for the at least one circuit unit 110.

(28) In a preferred embodiment, the decoupling unit 120 includes a discrete capacitor having a height less than 30 micrometers, and the discrete capacitor is preferred to be a stack-type capacitor to provide a high capacitance density. The stack-type capacitor can have multiple MIM (metal-insulator-metal) sandwich layers stacked in a small volume to provide sufficient capacitance for the AC signals decoupling function.

(29) Accordingly, the circuit system of FIG. 5 can have a compact decoupling structure to provide a low profile form factor. In addition, due to the high capacitance density of the stack-type capacitor and close proximity of the decoupling unit 120 to the circuit unit 110, the compact decoupling structure can provide low parasite resistance and low parasite inductance to optimize the AC signals decoupling function.

(30) Thanks to the designs mentioned above, the present invention can therefore provide the advantages as follows:

(31) 1. The circuit system having compact decoupling structure of the present invention can provide a low profile form factor.

(32) 2. The circuit system having compact decoupling structure of the present invention can provide low parasite resistance and low parasite inductance to optimize the AC signals decoupling function.

(33) While the invention has been described by way of example and in terms of preferred embodiments, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.

(34) In summation of the above description, the present invention herein enhances the performance over the conventional structure and further complies with the patent application requirements and is submitted to the Patent and Trademark Office for review and granting of the commensurate patent rights.