Single-phase voltage source inverter circuit with power decoupling, and control methods

Abstract

A single-phase voltage source inverter including a first stage configured to be connectable to a DC source, and a second stage configured to be connectable to an AC load, the first stage including a bridge leg including first and second decoupling switches, the bridge leg connected through an inductor to a decoupling capacitor, where the decoupling capacitor is in series with the DC source when the inverter is connected to the DC source, and the second stage including a bi-directional H-bridge inverter including first, second, third and fourth switches. The decoupling capacitor can be a small film capacitor. The first and second decoupling switches are the only decoupling switches in the bridge leg. The first controller can use pulse width modulation and the second controller uses sinusoidal pulse width modulation. The first controller can use pulse width modulation and the second controller uses pulse energy modulation.

Claims

1. A single-phase voltage source inverter comprising: a first stage adapted to be connected to a DC source, wherein the DC source provides an input DC current and a second stage adapted to be connected to an AC load, whereby the AC load includes a second-order ripple power as produced by an AC voltage and an AC current, the first stage comprising a bridge leg comprising first and second current-bidirectional decoupling switches, the bridge leg connected through an inductor connected between the decoupling switches to a small film decoupling capacitor, where the decoupling capacitor is in series with the DC source when the inverter is connected to the DC source, whereby current can flow into and out of the decoupling capacitor bi-directionally, the second stage comprising a bi-directional inverter comprising first, second, third and fourth switches, a first controller for modulating the first stage to provide power decoupling functionality comprising diverting the second-order ripple power into the small film decoupling capacitor, whereby the second-order ripple is removed from the input DC current, and a second controller for modulating the second stage.

2. The single-phase voltage source inverter of claim 1, wherein the first and second decoupling switches are the only decoupling switches in the bridge leg.

3. The single-phase voltage source inverter of claim 1, wherein the bi-directional inverter is an H-bridge.

4. The single-phase voltage source inverter of claim 1, wherein the first controller uses pulse width modulation and the second controller uses sinusoidal pulse width modulation.

5. The single-phase voltage source inverter of claim 1, wherein the first controller uses sinusoidal pulse width modulation and the second controller uses pulse energy modulation.

6. The single-phase voltage source inverter of claim 1, wherein the AC load is an AC grid.

7. The single-phase voltage source inverter of claim 1, wherein the small film capacitor has a capacitance measured in micro Farads.

8. The single-phase voltage source inverter of claim 1, wherein the small film capacitor has a capacitance of 160 micro Farads.

9. The single-phase voltage source inverter of claim 1, wherein modulating the first stage to provide power decoupling functionality in the first stage further comprises: controlling voltage across the decoupling capacitor as a DC-biased sine wave, adding a DC component of the voltage across the decoupling capacitor with input DC voltage from the DC source thereby providing voltage-boosting functionality, and cancelling out the second-order ripple power using an AC component of the voltage across the decoupling capacitor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) To facilitate further description of the embodiments, the following drawings are provided in which:

(2) FIG. 1 illustrates a schematic of a prior art H-bridge inverter with a flying capacitor DC-DC converter;

(3) FIG. 2 illustrates a schematic of a power inverter system, according to an embodiment of the present disclosure;

(4) FIG. 3 illustrates a control diagram according to an embodiment of the present disclosure;

(5) FIGS. 4a-4c illustrate plots of voltage and current waveforms of an inverter with only voltage-boosting capability;

(6) FIGS. 4d-f illustrate plots of voltage and current waveforms of an inverter with both voltage-boosting and power decoupling capabilities according to embodiments of the present disclosure;

(7) FIG. 5a illustrates a plot of experimental results for the proposed inverter without power decoupling control;

(8) FIG. 5b illustrates a plot of experimental results for an inverter with power decoupling control according to an embodiment of the present disclosure;

(9) FIG. 6 illustrates a control diagram according to another embodiment of the present disclosure;

(10) FIG. 7a illustrates a simulation result of a pulse energy modulation (PEM) method according to an embodiment of the present disclosure for controlling an inverter without power decoupling; and

(11) FIG. 7b illustrates a simulation result of a PEM method according to an embodiment of the present disclosure for controlling an inverter with power decoupling.

DETAILED DESCRIPTION OF EXAMPLES OF EMBODIMENTS

(12) According to an embodiment, the present invention relates to an inverter topology with voltage boosting and power decoupling, which has advantages such as adapting to various DC input voltages and eliminating the large electrolytic capacitor. The inverter topology of the present embodiment maintains the advantages of a bridge inverter, while adding the functionalities of active power decoupling and adapting to a wide range of input voltage.

(13) According to another embodiment, the present invention relates to a single-phase voltage source inverter including a first stage configured to be connectable to a DC source, and a second stage configured to be connectable to an AC load which in some embodiments includes an AC grid, the first stage comprising a bridge leg comprising first and second decoupling switches, the bridge leg connected through an inductor to a decoupling capacitor, where the decoupling capacitor is in series with the DC source when the inverter is connected to the DC source, and the second stage comprising a bi-directional inverter, such as an H-bridge inverter including first, second, third and fourth switches. In one embodiment, the decoupling capacitor is a small film capacitor. In another embodiment, the first and second decoupling switches are the only decoupling switches in the bridge leg. In other embodiments, other types of bi-directional inverters can be used. In some embodiments, the inverter further includes a first controller for modulating the first stage and a second controller for modulating the second stage. In some embodiments, the first controller uses pulse width modulation and the second controller uses sinusoidal pulse width modulation. In other embodiments, the first controller uses pulse width modulation and the second controller uses pulse energy modulation.

(14) According to another embodiment, the present invention relates to a method of modulating a bi-directional inverter using pulse energy modulation to provide triggering signals to the switches of the inverter.

(15) Topology Design

(16) FIG. 2 is a schematic diagram illustrating a single-phase voltage source inverter (VSI) system indicated generally at 2 according to an embodiment of the present invention. The VSI 2 is configured to provide both voltage-boosting and power decoupling functions. The VSI 2 is further configured to connect to a DC source (such as a photovoltaic DC source 4 illustrated in FIG. 2) and an AC load (such as an AC power grid 6 illustrated in FIG. 2).

(17) The VSI 2 includes a first stage 8 with voltage-boosting and power decoupling functionalities and a second stage 10 with power inversion functionality. In the present embodiment, the first stage 8 is a bi-directional buck-boost converter and includes a bridge leg 12 connected through an inductor L to a decoupling capacitor C.sub.D where the decoupling capacitor C.sub.D is in series with the DC source 4. The bridge leg 12 includes switches S.sub.c1 and S.sub.c2. The inductor L has high flexibility because it does not need to withstand DC current from the DC source 4, whereas an inductor in a typical prior art boost inverter does. In other embodiments, the positions of the DC source 4 and the decoupling capacitor C.sub.D, as illustrated in FIG. 2, can be interchanged.

(18) The second stage 10 includes a bi-directional inverter which in the present embodiment is an H-bridge which includes switches S.sub.a1 and S.sub.a2, and S.sub.b1 and S.sub.b2. In other embodiments, other suitable bi-directional inverters can be used. The switches Sai and S.sub.a2, and S.sub.b1 and S.sub.b2 are connect to AC load 6 through inductor L.sub.f and capacitor C.sub.f which function as an AC filter. In other embodiments, an AC filter can be integrated with the bi-directional inverter.

(19) Voltage-Boosting Capability

(20) In the first stage 8, the inductor current is always continuous with complementary triggering signal for the bridge leg 12. The relationship between input DC voltage V.sub.DC and the voltage v.sub.CD across the decoupling capacitor C.sub.D is:

(21) $\begin{array}{cc}{v}_{C_D}=\frac{d}{1-d}.Math.V_{DC}& \left(1\right)\end{array}$
where d is the duty cycle of S.sub.C.sub.1 in the buck-boost converter and the value of d is between 0 and 1.

(22) With the first stage 8, the DC-link voltage v.sub.link of the VSI 2 can be calculated as:

(23) $\begin{array}{cc}{}_{\mathrm{link}}=V_{DC}+v_{C_D}=\frac{1}{1-d}.Math.V_{DC}& \left(2\right)\end{array}$

(24) It can be seen from the relationship between v.sub.link and V.sub.DC that the buck-boost converter 8 has the voltage-boosting capability, that V.sub.link is always greater than V.sub.DC, and the value of v.sub.link can be determined by the duty cycle of S.sub.C.sub.1.

(25) Power Decoupling Function

(26) To achieve the power decoupling function, the voltage across the power decoupling capacitor C.sub.D is controlled as a DC-biased sine wave. The DC component of the capacitor voltage v.sub.C.sub.D, is added with input DC voltage, voltage V.sub.DC, to achieve the voltage-boosting function, and the AC component of the capacitor voltage v.sub.C.sub.D, is used to cancel out the second-order ripple power. The DC-link voltage v.sub.link must always be higher than the peak value of the output AC voltage, to ensure that there is no over-modulation or even malfunction for the bridge inverter of the second stage 10.

(27) The inverter topology in the present embodiment diverts the second-order ripple power into the decoupling capacitor C.sub.D without the need for a bulky/large electrolytic capacitor on the DC side indicated generally at 14 of the VSI 2. In the present embodiment, the decoupling capacitor C.sub.D is a small film capacitor with a capacitance of 160 uF. In other embodiments, other suitable small film capacitors can be used. A bulky/large electrolytic capacitor often has a short lifespan and typically has a capacitance of a few thousand micro-Farads. The range of the decoupling capacitor voltage v.sub.C.sub.D is allowed to be wide so that a small film capacitor is adequate to absorb the second-order ripple power and current. The voltage across the decoupling capacitor is controlled as a DC-biased sine wave, and the DC offset in decoupling capacitor C.sub.D is used to boost the DC-link voltage v.sub.link, as opposed to being under-utilized as in prior art DC-voltage power decoupling techniques.

(28) To achieve power decoupling, a power flow analysis of the VSI 2 is investigated in the following. Suppose the VSI 2 is operated with unity power factor, then the voltage and current of the AC load 6 are as follows:
v.sub.o=V.sub.o.Math.sin(t)(3)
i.sub.o=I.sub.o.Math.sin(t)(4)
where V.sub.o and I.sub.o are the peak values of the AC load 6 voltage and current. The current through filtering capacitor C.sub.f can be calculated as:

(29) $\begin{array}{cc}{i}_{C_f}=C_f.Math.\frac{d{}_o}{\mathrm{dt}}=I_{C_f}.Math.\cos \left(t\right)& \left(5\right)\end{array}$
where I.sub.C.sub.f=C.sub.fV.sub.o is the peak current through filtering capacitor C.sub.f.

(30) The instantaneous power absorbed by the AC load 6 and by the filtering capacitor C.sub.f are, respectively,

(31) $\begin{array}{cc}{p}_o=v_o{i}_o=\frac{V_o{I}_o}{2}-\frac{V_o{I}_o}{2}.Math.\cos \left(2t\right)& \left(6\right)\end{array}$
and

(32) $\begin{array}{cc}{p}_{C_f}=v_o{i}_{C_f}=\frac{V_o{I}_{C_f}}{2}.Math.\sin \left(2t\right)& \left(7\right)\end{array}$
from which it can be seen that the second-order pulsating power comes from both the AC load 6 and the filtering capacitor C.sub.f. To balance the second-order pulsating power on the AC side indicated generally at 16, the VSI 2 is controlled to divert the second-order pulsating power into the decoupling capacitor C.sub.D on the DC side 14, where the decoupling capacitor voltage v.sub.C.sub.D is controlled such that the instantaneous power p.sub.C.sub.D absorbed by C.sub.D becomes:
p.sub.C.sub.D=P.sub.o.Math.cos(2t)P.sub.C.sub.f.Math.sin(2t)(8)
where

(33) $P_o=\frac{V_o{I}_o}{2}$
and

(34) $P_{C_f}=\frac{V_o{I}_{C_f}}{2}.$

(35) The voltage across the decoupling capacitor C.sub.D is basically a DC-biased sine wave, which contains a DC offset V.sub.d and an additional AC component v.sub.add. Suppose the voltage across the decoupling capacitor C.sub.D is:
v.sub.C.sub.D=V.sub.d+v.sub.add(9)

(36) Then the current flowing through the decoupling capacitor can be calculated as:
i.sub.C.sub.D=C.sub.D{dot over (v)}.sub.C.sub.D=C.sub.D{dot over (v)}.sub.add(10)
where .Math. denotes the derivative of the variable.

(37) The instantaneous power p.sub.C.sub.D absorbed by C.sub.D is calculated as:
p.sub.C.sub.D=v.sub.C.sub.Di.sub.C.sub.D=C.sub.DV.sub.d{dot over (v)}.sub.add+C.sub.Dv.sub.add{dot over (v)}.sub.add(11)

(38) Combining Equation (8) with Equation (11) yields:
C.sub.DV.sub.d{dot over (v)}.sub.add+C.sub.Dv.sub.add{dot over (v)}.sub.add=P.sub.o.Math.cos(2t)P.sub.C.sub.f.Math.sin(2t)(12)

(39) Taking the integral for both sides, a quadratic equation with respect to v.sub.add is obtained:

(40) $\begin{array}{cc}{C}_D{v}_{add}^2+2C_D{V}_d{v}_{add}=\frac{V_o{I}_o}{2}.Math.\sin \left(2t\right)+\frac{V_o^2{C}_f}{2}.Math.\cos \left(2t\right)& \left(13\right)\end{array}$

(41) From the quadratic function, the additional AC component v.sub.add is solved as:

(42) $\begin{array}{cc}{v}_{add}=-V_d+\sqrt{V_d^2+\frac{V_o{I}_o}{2c}\sin \left(2t\right)+\frac{c_f}{2C_D}{V}_o^2\cos \left(2t\right)}& \left(14\right)\end{array}$

(43) Thus, the reference decoupling capacitor voltage is calculated as:

(44) 0$\begin{array}{cc}{v}_{C_D}=\sqrt{V_d^2+\frac{V_o{I}_o}{2C}\sin \left(2t\right)+\frac{C_f}{2C_D}{V}_o^2\cos \left(2t\right)}& \left(15\right)\end{array}$
which can be used to control duty cycles of the decoupling switches (i.e. S.sub.c1 and S.sub.c2) of the first stage 8 to achieve the power decoupling function.

(45) Since the output voltage of a traditional prior art bridge inverter is always limited by the input DC voltage, voltage-boosting is required if the peak voltage of the AC output is higher than the input DC voltage. The inverter topology according to embodiments of the present invention is able to boost the input DC voltage, ensuring that the DC-link voltage is always higher than the peak output AC voltage. The added inductor L has high flexibility because it does not need to withstand DC current as the inductor in a prior art boost converter does. Moreover, the decoupling switches are easy to modulate by a complementary triggering signal.

(46) As illustrated in FIG. 2, since the first stage 8 buck-boost converter is a bidirectional buck-boost converter, where the inductor current can be controlled as always continuous, the relationship between input DC voltage V.sub.DC and the voltage v.sub.C.sub.D across the decoupling capacitor C.sub.D is expressed according to Equation (1).

(47) With the connection in FIG. 2, the DC-link voltage v.sub.link of the H-bridge of the second stage 10 can be calculated according to Equation (2).

(48) It can be seen from the relationship between v.sub.link and V.sub.DC that the first stage 8 has the voltage-boosting capability, and the value of v.sub.link can be determined by the duty cycle of S.sub.C1. According to an embodiment, the H-bridge of the second stage 10 can be simply modulated by sinusoidal pulse-width modulation (SPWM).

(49) Active Power Decoupling Method

(50) According to another embodiment, the present disclosure relates to an active power decoupling method. The method can comprise a power decoupling control method based on the power transfer, calculating the duty cycles of the switches according to demanded power, making the modulation technique more direct without adding a low-order ripple component.

(51) The instantaneous power absorbed by the AC load 6 and by filtering capacitor C.sub.f are, respectively,

(52) $\begin{array}{cc}{p}_o=v_o{i}_o=\frac{V_o{I}_o}{2}-\frac{V_o{I}_o}{2}.Math.\cos \left(2t\right)& \left(16\right)\end{array}$
and

(53) $\begin{array}{cc}{P}_{C_f}=v_o{i}_{C_f}=\frac{V_o{I}_{C_f}}{2}.Math.\sin \left(2t\right)& \left(17\right)\end{array}$

(54) The reference decoupling capacitor voltage is calculated as:

(55) $\begin{array}{cc}{V}_{C_D}=\sqrt{V_d^2+\frac{V_o{I}_o}{2C}\sin \left(2t\right)+\frac{C_f}{2C_D}{V}_o^2\cos \left(2t\right)}& \left(18\right)\end{array}$

(56) A control block diagram for modulating the VSI 2 is shown in FIG. 3, including the inverter stage control and the power decoupling control. Different from waveform control in some literature [6]-[8], the control method of the present embodiment achieves successful power decoupling without adding any low-order harmonics. The control block diagram for the topology with SPWM is shown in FIG. 3, including the inverter stage control and the power decoupling control. In the inverter stage control, a proportional-resonant controller (PR Controller) is employed instead of a traditional proportional-integral (PI) controller to track the reference AC current, for the PR controller has better sinusoidal signal response. The power decoupling control achieves the desired capacitor voltage based on above equations, which is also added to the DC input voltage to reach higher DC-link voltage to ensure proper operation in the inverter stage control.

(57) Referring to FIG. 3, Power Decoupling Control 18 controls the first stage 8 and in particular, switches S.sub.c1 and S.sub.c2, while Power Inverter Control 20 controls the second stage 10 and in particular, the switches S.sub.a1, S.sub.a2, S.sub.b1 and S.sub.b2. T.sub.c1 and T.sub.C2 are the triggering signals for the switches S.sub.c1 and S.sub.c2, respectively, while T.sub.a1, T.sub.a2, T.sub.b1 and T.sub.b2 are the triggering signals for switches S.sub.a1, S.sub.a2, S.sub.b1 and S.sub.b2, respectively.

(58) According to another embodiment, to increase the flexibility for component design and inverter control, a pulse energy modulation (PEM) method is proposed as an alternative modulation method to sinusoidal pulse width modulation (SPWM) for the bridge inverter of the second stage 10. A control block for modulating the bridge inverter using PEM is illustrated in FIG. 6. The bridge inverter can then be operated under the discontinuous conduction mode (DCM) when the instantaneous output power is low, and under the continuous conduction mode (CCM) when the instantaneous output power is high. The switching losses of the bridge inverter are reduced due to the zero-current switching under DCM. In addition, PEM modulates the bridge inverter based on the energy transfer, making the inverter operation less sensitive to the input voltage fluctuation and AC grid harmonics than SPWM does. In other embodiments, a modulation method using PEM can be used to modulate bridge inverters with other converters as the first stage.

(59) In PEM, the operation principles of the bridge inverter can be described by the following two operating half cycles: Positive half cycle (PHC): S.sub.a1 remains on, S.sub.a2 and S.sub.b1 remain off; S.sub.b2 is controlled on and off, acting like a buck chopper, to produce a half sine wave at the output. Negative half cycle (NHC): S.sub.a2 remains on, s.sub.a1 and S.sub.b2 remain off; S.sub.b1 is controlled on and off to produce a half sine wave at the output, which is 180 out of phase with PHC and has the opposite polarity of PHC.

(60) During each half cycle, PHC for example, the H-bridge of the second stage 10 operates in two modes: Mode 1: S.sub.a1 and S.sub.b2 are on. The DC source delivers the energy into output inductor L.sub.f and the AC load 6. Mode 2: Only S.sub.a1 is on. The output inductor L.sub.f discharges energy into the AC load 6 through S.sub.a1 and the paralleling diode of S.sub.b1.

(61) In case of a grid-connected inverter, the AC load 6 becomes an AC grid, and v.sub.o=V.sub.grid and i.sub.o=I.sub.grid, the demanded energy during the n.sup.th switching period is calculated approximately from:
E.sub.dm(n)=V.sub.grid(n).Math.I.sub.ref(n).Math.T.sub.s(19)
in which V.sub.grid(n) and I.sub.ref(n) are grid voltage and reference grid current, respectively, in the n.sup.th switching period, during which V.sub.grid(n) and I.sub.ref(n) are approximately constant for the fact that the switching frequency is much higher than the line frequency. T.sub.s is the switching period.

(62) If the initial current of the inductor is I.sub.n(t.sub.0) and the inductor current after charging is I.sub.n(t.sub.1) for the n.sup.th switching period, the average current flowing to the grid is

(63) $\frac{1}{2}\left(I_n\left(t_0\right)+I_n\left(t_1\right)\right).$
The energy charged during the n.sup.th switching period is calculated from:

(64) $\begin{array}{cc}{E}_{in}\left(n\right)=\frac{1}{2}{L}_f.Math.\left(I_n^2\left(t_1\right)-I_n^2\left(t_0\right)\right)+\frac{1}{2}{V}_{grid}\left(n\right)\left(I_n\left(t_0\right)+I_n\left(t_1\right)\right)D{T}_s& \left(20\right)\end{array}$
where D is the duty cycle. According to the energy balance, in each switching period the following equation must be satisfied:
E.sub.in(n)=E.sub.dm(n)(21)

(65) During PHC, S.sub.a1 remains on, S.sub.a2 and S.sub.b1 remain off; the only switch controlled according to PEM is S.sub.b2.Math.I.sub.n(t.sub.1) can be calculated by:

(66) $\begin{array}{cc}{I}_n\left(t_1\right)=I_n\left(t_0\right)+\frac{\left(v_{\mathrm{link}}-V_{grid}\left(n\right)\right).Math.D_p\left(n\right)}{L_f}& \left(22\right)\end{array}$

(67) The duty cycle for S.sub.b2 during PHC can be stated as:

(68) $\begin{array}{cc}{D}_p\left(n\right)=\frac{L_f}{T_s.Math.\left(v_{\mathrm{link}}-V_{grjd}\left(n\right)\right)}\left(\sqrt{I_n^2\left(t_0\right)+\frac{2E_{dm}\left(n\right).Math.\left(v_{\mathrm{link}}-V_{grid}\left(n\right)\right)}{v_{\mathrm{link}}.Math.L_f}}-I_n\left(t_0\right)\right)& \left(23\right)\end{array}$

(69) During NHC, S.sub.a2 remains on, S.sub.a1 and S.sub.b2 remain off; the only switch controlled according to PEM is S.sub.b1. I.sub.n(t.sub.1) can be calculated by:

(70) $\begin{array}{cc}{I}_n\left(t_1\right)=I_n\left(t_0\right)+\frac{\left(-v_{\mathrm{link}}-V_{grid}\right).Math.D_p\left(n\right)}{L_f}& \left(24\right)\end{array}$

(71) The duty cycle for S.sub.b1 during NHC can be stated as:

(72) $\begin{array}{cc}{D}_n\left(n\right)=\frac{L_f}{T_s.Math.\left(v_{\mathrm{link}}+V_{grid}\left(n\right)\right)}\left(\sqrt{I_n^2\left(t_0\right)+\frac{2E_{dm}\left(n\right).Math.\left(v_{\mathrm{link}}+V_{grid}\left(n\right)\right)}{{}_{\mathrm{link}}.Math.L_f}}+I_n\left(t_0\right)\right)& \left(25\right)\end{array}$

(73) The simulation result of PEM on the bridge inverter is shown in FIGS. 7a and 7b, where the AC load is composed of a grid in series with an inductor. The output current of the bridge inverter i.sub.Lf is discontinuous around zero-crossing of output voltage V.sub.grid (same as v.sub.o), and is continuous around the crest and trough of V.sub.grid. PEM achieves zero-current switching when i.sub.Lf is discontinuous.

(74) The parameters of the new single-phase inverter according to one embodiment have been designed in MATLAB/SIMULINK and PSIM.

(75) Simulation and Experimental Results

(76) To verify single-phase inverter topology and modulation methods according to some embodiments, a 750 W single-phase VSI with a buck-boost stage was designed in the MATLAB/SIMULINK environment. The key parameters are listed in Table 1. With input DC voltage as 225V, the simulation results, using the parameters in Table 1 are shown in FIGS. 4a-c and FIGS. 4d-f, where v.sub.o=V.sub.AC and i.sub.o=i.sub.AC.

(77) TABLE-US-00001 TABLE 1 PARAMETERS OF A SINGLE-PHASE VSI Input DC voltage V.sub.DC 225 V Output peak AC voltage V.sub.O 311 V Output peak AC current I.sub.O 5 A Output load rated power P.sub.O 750 W Filtering Inductance L.sub.f 1 mH Flyback Inductance L 300 H Filtering Capacitance C.sub.f 10 F Power decoupling capacitance C.sub.D 160 F AC frequency f.sub.AC 60 Hz Switching frequency f.sub.s 10 kHz

(78) In laboratory tests, a DSP TMS320F28335 microprocessor was programmed to provide control and protection functions for the inverter. The preliminary results are shown in FIG. 5a and FIG. 5b, containing waveforms of input DC current, DC-link voltage, output AC voltage and output AC current, and being preliminary results, the voltage and current values are lower than the parameters in Table 1. The DC-link voltage is always higher than the peak output AC voltage, ensuring the bridge inverter never reach the over-modulation region. The second-order ripple component has been mitigated in the input DC current in FIG. 5b, indicating the successful power decoupling.

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