DELAY-BASED SPREAD SPECTRUM CLOCK GENERATOR CIRCUIT

Abstract

A delay chain circuit with series coupled delay elements receives a reference clock signal and outputs phase-shifted clock signals. A multiplexer circuit receives the phase-shifted clock signals and selects among the phase-shifted clock signals for output as in response to a selection signal. The selection signal is generated by a control circuit from a periodic signal having a triangular wave profile. A sigma-delta modulator converts the periodic signal to a digital signal, and an integrator circuit integrates the digital signal to output the selection signal. The selected phase-shifted clock signal is applied as the reference signal to a phase locked loop which generates a spread spectrum clock signal.

Claims

1. A circuit, comprising: a delay chain circuit having an input configured to receive a reference clock signal, the delay chain circuit including a plurality of delay elements coupled in series, wherein the delay chain circuit outputs a plurality of phase-shifted clock signals; a first multiplexer circuit having inputs coupled to receive the plurality of phase-shifted clock signals and having a first selection input configured to receive a first selection signal which selects one of the plurality of phase-shifted clock signals for output; and a control circuit configured to generate values for the first selection signal from a waveform signal having a periodic triangular wave profile, wherein the control circuit includes: a sigma-delta modulator configured to convert the waveform signal to generate a modulated digital signal from which the values for the first selection signal are generated.

2. The circuit of claim 1, further comprising a phase generator circuit configured to process the modulated digital signal and output the values of the first selection signal.

3. The circuit of claim 2, wherein the phase generator circuit comprises a digital integrator circuit.

4. The circuit of claim 1, further comprising a phase lock loop (PLL) circuit configured to receive the selected phase-shifted clock signal as a reference for generating a spread spectrum clock signal.

5. The circuit of claim 4, wherein the sigma-delta modulator implements noise shaping to push quantization noise into a higher frequency domain and the PLL circuit has a low-pass response for filtering out the quantization noise.

6. The circuit of claim 1, further comprising: a compensation circuit configured to determine a number of delay elements within the delay chain circuit which change state in response to one cycle of the reference clock signal; and wherein the control circuit adjusts a modulation depth of the waveform signal having the triangular wave profile in response to the determined number of delay elements.

7. The circuit of claim 1, further comprising a compensation circuit configured to determine a number of delay elements within the delay chain circuit which change state in response to one cycle of the reference clock signal; and wherein the control circuit adjusts a number of quantization levels for the sigma-delta modulator in response to the determined number of delay elements.

8. The circuit of claim 1, wherein the control circuit further includes a digital waveform generator configured to generate the waveform signal having the triangular wave profile in response to the reference clock signal.

9. The circuit of claim 8, wherein the triangular wave profile is defined by a modulation frequency and a modulation depth.

10. The circuit of claim 9, wherein the modulation depth is scaled by a compensation value to account for process and voltage variation of the plurality of delay elements.

11. The circuit of claim 10, wherein the compensation value is generated dependent on a number of delay elements within the delay chain circuit which change state in response to one cycle of the reference clock signal.

12. The circuit of claim 1, further comprising a register circuit configured to latch the first selection signal in response to a control clock, wherein the control clock is a delayed version of the phase-shifted clock signal selected by the first selection signal and output by the first multiplexer circuit.

13. The circuit of claim 1, further comprising a register circuit configured to latch the first selection signal in response to a control clock, wherein the control clock is a further selected one of the plurality of phase-shifted clock signals.

14. The circuit of claim 13, further comprising a second multiplexer circuit having inputs coupled to receive the plurality of phase-shifted clock signals and having a second selection input configured to receive a second selection signal which selects said further selected one of the plurality of phase-shifted clock signals for output by the second multiplexer circuit.

15. The circuit of claim 14, wherein the second selection signal is a delayed version of the first selection signal generated by the control circuit.

16. A method, comprising: selecting one of a plurality of phase-shifted clock signals for output in response to a selection signal; generating values for the selection signal by performing sigma-delta modulation of a waveform signal having a periodic triangular wave profile; and processing the selecting one of the plurality of phase-shifted clock signals to output a spread spectrum clock signal.

17. The method of claim 16, wherein the sigma-delta modulation generates a modulated digital signal, further comprising: phase processing the modulated digital signal to generate the values of the selection signal.

18. The method of claim 17, wherein phase processing comprises digitally integrating the modulated digital signal.

19. The method of claim 16, wherein processing comprises using the selected one of the plurality of phase-shifted clock signals as a reference clock for a phase lock loop (PLL) circuit which generates the spread spectrum clock signal.

20. The method of claim 19, wherein sigma-delta modulation implements noise shaping to push quantization noise into a higher frequency domain and wherein the PLL circuit has a low-pass response for filtering out the quantization noise.

21. The method of claim 16, further comprising: determining a number of delay elements within a delay chain circuit generating the plurality of phase-shifted clock signals from a reference clock signal which change state in response to one cycle of the reference clock signal; and adjusting a modulation depth of the waveform signal having the triangular wave profile in response to the determined number of delay elements.

22. The method of claim 16, further comprising determining a number of delay elements within a delay chain circuit generating the plurality of phase-shifted clock signals from a reference clock signal which change state in response to one cycle of the reference clock signal, and adjusting a number of quantization levels for the sigma-delta modulation in response to the determined number of delay elements.

23. The method of claim 16, further comprising scaling a modulation depth of the waveform signal by a compensation value to account for process and voltage variation of delay elements within a delay chain circuit generating the plurality of phase-shifted clock signals.

24. The method of claim 16, further comprising adjusting a number of quantization levels for the sigma-delta modulation to account for process and voltage variation of delay elements within a delay chain circuit generating the plurality of phase-shifted clock signals.

25. The method of claim 16, further comprising latching the value of the selection signal in response to a control clock, wherein the control clock is a delayed version of the selected one of the phase-shifted clock signals.

26. The method of claim 16, further comprising latching the value of the selection signal in response to a control clock, wherein the control clock is a further selected one of the plurality of phase-shifted clock signals.

27. The method of claim 26, further comprising selecting the further selected one of the plurality of phase-shifted clock signals in response to a delayed version of the selection signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIG. 1-3 show block diagrams for embodiments of a spread spectrum clock generator circuit.

[0008] FIGS. 4-5 show block diagrams for embodiments of a clocking control circuit.

[0009] FIG. 6 is a block diagram for a calibration circuit.

[0010] FIGS. 7A-7D are plots illustrating operation of the FIG. 3 circuit.

[0011] FIG. 8 shows operational timing waveforms.

DETAILED DESCRIPTION

[0012] Reference is now made to FIG. 1 which shows a block diagram for an embodiment of a spread spectrum clock generator circuit 10. The circuit 10 includes a phase lock loop (PLL) circuit 12 configured to generate a clock signal 14 oscillating at a frequency fclk. The clock signal 14 is input to a delay chain circuit 16 that includes a plurality of delay elements 18 (for example, signal buffer circuits) of identical construction and designed to provide identical delays. The delay elements 18 are coupled in series with each other, with the delay chain circuit 16 including a plurality of taps 20, wherein each tap 20 outputs a phase shifted clock signal 22 oscillating at the frequency fclk but having a different phase shift. The plurality of phase shifted clock signals 22 are applied to the inputs of a multiplexer circuit 26. The selection input of the multiplexer circuit 26 receives a digital multiplexer control signal 28 and the multiplexer circuit 26 operates in response to the values of the digital multiplexer control signal 28 to select one of the phase shifted clock signals 22 for output as a spread spectrum clock signal (SSclk) 30.

[0013] The multiplexer control signal 28 is generated by a control circuit 40. The control circuit 40 includes a digital waveform generator circuit 42 that outputs a digital signal 44 whose values define a periodic signal having a triangular wave profile defined by a modulation depth parameter (mod_depth) and a modulation frequency parameter (mod_freq) and which is generated in response to a reference clock signal 46 output by a reference clock generator circuit 48. The frequency fref of the reference clock signal 46 is substantially less than the frequency fclk of the clock signal 14. A phase generator 50 receives the triangular wave profile digital signal 44 and generates the digital multiplexer control signal 28. The phase generator 50 may, for example, comprise a digital integrator circuit (such as an accumulator with a transfer function

[00001]$\frac{1}{\left(1-z^{-1}\right)}).$

[0014] Reference is now made to FIG. 2 which shows a block diagram for an embodiment of a spread spectrum clock generator circuit 110. The circuit 110 includes a reference clock generator 148 that generates a reference clock signal 146 oscillating at a frequency fref. The reference clock signal 146 is input to a delay chain circuit 116 that includes a plurality of delay elements 118 (for example, signal buffer circuits) of identical construction and designed to provide identical delays. The delay elements 118 are coupled in series with each other, with the delay chain circuit 116 including a plurality of taps 120, wherein each tap 120 outputs a phase shifted clock signal 122 oscillating at the frequency fref but having a different phase shift. The plurality of phase shifted clock signals 122 are applied to the inputs of a multiplexer circuit 126. The selection input of the multiplexer circuit 126 receives a digital multiplexer control signal 128 and the multiplexer circuit 126 operates in response to the values of the digital multiplexer control signal 128 to select one of the phase shifted clock signals 122 for output as an input spread spectrum clock signal 130. The input spread spectrum clock signal 130 is applied as the reference clock signal to a phase lock loop (PLL) circuit 112 that generates an output spread spectrum clock signal 132 oscillating at a frequency fclk (where the frequency fclk is substantially greater than the frequency fref).

[0015] The digital multiplexer control signal 128 is generated by a control circuit 140. The control circuit 140 includes a digital waveform generator circuit 142 that outputs a digital signal 44 whose values define a periodic signal having a triangular wave profile defined by a modulation depth parameter (mod_depth) and a modulation frequency parameter (mod_freq) and which is generated in response to the reference clock signal 146 output by the reference clock generator circuit 148. A phase generator 150 receives the values of the triangular wave profile digital signal 144 and generates the digital multiplexer control signal 128. The phase generator 150 may, for example, comprise a digital integrator circuit (such as an accumulator with a transfer function of

[00002]$\frac{1}{\left(1-z^{-1}\right)}).$

[0016] The circuit 110 possesses a number of advantages over the circuit 10 in terms of a lower buffer delay and reduced power consumption. However, both circuit 10 and circuit 110 suffer from a common drawback in terms of a requirement for an excessively high number of delay elements 18, 118 within the delay chain circuit 16, 116. Consider, for example, a reference frequency fref of 10e{umlaut over ()}6, a modulation frequency of 50e{circumflex over ()}3 and a modulation depth of 1% peak; so there is a period of 100 ns with a modulation depth of 1 ns Peak. The reference frequency divided by the modulation frequency is 200. The phase movement in the spread spectrum clock generator is given by: (0.5)*(1 ns)*100=50. The delay value (in each buffer) for a 5% error tolerance in profile is equal to 5/100*1 ns=50 ps. With this, the number of delay elements 18, 118 required in the delay chain circuit 16, 116 for the phase movement is 50 ns/50 ps=1000.

[0017] Reference is now made to FIG. 3 which shows a block diagram for an embodiment of a spread spectrum clock generator circuit 210. The circuit 210 includes a reference clock generator 248 that generates a reference clock signal 246 oscillating at a frequency fref. The reference clock signal 246 is input to a delay chain circuit 216 that includes a plurality of delay elements 218 (for example, signal buffer circuits) of identical construction and designed to provide identical delays. The delay elements 218 are coupled in series with each other, with the delay chain circuit 216 including a plurality of taps 220, wherein each tap 220 outputs a phase shifted clock signal 222 oscillating at the frequency fref but having a different phase shift. The plurality of phase shifted clock signals 222 are applied to the inputs of a multiplexer circuit 226. The selection input of the multiplexer circuit 226 receives a digital multiplexer control signal 228 and the multiplexer circuit 226 operates in response to values of the digital multiplexer control signal 228 to select one of the phase shifted clock signals 222 for output as an input spread spectrum clock signal 230. The input spread spectrum clock signal 230 is applied as the reference clock signal to a phase lock loop (PLL) circuit 212 that generates an output spread spectrum clock signal 232 oscillating at a frequency fclk (where the frequency fclk is substantially greater than the frequency fref).

[0018] The multiplexer control signal 228 is generated by a control circuit 240. The control circuit 240 includes a digital waveform generator circuit 242 that outputs a digital signal 244 whose values define a periodic signal having a triangular wave profile defined by a modulation depth parameter (mod_depth) and a modulation frequency parameter (mod_freq) and which is generated in response to the reference clock signal 246 output by the reference clock generator circuit 248. A digital sigma-delta modulator 260 receives the digital signal 144 and generates a modulated digital signal 262. In an embodiment, the sigma-delta modulator 260 is a third-order single, MASH 1-1-1 type circuit, but it will be understood that the sigma-delta modulator 260 may be of any desired order and configuration. A phase generator 250 receives the modulated digital signal 262 and generates the digital multiplexer control signal 228. The phase generator 250 may, for example, comprise a digital integrator circuit (such as an accumulator with a transfer function

[00003]$\frac{1}{\left(1-z^{-1}\right)}).$

[0019] The circuit 210 of FIG. 3 takes advantage of the fact that the PLL 212 has a low-pass transfer function. The sigma-delta modulator 260 performs noise shaping by pushing the quantization noise introduced by the modulation operation into the higher frequency domain. This noise is then filtered out by the low-pass response of the PLL. This is beneficial because an error tolerance similar to the FIG. 2 circuit can be achieved in circuit 210 with fewer delay elements. Consider, for example, a reference frequency fref of 10e{circumflex over ()}6, a modulation frequency of 50e{circumflex over ()}3, a modulation depth of 1% peak and sigma-delta modulation step of 5% (5 ns); so there is a period of 100 ns with a modulation depth of 1 ns Peak for the triangle waveform. The reference frequency divided by the modulation frequency is 200. The phase movement in the spread spectrum clock generator is given by: (0.5)*(1 ns)*100=50. So, the delay elements for phase movement with sigma-delta modulation are 50 ns/5 ns=10. The delay value (in each buffer) for a 5% error tolerance in profile is equal to 5/100*1 ns=50 ps. With this, the number of delay elements 18, 118 required in the delay chain circuit 16, 116 for the phase movement in the FIG. 3 implementation 5 ns/50 ps=100. For a similar error tolerance, this is an order of magnitude reduction in the number of delay elements used by the FIG. 3 circuit 210 in comparison to the FIG. 2 circuit 110.

[0020] Reference is now made to FIG. 4 which shows a block diagram of a clocking control circuit 300. The multiplexer control signal 228 output from the control circuit 240 is applied to the input of a multi-bit register 302 (formed, for example, by D-type flip-flops). The multi-bit register 302 is clocked by a clock signal 304 and responds to the leading edge of the clock signal 304 by latching the data values of the multiplexer control signal 228 output from the control circuit 240 for output as signal 228 to the selection input of the multiplexer circuit 226. The multi-bit register 302 controls the timing for making changes to the value of the applied multiplexer control signal 228 so that such changes occur only when the logical value of the current phase and the next phase which is going to be selected are static. This is shown by the operating waveforms in FIG. 8 where it will be noted that: at each positive edge of clock signal 230 the control circuit 240 gives the next value for the multiplexer control signal 228; but if the changed value is immediately applied to the multiplexer there is a risk that a glitch will be produced on the output clock 230; so, to avoid this concern, a delay is introduced, which is greater than the maximum phase change that can happen, and the glitch is avoided. This control operation is best achieved for the clock at time instants defined by Tref/4 and 3*Tref/4, where Tref is the clock period of the reference clock signal 246. The input spread spectrum clock signal 230 is used to clock the logic circuitry of the control circuit 240 and is further applied to the input of a delay circuit 306 which delays the input spread spectrum clock signal 230 by Tref/4 and outputs the clock signal 304.

[0021] Reference is now made to FIG. 5 which shows a block diagram of a clocking control circuit 400. The multiplexer control signal 228 output from the control circuit 240 is applied to the input of a multi-bit register 402 (formed, for example, by D-type flip-flops). The multi-bit register 402 is clocked by a clock signal 404 and responds to the leading edge of the clock signal 404 by latching the data values of the multiplexer control signal 228 output from the control circuit 240 for output as signal 228 to the selection input of the multiplexer circuit 226. The multi-bit register 402 controls the timing for change in the applied multiplexer control signal 228 to occur only when the logical value of the current phase and the next phase which is going to be selected are static (see, FIG. 8). This is best achieved for the clock at time instants defined by Tref/4 and 3*Tref/4, where Tref is the clock period of the reference clock signal 246. The input spread spectrum clock signal 230 is used to clock the logic circuitry of the control circuit 240. The plurality of phase shifted clock signals 222 are applied to the inputs of a multiplexer circuit 408. The selection input of the multiplexer circuit 408 receives a delayed version (signal 228) of the multiplexer control signal 228 generated by a delay circuit 406 (which delays the multiplexer control signal 228 by Tref/4 (for example)), and the multiplexer circuit 408 operates in response to that signal 228 to select one of the phase shifted clock signals 222 for output as the clock signal 404.

[0022] With reference once again to FIG. 3, it will be noted that the length of the delay provided by each delay element 218 (for example, signal buffer circuit) in the delay chain circuit 216 is process, voltage and temperature (PVT) dependent. Because of this, the modulation depth of circuit 210 will also vary with change in process, voltage and temperature. An initial calibration can be performed to address the process and voltage variation of the buffer circuits. This calibration utilizes the circuit 500 shown in FIG. 6. Circuit 500 includes a delay element 502 configured to apply a small delay d to the reference clock signal 246 and generate a delayed clock signal 504 which is applied to the string of delay elements 218 in the delay chain circuit 216. A D-type flip-flop 506 is provided for each delay element 218, with the output of the delay element 218 provided to the D input of the corresponding flip-flop 506. The clock input of each flip-flop 506 receives the reference clock signal 246. The Q output of each flip-flop 506 is connected to a corresponding input of a binary encoder circuit 510. The circuit 500 operates as a timed counter circuit with the binary encoder circuit 510 functioning to count the number of delay elements 218 which change logic state within one cycle of the reference clock signal 246 and output an encoded digital count value (Count) 512 indicative of the counted number.

[0023] The encoded digital count value 512 is then applied as a further input to the signal generator circuit 242 that generates the periodic signal 244 having the triangular wave profile (and optionally or alternatively to the sigma-delta modulator 260 that generates the digital output signal 262). The value of the Count 512 is used in the signal generator circuit 242 to adjust the modulation depth (mod_depth) value by way of a simple multiplication (scaling) operation. In the alternative implementation, the value of the Count 512 is instead used in the sigma-delta modulator 260 to adjust the quantization levels. It is somewhat easier to perform the adjustment of modulation depth, and so this solution is preferable. The adjustment that is made will account for sensed differences in the Count 512 value due to process and voltage variation of the buffer circuits. For example, for Fref having a 100 ns period and where the delay provided by each delay element is 5 ns, then Count 512=20 (ideal). The quantizer level for the SDM 260 is considered to be 5 ns (always). Now, due to process variation, the delay element becomes 10 ns, Count=10 (actual). In that case the scaling factor will become actual/deal=10/20=0.5. A multiplication block (not explicitly shown) positioned between generator 242 and SDM 260 can be used.

[0024] The foregoing calibration operation does not address temperature variation. However, temperature variation is minute in circuit 210 and may in many implementations be ignored without negative impact. If temperature compensation is needed, a delay locked loop (DLL) circuit may be provided in order to keep the buffer delays locked with each other.

[0025] Reference is now made to FIGS. 7A-7D which show plots illustrating operation of the FIG. 3 circuit 210. FIG. 7A shows the unfiltered output clock frequency signal 230 scaled by N (which is the divisor value in the PLL 212) where the y-axis shows frequency in Hz and the x-axis shows the sample number in terms of clock cycle. FIG. 7B shows the output clock frequency of the PLL with signal 232 where the y-axis shows frequency in Hz and the x-axis shows the sample number in terms of clock cycle. FIG. 7C shows the multiplexer control for the delay chain signal 228 where the y-axis shows the value of the multiplexer selection and the x-axis shows the sample number in time (every REF cycle). FIG. 7D shows a plot of the phase noise power spectral density where the y-axis shows dBc/Hz and the x-axis shows frequency in Hz. The density plot for No mod clock shows the density for the case where no spread spectrum clock generation (SSCG) is performed. The density plot for Ideal SSCG shows the density for the case where a pure triangle waveform is used for the spread spectrum clock generation. The density plot for Modulated SSCG shows the density for the case where sigma-delta modulation (SDM) of the triangle waveform is used for the spread spectrum clock generation.

[0026] Although the preceding description has been described herein with reference to particular circuits and embodiments, it is not intended to be limited to the particulars disclosed herein; rather, it extends to all functionally equivalent structures, methods, and uses, such as are within the scope of the appended claims.