Circuit for breaking alternating current

Abstract

The present invention relates to a circuit and an arrangement for breaking alternating current, the circuit comprising: an input arranged to receive an alternating current (AC); an output arranged to provide the alternating current (AC) to at least one electrical load; at least one controllable switch coupled between the input and the output; an impedance network (Z) coupled between the input and the output; and a transistor network (TN) comprising at least one transistor (T.sub.TN1; T.sub.TN2), the transistor network (TN) being arranged to control the at least one controllable switch, so as to control the breaking of the alternating current (AC) provided to the at least one electrical load, based on a value of at least one voltage (V1; V2) of at least one node of the impedance network (Z).

Claims

1. A circuit for breaking alternating current, the circuit comprising: an input arranged to receive an alternating current; an output arranged to provide the alternating current to at least one electrical load; a first controllable switch and a second controllable switch coupled in series with each other and being arranged between the input and the output; an impedance network coupled between the first controllable switch and the second controllable switch, wherein the impedance network comprises a limiting/delay circuit coupled between the first controllable switch and the second controllable switch; and a transistor network comprising at least one transistor, the transistor network being arranged to control the first controllable switch and the second controllable switch, so as to control the breaking of the alternating current provided to the at least one electrical load, based on a value of at least one voltage of at least one node of the impedance network.

2. The circuit according to claim 1, wherein the first controllable switch and the second controllable switch are coupled in opposite directions between the input and the output.

3. The circuit according to claim 1, wherein the first controllable switch and the second controllable switch are Field Effect Transistors (FETs).

4. The circuit according to claim 1, wherein the transistor network is further arranged to control the first controllable switch and the second controllable switch based on at least one of a first voltage of a first node of the impedance network and a second voltage of a second node of the impedance network.

5. The circuit according to claim 4, wherein the second voltage is a difference voltage between the second node and a reference ground, the reference ground being different from at least one reference voltage for the at least one electrical load.

6. The circuit according to claim 4, wherein the first voltage is a difference voltage between the first node and a reference ground, the reference ground being different from a reference voltage for the at least one electrical load.

7. The circuit according to claim 1, further comprising: a combining circuit; and a controller coupled to a reference ground common to the controller and the first controllable switch and the second controllable switch, and arranged to measure the at least one voltage of the at least one node of the impedance network; wherein the combining circuit is arranged to provide a combined control of the first controllable switch and the second controllable switch based on the value of the at least one voltage by use of the transistor network and of the controller.

8. The circuit according to claim 7, wherein the controller is further arranged to control the first controllable switch and the second controllable switch such that breaking of the alternating current is triggered for a lower power consumption of the at least one electrical load than a power consumption that would trigger breaking of the alternating current when the first controllable switch and the second controllable switch are controlled by the transistor network alone.

9. The circuit according to claim 7, wherein the controller is further arranged to: monitor a power consumption pattern of the at least one electrical load; and control the first controllable switch and the second controllable switch based on the monitored power consumption pattern of the at least one electrical load.

10. The circuit according to claim 9, wherein the controller is further arranged to control the first controllable switch and the second controllable switch such that breaking of the alternating current is effected if the power consumption pattern is irrational.

11. The circuit according to claim 9, wherein the controller is further arranged to determine the type of the at least one electrical load based on the monitored power consumption pattern.

12. The circuit according to claim 11, wherein the controller is further arranged to control the first controllable switch and the second controllable switch based on the determined type.

13. The circuit according to claim 7, wherein the controller is further arranged to: receive one or more of at least one information element and at least one instruction associated with the at least one electrical load; and control the first controllable switch and the second controllable switch based on one or more of the at least one information element and the at least one instruction.

14. The circuit according to claim 13, wherein the controller comprises any of wireless receiving means and wired receiving means arranged to receive communication signals comprising an indication of at least any of the at least one information element and the at least one instruction element.

15. The circuit according to claim 1, wherein the transistor network is an autonomous network arranged to control the first controllable switch and the second controllable switch based only on the at least one voltage.

16. The circuit according to claim 1, wherein the transistor network is arranged to control the first controllable switch and the second controllable switch based on at least one voltage comparison.

17. The circuit according to claim 1, wherein one or more of the at least one transistor comprised in the transistor network are supplied with at least one bias voltage.

18. The circuit according to claim 1, wherein the transistor network comprises at least one resistor coupled in series to a controlling input of the at least one transistor, the at least one resistor having a resistance such that the at least one transistor is protected, and a time period during which the at least one transistor operates in its linear region is reduced.

19. An alternating current breaking arrangement comprising: the alternating current breaking circuit according to claim 1, and a power supply circuit arranged to provide electrical power for driving the alternating current breaking circuit, the power supply circuit comprising: a first parasite arrangement arranged to extract a first parasite voltage from the alternating current; a second parasite arrangement arranged to extract a second parasite voltage from the alternating current; and a voltage combiner arranged to combine the first parasite voltage and the second parasite voltage.

20. The alternating current breaking arrangement according to claim 19, wherein the first parasite arrangement comprises a transformer arranged to generate the first parasite voltage from the alternating current.

21. The alternating current breaking arrangement according to claim 19, wherein the second parasite arrangement is arranged to extract a second parasite voltage by one or more in the group of: extracting a portion of an amplitude of a voltage corresponding to the alternating current; and extracting a time duration portion of a cycle of a voltage corresponding to the alternating current.

22. The alternating current breaking arrangement according to claim 19, wherein the voltage combiner comprises two rectifying diodes.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The appended drawings are intended to clarify and explain different embodiments of the present invention, in which:

(2) FIG. 1 shows a circuit according to an embodiment of the invention;

(3) FIG. 2 shows a circuit according to an embodiment of the invention;

(4) FIGS. 3a-b shows a circuit according to an embodiment of the invention;

(5) FIG. 4 shows a circuit according to an embodiment of the invention;

(6) FIG. 5 shows a circuit according to an embodiment of the invention;

(7) FIG. 6 shows a circuit according to an embodiment of the invention;

(8) FIG. 7 shows a circuit according to an embodiment of the invention;

(9) FIGS. 8a-b show a circuit according to an embodiment of the invention;

(10) FIGS. 9a-b show a circuit according to an embodiment of the invention;

(11) FIG. 10 shows a circuit according to an embodiment of the invention;

(12) FIG. 11 shows a circuit according to an embodiment of the invention;

(13) FIGS. 12a-b shows a circuit according to an embodiment of the invention;

(14) FIG. 13. shows an arrangement according to an embodiment of the invention; and

(15) FIGS. 14a-c show some energy harvesting methods.

DETAILED DESCRIPTION

(16) FIG. 1 schematically illustrates a circuit 100 for breaking alternating current according to an embodiment of the invention. The circuit 100 may be coupled to one or more electrical loads 200a, 200b, . . . 200N (having index n=a, b, . . . , N). An alternating current (AC) is fed to the input 102 of the circuit 100 and forwarded to the loads 200a, 200b, . . . 200N via the output 104 of the circuit 100. The current is, according to an embodiment, a so-called mains alternating current. The loads 200a, 200b, . . . 200N may therefore comprise household appliances and/or electrical heaters and/or other household electronics.

(17) FIG. 2 schematically shows an embodiment of a circuit 100 for breaking alternating current according to the invention. The circuit 100 comprises an input 102 arranged to receive alternating current (AC), and an output 104 arranged to provide the current to at least one electrical load 200n, as mentioned above. The circuit 100 further comprises at least one controllable switch 106; 108 coupled between the input 102 and the output 104. The at least one controllable switch 106; 108 may e.g. comprise one or more relay, thyristor, triac, gate turn off thyristor, transistor and/or any other type of silicon controlled rectifier or switch.

(18) The circuit 100 further comprises an impedance network (Z) 140, which is coupled between the input 102 and the output 104 in series with the at least one controllable switch 106; 108. In the embodiment shown in FIG. 2, the impedance network (Z) 140 is coupled between the input 102 and the at least one controllable switch 106; 108. However, the impedance network (Z) 140 may also be coupled between the at least one controllable switch 106; 108 and the output 104.

(19) The circuit 100 also comprises a transistor network (TN) 110, which comprises at least one transistor T.sub.TN1; T.sub.TN2 described more in detail below. The transistor network (TN) 110 is arranged to control the at least one controllable switch 106; 108. Hereby, the breaking of the alternating current (AC) provided to the at least one electrical load 200n is controlled. At least one voltage V1; V2 of at least one node of the impedance network (Z) 140 is supplied to, and controls, the at least one transistor T.sub.TN1; T.sub.TN2, wherefore the control of the at least one controllable switch 106; 108, and thus also the control of the breaking of the alternating current (AC), is based on the value of the least one voltage V1; V2.

(20) The control of the at least one controllable switch 106; 108 may be performed using control means 130 coupled between the transistor network (TN) 110 and the least one controllable switch 106; 108 as shown in FIG. 2. The control means 130 may carry control signals, e.g. one or more different control voltages or currents, which may have different levels suitable for opening and closing the at least one controllable switch 106; 108. If an overcurrent is detected, the least one controllable switch 106; 108 is switched open, whereby breaking of the applied current is effected. Since the control of the at least one controllable switch 106; 108 is provided by the at least one transistor T.sub.TN1; T.sub.TN2, the switching, and thus also the breaking of the alternating current, may be effected very quickly. Thereby, the risk for damages of the loads 200n and/or the circuit 100 itself due to the current triggering the switching is very low.

(21) FIG. 3a shows an embodiment of a circuit 100 for breaking alternating current according to the invention. The circuit 100 in this embodiment comprises two controllable switches, i.e. a first controllable switch 106 and a second controllable switch 108, that are coupled in series with each other and being arranged between the input 102 and the output 104 as shown in FIG. 3a. The first controllable switch 106 and the second controllable switch 108 may be coupled in opposite directions between the input 102 and the output 104. As mentioned above, the transistor network (TN) 110 is arranged to control the two controllable switches 106; 108 based on the at least one voltage V1; V2 of at least one node of the impedance network (Z) 140. When the circuit 100 comprises two controllable switches 106; 108, the impedance network (Z) 140 may be arranged between the first controllable switch 106 and the second controllable switch 108, as illustrated in FIG. 3a.

(22) The at least one controllable switch 106, 108 mentioned in this document may, according to an embodiment, include at least one Field Effect Transistor (FET). A FET blocks the current in one direction, and two FETs may hence, according to an embodiment, be coupled in opposite directions relative to the direction of the current. The FETs have a fast switching time (the time period for opening or closing the switch), which means that the current through the FETs may be broken very quickly when an overcurrent is detected. Hereby, damages to circuits and loads coupled to the output 104 may be limited and/or eliminated. Preferably, the two FETs are according to an embodiment controlled with the same control means using a common gate voltage, thereby simplifying the architecture. The example embodiment illustrated in FIG. 3a shows that the transistor network (TN) 110 controls the two controllable switches 106, 108 via separate control means 130. However, the controller (C) 110 may also control the two switches 106, 108 via common control means 130 as described above.

(23) FIG. 3b shows some parts of the circuit 100 according to an embodiment more in detail. According to an embodiment mentioned above, the circuit 100 comprises two controllable switches formed by a first FET 106 and a second FET 108 coupled in series in opposite directions relative to the current between the input 102 and the output 104. The two FETs are controlled by the same control means 130 using the same control voltage as gate voltage, as mentioned above. FIG. 3b further shows the impedance network (Z) 140 coupled between the FETs more in detail, and how the first voltage V1 and the second voltage V2 are provided.

(24) The impedance network (Z) 140 may generally be configured such that at least one voltage V1; V2 can be measured/detected/provided at the impedance network (Z) 140. One solution is to have a measuring resistor over which a voltage is measured/detected/provided. A reference value for the resistance of the measuring resistor may e.g. be approximately 0.01 Ohm or lower for AC mains, e.g. 110 or 230 Volts. The voltage may then, as is described in detail below, be compared with a threshold voltage in a comparator circuit, and if the voltage exceeds the threshold voltage, the at least one controllable switch 106, 108 are controlled to take an open position so as to prevent that an overcurrent damages circuits/components and/or the at least one electrical load coupled to the output 104. Hence, the at least one voltage is used for detecting overcurrent.

(25) The impedance network (Z) 140 includes, according to an embodiment, a first resistor R1 coupled in parallel with an inductor L1. The first resistor R1 and the inductor L1 may be coupled together in series with a second resistor R2. According to some embodiments, the second resistor R2 may be omitted. The first voltage V1 is available/measured/detected (as a potential difference) between a potential of a first node and the reference ground REF.sub.GND 112. The first node is located between the first controllable switch 106 and the parallel coupling of the first resistor R1 and the inductor L1. The reference ground REF.sub.GND 112 is here different from a reference voltage for the at least one electrical load 200n, which may be a zero/neutral voltage, an earthed/grounded neutral voltage, a protective earth/ground voltage, another phase and/or another suitable reference potential of a network to which the at least one load 200n is connected. The first voltage V1 is related to the change of the load coupled to the output 104, and thus indicates a short circuit.

(26) The second voltage V2 is available/measured (as a potential difference) between a second node and the reference ground REF.sub.GND 112. The reference 112 is different from the reference voltage for the at least one electrical load 200n, as mentioned above. The second node is located between the second resistor R2 and the parallel coupling of the first resistor R1 and the inductor L1. Hence, the second voltage V2 is obtained over the second resistor R2, and is directly proportional to the current flowing through the second resistor R2, and thus also through the alternating current breaking circuit 100, and indicates overcurrent. The second voltage V2 is therefore also suitable for monitoring the power consumption of the at least one load 200n and may be used for determining the power consumption pattern. Further, at low frequencies, the alternating current AC passes through the inductor L1, i.e. the inductor L1 is essentially a shortcut, and the second resistor R2, which in that case gives the relation that the first and second voltages are equal; V1=V2. If the one or more loads coupled to the output 104 are changing quickly (which can be seen as a high frequency signal), then inductor L1 has a high impedance and acts as a current brake or stopper. The voltage over the inductor L1 is thus related to the frequency, and may therefore be very high, since the impedance increases with increasing frequency. In this case, the first resistor R1 acts as a current shunt preventing that the voltage gets too high. According to an embodiment, at least one protection circuit, including e.g. at least one diode having a Zener functionality, is coupled in parallel with the inductor L1 and the first resistor R1.

(27) According to an embodiment, the impedance network (Z) 140 comprises a limiting/delay circuit coupled between the first controllable switch 106 and the second controllable switch 108. The limiting/delay circuit is arranged to limit/delay the speed of changes of the current, e.g. an overcurrent. The limitation/delay is preferably of an order such that the transistor network 110 via the at least one controllable switch 106; 108 has time to detect an overcurrent and break the current before the overcurrent reaches the circuits/components and/or the at least one electrical load connected to the output 104. The overcurrent, which is also known as an overload, is often due to short circuits, overloading of electrical loads, mismatch of electrical loads, and electrical device failures. There are a number of different solutions for providing a limiting/delay circuit. In one solution, the limiting/delay circuit includes an inductor shown as L1 in FIG. 3b.

(28) According to an embodiment illustrated in FIG. 3a, the circuit 100 comprises at least one driver circuit 114 coupled between the transistor network (TN) 110 and the controllable switches 106, 108. The at least one driver circuit 114 is arranged to amplify control signals used by the transistor network (TN) 110 for controlling the switches 106, 108 via the control means 130. This may be needed e.g. when the control voltages and/or currents transmitted to the controllable switch has to be boosted/amplified. For example, the driver circuit 114 can be arranged to be fed with 10-15 Volts and to deliver this voltage to the gate side of the FET. A driver circuit 114 may, according to some embodiments, be implemented between the transistor network (TN) 110 and/or the controller (C) 120 described below, and the at least one controllable switch 106; 108 in any one of the in this documents described embodiments of the circuit 100.

(29) FIGS. 4 and 5 schematically illustrate the transistor network 110 more in detail for some embodiments.

(30) As mentioned above, the circuit 100 for breaking alternating current comprises an input 102, an output 104, and at least one controllable switch 106; 108 and an impedance network (Z) 140 coupled between the input 102 and the output 104. In the embodiment shown in FIG. 4, the impedance network (Z) 140 is coupled between the input 102 and the at least one controllable switch 106; 108. However, the impedance network (Z) 140 may also be coupled between the at least one controllable switch 106; 108 and the output 104.

(31) In the embodiment shown in FIG. 5, the circuit 100 comprises two controllable switches 106; 108 between the input 102 and the output 104, and the impedance network (Z) 140 is coupled between the first controllable switch 106 and the second controllable switch 108.

(32) The transistor networks (TN) 110 of the embodiments shown in FIGS. 4 and 5 comprise two transistors T.sub.TN1; T.sub.TN2 arranged for controlling the at least one controllable switch 106; 108, such that breaking of the alternating current (AC) is controlled, based on the at least one voltage V1; V2 of the at least one node of the impedance network (Z) 140, as explained above.

(33) The transistor networks (TN) 110 described for the different embodiments of this document function as autonomous networks according to some embodiments. An autonomous network is arranged to independently control the at least one controllable switch 106; 108 based only on the at least one voltage V1; V2. The transistor network (TN) 110 does thus not need to be controlled itself, and does also not, according to some embodiments, need to be externally supplied with power/voltage to perform the control of the at least one controllable switch 106; 108.

(34) The transistor networks (TN) 110 described in this document may also, according to some embodiments, be arranged to function as voltage comparator circuits, i.e. circuits that control the at least one controllable switch 106; 108 based on at least one voltage comparison.

(35) The transistor networks (TN) 110 of the herein described embodiments may comprise at least one resistor R.sub.TN1; R.sub.TN2 coupled in series with a controlling input of the at least one transistor T.sub.TN1; T.sub.TN2. As shown in e.g. FIGS. 4 and 5, the transistor network (TN) 110 may comprise two resistors R.sub.TN1; R.sub.TN2, one resistor coupled in series with the controlling input of each one of the two transistors T.sub.TN1; T.sub.TN2.

(36) More in detail, a first resistor R.sub.TN1 may be coupled between a reference ground REF.sub.GND node located between the impedance network (Z) 140 and the at least one controllable switch 106; 108, and the controlling input of the first transistor T.sub.TN1, as illustrated in FIG. 4. For the embodiment shown in FIG. 5, having two controllable switches 106:108, the first resistor R.sub.TN1 may be coupled between a reference ground REF.sub.GND node located between the impedance network (Z) 140 and the second controllable switch 108, and the controlling input of the first transistor T.sub.TN1. Further, the emitter/source of the first transistor T.sub.TN1 is coupled to at least one node of the impedance network (Z) 140 having a potential corresponding to the at least one voltage V1; V2. The collector/drain of the first transistor T.sub.TN1 is coupled, possibly directly or indirectly via a driver and/or a logic circuit, to the at least one controllable switch 106; 108.

(37) A second resistor R.sub.TN2 may be coupled between a node of the impedance network (Z) 140, e.g. the first node providing the at least on voltage V1; V2, and the controlling input of the second transistor T.sub.TN2, as illustrated in FIGS. 4 and 5. Further, the emitter/source of the second transistor T.sub.TN2 is coupled to the reference ground REF.sub.GND node located between the impedance network (Z) 140 and the at least one controllable switch 106:108. For the embodiment shown in FIG. 5, having two controllable switches 106:108, the emitter/source of the second transistor T.sub.TN2 is coupled to a reference ground REF.sub.GND node located between the impedance network (Z) 140 and the second controllable switch 108. The collector/drain of the second transistor T.sub.TN2 is coupled, possibly directly or indirectly via a driver and/or a logic circuit, to the at least one controllable switch 106; 108.

(38) The herein described one or more transistors T.sub.TN1; T.sub.TN2 may be bipolar junction transistors (BJT), having a base pin as a controlling input, or may be field effect transistors (FET), having a gate pin as a controlling input. Further, bipolar junction transistors also comprise an emitter pin and a collector pin, while filed effect transistors also comprise a source pin and a drain pin.

(39) The at least one resistor R.sub.TN1; R.sub.TN2 may have a resistance having a value being high enough for the at least one transistor T.sub.TN1; T.sub.TN2 to be protected against overcurrents. The at least one resistor R.sub.TN1; R.sub.TN2 may also have a resistance having a value being low enough for reducing a time period during which the at least one transistor T.sub.TN1; T.sub.TN2 operates in its linear region/mode.

(40) FIGS. 6 and 7 schematically illustrate the transistor network 110 for some embodiments, wherein one or more of the at least one transistor T.sub.TN1; T.sub.TN2 comprised in the transistor network (TN) 110 are supplied with at least one bias voltage V.sub.bias1; V.sub.bias2. FIG. 6 corresponds to FIG. 4 complemented with supply of a first V.sub.bias1 and second V.sub.bias1 bias voltage to the first T.sub.TN1 and second T.sub.TN2 transistors, respectively. FIG. 7 corresponds to FIG. 5 complemented with supply of a first V.sub.bias1 and second V.sub.bias1 bias voltage to the first T.sub.TN1 and second T.sub.TN2 transistors, respectively. Therefore, essentially only the supplied bias voltage V.sub.bias1; V.sub.bias2 is described below for FIGS. 6 and 7, the rest of the circuitry is described above for FIGS. 4 and 5.

(41) As illustrated in FIGS. 6 and 7, a first bias voltage V.sub.bias1 is provided to the controlling input of the first transistor T.sub.TN1, by a first bias resistor R.sub.bias1 being coupled to a source of energy. Correspondingly, a second bias voltage V.sub.bias2 is provided to the controlling input of the second transistor T.sub.TN2, by a second bias resistor R.sub.bias2 being coupled to a source of energy. The source of energy may e.g. be a battery, or may be a power supply circuit 400 as the one described below.

(42) To supply bias voltages V.sub.bias1; V.sub.bias2 to the controlling input of one or more of the at least one transistor T.sub.TN1; T.sub.TN2 makes it possible for the at least one transistor T.sub.TN1; T.sub.TN2 to act on, i.e. be triggered by, lower voltages/currents than allowed by the constitution of the at least one transistor T.sub.TN1; T.sub.TN2 itself.

(43) FIGS. 8a-b and 9a-b show the embodiment shown in FIG. 7 in semi-block representations. In FIGS. 8a-b, the first transistor T.sub.TN1 and the first resistor R.sub.TN1 are arranged in a first transistor network block (TN block) 121. The second transistor T.sub.TN2 and the second resistor R.sub.TN2 are arranged in a second transistor network block (TN block) 122. In FIGS. 9a-b, the first transistor T.sub.TN1, the second transistor T.sub.TN2, the first resistor R.sub.TN1, and the second resistor R.sub.TN2 are arranged in a common transistor network block (TN block) 123. Reference is here made to the descriptions above for FIG. 7 regarding the couplings and functions of the circuit 100 of FIGS. 8a-b and 9a-b.

(44) FIG. 10 shows a circuit according to an embodiment, in which both the transistor network (TN) 110 and a controller (C) 120 are used for controlling the at least one controllable switch 106; 108. The circuit 100 here comprises a transistor network (TN) 110 according to any one of the herein described embodiments. The circuit also comprises a controller (C) 120 coupled to a reference ground 112 corresponding to the above mentioned reference ground REF.sub.GND and being common to the controller (C) 120 and the at least one controllable switch 106; 108. The controller (C) 120 is arranged to measure the at least one voltage V1; V2 of the at least one node of the impedance network (Z) 140. The circuit 100 further comprises a combining circuit 150 being arranged to provide a combined control of the at least one controllable switch 106; 108 based on the value of the at least one voltage V1; V2 by use of the transistor network (TN) 110 and of the controller (C) 120. Hereby, a combined control of the at least one controllable switch 106; 108 using both the transistor network (TN) 110 and the controller (C) 120 is provided. For further details of the circuit 100 illustrated in FIG. 10, apart from the controller (C) 120, reference is made to the above description e.g. of the circuit illustrated in FIG. 2.

(45) The controller (C) 120 may, according to an embodiment, be arranged to control, via the combining circuit 150, the at least one controllable switch 106; 108 such that breaking of the alternating current AC is triggered for a low power consumption for the at least one electrical load 200n, e.g. for a lower power consumption than a power consumption that would trigger breaking of the alternating current AC when the at least one controllable switch 106; 108 is controlled by the transistor network (TN) 110 alone. Thus, by the combined control of the at least one controllable switch 106; 108, using both the transistor network (TN) 110 and the controller (C) 120, breaking of the alternating current AC may be effected already at very low power consumptions.

(46) According to an embodiment, the controller (C) 120 is arranged to monitor the power consumption pattern of the at least one electrical load 200n and to control the at least one controllable switch 106; 108 based on the monitored power consumption pattern of the at least one electrical load 200n. The power consumption pattern can be monitored by using and analysing the measured/detected/provided at least one voltage V1; V2 described above. Thereby, the controller (C) 120 may adapt the current fed to the load depending on the type of the load, by for example shutting down the load for safety reasons or providing a higher or lower amount of current. Also, the controller (C) 120 may be arranged to control the at least one controllable switch 106; 108 such that breaking of the alternating current AC is effected if the power consumption pattern is irrational, i.e. if the power consumption pattern appears to be unexpected and/or disadvantageous, e.g. including transients, steps, or other sudden changes.

(47) Also, the controller (C) 120 may be further arranged to determine the type of the at least one load 200n based on the monitored power consumption pattern. Each type of load has its own power consumption pattern which can be identified. By using and analysing the measured/detected/provided at least one voltage V1; V2, as described above, the type of at least one load 200n may be determined. Hence, in this solution, the controller (C) 120 also has the capability to determine or identify the type of load, which means that the at least one controllable switch 106; 108 can be controlled based on the determined or identified type of load.

(48) According to an embodiment, at least one driver circuit 114 may be coupled between the combining circuit 150 and the controllable switches 106, 108 (not shown in FIG. 10). The driver circuit 114 is, as mentioned above, arranged to amplify control signals used for controlling the switches 106, 108 via the control means 130.

(49) According to an embodiment, the controller (C) 120 is arranged to receive at least one information element IE and/or at least one instruction I associated with the at least one electrical load 200n. Some parts of the circuit of the embodiment are shown in FIG. 11, in which the controller (C) 120 is further arranged to control, via the combiner 150, the at least one controllable switch 106; 108 based on any of the at least one information element IE and the at least one instruction I. Therefore, the controller (C) 120 comprises any of wireless receiving means 304a and wired receiving means 304b arranged to receive communication signals comprising an indication of at least one information element IE and/or the at least one instruction I. This instruction I may be an internal primal functioning and/or external incoming instruction e.g. defining a working mode and/or a working constant or variable for the controller (C) 120. The information element IE and/or the instruction I may be transmitted in control signalling of essentially any known communication protocol. For example, 3GPP, WiFi or ITU standards may be used in this respect.

(50) The controller (C) 120 may also be arranged to combine the information element IE and the instruction I with any of monitored power consumption pattern of the at least one electrical load 200n and a determined type of the at least one electrical load for controlling the at least one electrical load.

(51) The controller (C) 120 may further comprise transmitting wired/wireless communication means for transmitting monitored power consumption pattern of the at least one electrical load 200n and/or determined type of the at least one electrical load 200n to other controllers or control devices for further processing.

(52) The controller (C) 120 may be a standalone device such as the one illustrated in FIG. 11, but may in another embodiment be part of a distributed system where e.g. different functions of the controller (C) 120 are located in spatially different locations. For example, the controller (C) 120 may include a master controller (C) and a plurality of slave controllers (not shown in the Figs.). The intelligence may be located in the master controller, which so to speak controls the slave controllers via suitable communication means being wireless and/or wired.

(53) The controller (C) 120 may be a micro controller and may comprise at least one processor for managing the communication and controlling the at least one controllable switch and/or slave controllers. Moreover, it is realized by the skilled person that the present controller (C) 120 may comprise other necessary capabilities in the form of e.g., functions, means, units, elements, etc., for performing the present solution. Examples of other such means, units, elements and functions are: processors, memory, buffers, control logic, transmitters, receivers, encoders, decoders, rate matchers, de-rate matchers, mapping units, multipliers, decision units, selecting units, switches, interleavers, de-interleavers, modulators, demodulators, inputs, outputs, antennas, amplifiers, receiver units, transmitter units, DSPs, TCM decoder, power supply units, power feeders, communication interfaces, communication protocols, etc. which are suitably arranged together for performing the present solution.

(54) Especially, the processor or processors of the present controller (C) may comprise, e.g., one or more instances of a Central Processing Unit (CPU), a processing unit, a processing circuit, a processor, an Application Specific Integrated Circuit (ASIC), a microprocessor, a micro controller or other processing logic that may interpret and execute instructions. The expression processor may thus represent a processing circuitry comprising a plurality of processing circuits, such as, e.g., any, some or all of the ones mentioned above, or another known processor. The processing circuitry may further perform data processing functions for inputting, outputting, and processing of data comprising data buffering and device control functions, such as call processing control, user interface control, or the like.

(55) FIGS. 12a-b show a semi-block representation of the circuit 100 shown in FIG. 10, with additional bias voltages V.sub.bias1; V.sub.bias2 being provided, as described above e.g. in connection with FIGS. 9a-b. Thus, the circuit 100 in FIG. 12a includes a transistor network (TN) 110 in form of the above described common transistor network block (TN block) 123, a controller (C) 120 coupled to a reference ground REF.sub.GND 112 being common to the controller (C) 120 and the at least one controllable switch 106; 108, and a combining circuit 150. The combining circuit 150 is arranged to provide a combined control of the at least one controllable switch 106; 108 based on the value of the at least one voltage V1; V2 by use of the transistor network (TN) 110 and of the controller (C) 120, such that a combined control of the at least one controllable switch 106; 108 is provided. One or more of the at least one transistor T.sub.TN1; T.sub.TN2 of the common transistor network block (TN block) 123 are supplied with at least one bias voltage V.sub.bias1; V.sub.bias2 from a source of energy 400, as described above. The combining circuit 150 is coupled to both the common transistor network block (TN block) 123 and the controller (C) 120, and is also coupled to the first 106 and second 108 controllable switches. The combining circuit 150 is arranged to provide a combined control of the first 106 and second 108 controllable switches based on the at least one voltage V1; V2. Also, at least one driver circuit 114 may be coupled between the combining circuit 150 and the controllable switches 106, 108 (not shown in FIG. 12a). The driver circuit 114 is, as mentioned above, arranged to amplify control signals used for controlling the switches 106, 108 via the control means 130. For further details of the circuit illustrated in FIG. 12a, reference is made to the above description of the circuit 100 illustrated e.g. in FIG. 10.

(56) FIG. 12b shows the combining circuit 150 more in detail. The combining circuit 150 may, according to an embodiment comprise first IN.sub.1 and second IN.sub.2 inputs receiving control signals from the transistor network 110 and the controller (C) 120, respectively. The combining circuit 150 may include first Rim and second R.sub.IN2 resistors coupled in series between the first IN.sub.1 and second IN.sub.2 inputs, respectively, and an output coupled to a node between the first Rim and second R.sub.IN2 resistors. Hereby, the combined control signal is provided by the output of the combining circuit 150 to both of the first 106 and second 108 controllable switches, as illustrated in FIG. 12a.

(57) As mentioned above, the impedance network (Z) 140 may also be coupled between the at least one controllable switch 106; 108 and the output 104. Thus, embodiments corresponding to the ones shown in FIGS. 2-12, and described above, but with the impedance network (Z) 140 instead coupled between the at least one controllable switch 106; 108 and the output 104 are also included within the scope of the present invention. These embodiments function corresponding to what is described above for each respective embodiment shown in FIGS. 2-12, with the difference that the impedance network (Z) is located differently, i.e. between the at least one controllable switch 106; 108 and the output 104.

(58) FIG. 13 schematically shows an alternating current AC breaking arrangement 500 according to an aspect of the present invention. The alternating current AC breaking arrangement 500 comprises an input 102, an output 104, and an alternating current breaking circuit 100 according to any of the herein described embodiments. One or more electrical loads 200n are coupled to the output 104. Further, the alternating current AC breaking arrangement 500 comprises a power supply circuit 400 arranged to perform energy harvesting and to provide electrical power for driving the alternating current breaking circuit 100. Basically, the power supply circuit 400 is arranged to extract/draw electrical power from the alternating current AC, and is arranged to then provide the extracted electrical power to a circuit and/or a device in need of a power supply. For example, the alternating current breaking circuit 100 may here be provided with the extracted electrical power in order to drive the components included in the alternating current breaking circuit 100. For example, the controller (C) 120 included in the circuit 100 in some embodiments needs electrical power to run, and the one or more bias voltages V.sub.bias1, V.sub.bias2 used in some embodiments may be created by use of electrical power.

(59) As illustrated in FIG. 13, the power supply circuit 400 comprises a first parasite arrangement 410, which may also be denoted the high power load parasite voltage arrangement, being arranged to extract a first parasite voltage V.sub.par1 from the alternating current (AC). The first parasite arrangement 410 may comprise a transformer 411 arranged to generate the first parasite voltage V.sub.par1 from the alternating current AC. The transformer 411 may be essentially any kind of magnetic transformer, including e.g. an iron core and at least one coil, suitable for creating the first parasite voltage V.sub.par1 by use of induction and the magnetic field created around the alternating current. The transformer 411 may be located such that the alternating current runs through its core and/or its primary coil winding. For example, the transformer may be arranged at least partly as a ring formed unit/core/winding placed around a conductor carrying the alternating current AC.

(60) The power supply circuit 400 also comprises a second parasite arrangement 420, which may also be denoted a low power load parasite voltage arrangement, being arranged to extract a second parasite voltage V.sub.par2 from the alternating current AC. The second parasite arrangement 420 may be arranged to extract a second parasite voltage V.sub.par2 by extracting a portion of an amplitude of a voltage corresponding to the alternating current AC (as schematically shown in FIGS. 14a-b) and/or by extracting a time duration portion of a cycle of a voltage corresponding to the alternating current AC (as schematically shown in FIG. 14c). In FIGS. 14a-c, the portions extracted from the voltage signals are dashed. There are, as is realised by a skilled person, a number of other methods possible to use for extracting portions of the voltage signals for energy harvesting purposes. The claimed power supply circuit 400 may be configured to extract portions according to one or more of these possible methods.

(61) The power supply circuit 400 also comprises a voltage combiner 430 being arranged to combine the first parasite voltage V.sub.par1 and the second parasite voltage V.sub.par2. The voltage combiner 430 may for this reason comprise two rectifying diodes 431; 432 being coupled at their inputs to the first 410 and second 420 parasite arrangements, respectively, to be fed with the first V.sub.par1 and second V.sub.par2 parasite voltages. The outputs of the two rectifying diodes 431; 432 are coupled together to form a combined parasite voltage V.sub.par_comb, which is provided to the alternating current breaking circuit 100.

(62) According to an embodiment, the first 410 and second 420 parasite arrangements may be arranged to communicate 440 in simplex or duplex mode with each other, such that one of the first 410 and second 420 parasite arrangements is regarded as a master unit, arranged for controlling the other one of the first 410 and second 420 parasite arrangements, which is then regarded as a slave unit. Also, information may be communicated 440 to the controller (C) 120 of the alternating current breaking circuit 100. The information provided to the controller (C) 120 may include e.g. power consumption and/or load information. The controller (C) 120 may then use this information to switch between active and standby modes for the controller (C) 120.

(63) The combined use of the first 410 and second 420 parasite arrangements is very advantageous, since they complement each other very well. The first parasite arrangement 410 works well for higher power, i.e. for stronger AC currents, since the transformer 411 is well suited to create the first parasite voltage V.sub.par1 during strong currents. The second parasite arrangement 420, however, works poorly for strong currents, since the voltage extraction methods used by the second parasite arrangement 420 may cause heating of the second parasite arrangement 420 and/or may cause current/voltage transients and/or steps that need to be filtered. Filtering of such strong currents today demands for a bulky filter, which normally does not fit into an alternating current breaker. The second parasite arrangement 420 works well for lower power, i.e. for weaker AC currents. The first parasite arrangement 410, on the other hand, can often not extract a useful voltage from the alternating current AC if the current is not strong enough.

(64) According to an embodiment, the first parasite arrangement 410 is used mainly for extracting the first parasite voltage V.sub.par1 during stronger current time periods, and the second parasite arrangement 420 is used mainly for extracting the second parasite voltage V.sub.par2 during weaker current time periods. Thus, when these two extracting methods are combined, as is performed according to the embodiment, a reliable and useful combined parasite voltage V.sub.par_comb may be provided as a power supply to the alternating current AC breaking circuit 100 during essentially any condition when the one or more loads 200n consume power.

(65) Since the first V.sub.par1 and second V.sub.par2 parasite voltages are extracted from the alternating current AC in series with the one or more loads, the power supply circuit 400 will always be able to provide power to the alternating current breaking circuit 100 when current is provided to the one or more active loads. Also, when the one or more loads are inactive, a leakage current I.sub.leak still runs to the ground/earth at the loads, which often is enough for creating at least the first V.sub.par1 parasite voltage. Thus, a reliable and useful combined parasite voltage V.sub.par_comb may be provided as a power supply to the alternating current AC breaking circuit 100 during essentially any condition, also when the one or more loads 200n do not consume power.

(66) Further applications of the present invention may relate to power consumption of the at least one electrical load and the controlling of the at least one electrical load.