Power Electronic Module Comprising a Gate-Source Control Unit

Abstract

A power electronic module (2) includes at least one semiconductor switch (4) and a gate-source control unit. The gate-source control unit includes an asymmetric transient voltage suppressor (TVS) diode (8) or two Zener diodes (10, 10) or one or more avalanche diodes arranged between the gate terminal (G) and the source terminal (S) of the semiconductor switch (4).

Claims

1. A power electronic module comprising at least one semiconductor switch and a gate-source control unit, wherein the gate-source control unit comprise an asymmetric transient voltage suppressor (TVS) diode or two Zener diodes or one or more avalanche diodes arranged between the gate terminal and the source terminal of the semiconductor switch.

2. The power electronic module according to claim 1, wherein the semiconductor switch is a Power Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET).

3. The power electronic module according to claim 1, wherein the semiconductor switch is a junction gate field-effect transistor (JFET).

4. The power electronic module according to claim 1, wherein the semiconductor switch is a bipolar transistor.

5. The power electronic module according to claim 1, wherein the semiconductor switch is a SiC-based semiconductor switch.

6. The power electronic module according to claim 1, wherein the semiconductor switch is a Gallium nitride (GaN)-based switch.

7. The power electronic module according to claim 1, wherein the semiconductor switch is an Insulated Gate Bipolar Transistor (IGBT).

8. The power electronic module according to claim 2, wherein the semiconductor switch is a N-Channel Enhancement Mode MOSFET.

9. The power electronic module according to claim 2, wherein the semiconductor switch is a silicon carbide (SiC) MOSFET.

10. The power electronic module according to claim 1, wherein the power electronic module comprises: a first terminal electrically connected to the gate terminal; a second terminal electrically connected to the source terminal; and a third terminal electrically connected to the drain terminal of the semiconductor switch, wherein no Zener diode is arranged between the source terminal and the drain terminal.

11. The power electronic module according to claim 1, wherein the gate-source control unit comprise a first avalanche diode that has a breakdown voltage in the range of 5-35 V and a second avalanche diode that has a breakdown voltage of 5-35 V.

12. The power electronic module according to claim 2, wherein the semiconductor switch is MOSFET that has a maximum dynamic gate-source voltage range of 8V to 19V.

13. The power electronic module according to claim 1, wherein the power electronic module is configured to drive the asymmetric TVS diode or the two Zener diodes or the one or more avalanche diodes with a static current.

14. The power electronic module according to claim 1, wherein the gate-source control unit is arranged internally in the power electronic module and that the power electronic module comprises a circuit carrier substrate.

15. The power electronic module according to claim 1, wherein no additional electrical components other than the TVS diode or two Zener diodes or the one or more avalanche diodes are arranged between the gate terminal and the source terminal of the semiconductor switch.

16. The power electronic module according to claim 1, wherein the gate-source control unit is mounted on the same substrate as the semiconductor switch.

17. The power electronic module according to claim 1, wherein the gate-source control unit is mounted a different substrate to the substrate on which the semiconductor switch is mounted.

18. The power electronic module according to claim 8, the semiconductor switch is a silicon carbide (SiC) MOSFET.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0059] The invention will become more fully understood from the detailed description given herein below. The accompanying drawings are given by way of illustration only, and thus, they are not limitative of the present invention. In the accompanying drawings:

[0060] FIG. 1 shows a circuit diagram of a first embodiment according to the invention;

[0061] FIG. 2 shows the recommended and maximum voltage for reliable operation of a SiC MOSFET;

[0062] FIG. 3A shows the current and voltage of the as function of time for a power electronic device according to the invention and a prior art power electronic device and, shows a graph depicting the current as function of time for a power electronic device according to the invention and a prior art power electronic device;

[0063] FIG. 3B shows the current and voltage of the as function of time for a power electronic device according to the invention and a prior art power electronic device and, shows a graph depicting the voltage as function of time for a power electronic device according to the invention and a prior art power electronic device;

[0064] FIG. 4 shows a circuit diagram of a second embodiment according to the invention according to the invention;

[0065] FIG. 5A shows a circuit diagram of one embodiment according to the invention; and

[0066] FIG. 5B shows another view of the same circuit diagram as shown in FIG. 5A.

DETAILED DESCRIPTION

[0067] Referring now in detail to the drawings for the purpose of illustrating preferred embodiments of the present invention, a circuit diagram of a first embodiment according to the invention is illustrated in FIG. 1.

[0068] FIG. 1 illustrates a circuit diagram of a first embodiment of a power electronic module 2 according to the invention. The power electronic module 2 comprises a gate-source control unit (also referred to as a gate driver) arranged internally in a power electronic module 2. In a preferred embodiment, the power electronic module 2 comprises a circuit carrier substrate such as a Direct Copper Bond substrate (DCB-substrate), a Direct Aluminium Bond substrate (DAB-substrate), an Active Metal Braze substrate (AMB-substrate), a Printed Circuit Board substrate (PCB-substrate) or other known forms of circuit carrier substrate. A DC voltage source with potentials V.sub.1 and 7V is indicated.

[0069] By internally is meant that the gate-source control unit herein described is contained within the packaging that constitutes the power electronics module 2. Such packaging may take a number of forms well known within the field and dictated by the application environment of the power electronics module, or the specific requirements of manufacturing or use. One known packaging is that of a molded module, where the control and switching circuitry is totally encapsulated in an insulating mold material and conducting leads protrude from the mold material. Another known packaging is that of a frame module, where the substrate on which electronic components such as the semiconductor switch 2 and/or the gate-source control unit is surrounded by an open frame which is closed by a lid. A common characteristic of a packaging is that it protects the electronic components, such as the semiconductor switch 2 and/or the gate-source control unit, and connection circuitry from environmental dust or humidity as well as protecting such components from shock loadings.

[0070] The power electronic module 2 comprises a first terminal T.sub.1 and a second terminal T.sub.2. The power electronic module 2 comprises a semiconductor switch shaped as a SiC MOSFET 4 having a gate terminal G, a source terminal S, and a drain terminal D. Two Zener diodes 10, 10 are oppositely connected and arranged between the gate terminal G and the source terminal S of the SiC MOSFET 4. The two Zener diodes 10, 10 are capable of stabilizing the gate driver voltage.

[0071] It can be seen that no additional electrical components other than the two Zener diodes 10, 10 are arranged between the gate terminal G and the source terminal S of the SiC MOSFET 4. Moreover, the resistance and inductance are indicated by resistors R.sub.1, R.sub.4 and inductors L.sub.3, L.sub.5, L.sub.8, L.sub.9.

[0072] As previously explained, the SiC MOSFET 4 may be replaced by another type of semiconductor switch. The SiC MOSFET 4 may be replaced by another type of semiconductor switch such as one of the following: a MOSFET (not a SiC MOSFET), a JFET, a bipolar transistor, a GaN-based switch or an IGBT. It is also possible that an internal gate resistor is arranged. This is also represented by R.sub.4.

[0073] FIG. 2 illustrates the recommended and maximum voltage for carrying out a reliable operation of a SiC MOSFET. It can be seen that a parasitic and unwanted turn-on P occurs. Maintaining a reliable operation of a SiC MOSFET like the one shown in the power electronic module illustrated in FIG. 1, the gate-source voltage V.sub.GS is not allowed to fall below 4V. Accordingly, the static gate voltage V.sub.2 has to be above 4V, however, this causes the parasitic turn-on P illustrated in FIG. 2

[0074] FIG. 3A illustrates a first graph depicting the current I.sub.1 through the terminal inductance (illustrated as L.sub.8 in FIG. 1) as function of time for a power electronic device according to the invention and a second graph depicting the corresponding current I.sub.2 as function of time for a prior art power electronic device. The current I.sub.1 is indicated by a solid line, wherein the current I.sub.2 is indicated by a dashed line.

[0075] FIG. 3B illustrates a first graph depicting the gate-source voltage V.sub.gs of a prior art power electronic device (having a reference circuit without Z-diodes) as function of time. FIG. 3B moreover illustrates a second graph depicting the gate-source voltage V.sub.gs of a reference circuit of a power electronic device according to the invention (corresponding to the one illustrated in and explained with reference to FIG. 1). It can be seen that the amplitude of the gate-source voltage V.sub.gs of the prior art power electronic device is much larger than the amplitude of the gate-source voltage V.sub.gs of a reference circuit of a power electronic device according to the invention.

[0076] FIG. 3B illustrates a third graph depicting the reverse recovery current I.sub.4 of a prior art power electronic device (having a reference circuit without Z-diodes) as function of time. FIG. 3B also illustrates a fourth graph depicting the reverse recovery current I.sub.3 of a reference circuit of a power electronic device according to the invention (corresponding to the one illustrated in and explained with reference to FIG. 1). When comparing I.sub.3 and I.sub.4 it can be seen that there is a large parasitic turn-on associated with using a prior art power electronic device (having a reference circuit without Z-diodes).

[0077] When applying internal Z-diodes as explained with reference to FIG. 1, these Z-diodes will stabilize the driver voltage of e.g. 7V to 4V. Accordingly, there is a current flow through the terminal and the terminal inductance, which will advantageously affect the inductance.

[0078] When the Z-diodes are omitted, the current I.sub.4 during the reverse recovery is raised to a higher level (see the reverse recovery currents I.sub.3 and I.sub.4 with big turn on).

[0079] FIG. 4 illustrates a circuit diagram of a second embodiment of a power electronic module 2 according to the invention. The power electronic module 2 comprises a gate-source control unit (also referred to as a gate driver) arranged internally in a power electronic module 2. In a preferred embodiment, the power electronic module 2 comprises a circuit carrier substrate such as a DCB-substrate. A DC voltage source with potentials V.sub.1 and 7V is indicated.

[0080] The power electronic module 2 comprises a first terminal T.sub.1 and a second terminal T.sub.2. The power electronic module 2 comprises a semiconductor switch shaped as a SiC MOSFET 4 having a gate terminal G, a source terminal S and a drain terminal D. A TVS diode 8 is arranged between the gate terminal G and the source terminal S of the SiC MOSFET 4. The TVS diode 8 is capable of stabilizing the gate driver voltage.

[0081] No additional electrical components other than the TVS diode 8 is arranged between the gate terminal G and the source terminal S of the SiC MOSFET 4. Moreover, the resistance and inductance are indicated by resistors R.sub.1, R.sub.4 and inductors L.sub.3, L.sub.5, L.sub.8, L.sub.9. It is also possible that an internal gate resistor is arranged. This is also represented by R.sub.4.

[0082] FIG. 5A illustrates a circuit diagram of the gate-source control unit of a power electronic module according to the invention. The circuit diagram is a simplified version of and thus basically corresponds to the diagram shown in FIG. 1. When the gate-source control unit comprise a first and a second Zener diode, the breakdown voltage should be selected in an appropriate manner. In one embodiment gate-source control unit comprise a first avalanche diode having a breakdown voltage in the range of 15-25 V. The second avalanche diode may have a breakdown voltage of 15-25 V.

[0083] With reference in FIG. 5A one can find that the following inequality is fulfilled:

(V.sub.GDS(max)V.sub.RG)>(V.sub.C1(I)+V.sub.C2(I))>V.sub.GS(max)(1)

[0084] In normal operation (static) the following is fulfilled:

V.sub.C1(I)=V.sub.GS(max)(2)

[0085] During switching, the gate can be overloaded due to inductance. Accordingly, a non-zero (e.g. 0.5 A) current I is flowing and one can find that:

V.sub.C1(I)=V.sub.GS(max)V.sub.C2(I)(3)

During short circuit, the above-mentioned equation (3) is valid and the Miller current is significant (e.g. approximately 1 A if V.sub.GDS(max) is about 20 V).

[0086] FIG. 5B illustrates another view of the same circuit diagram as shown in FIG. 5A. With reference in FIG. 5B one can find derive that

V.sub.GS(min)=V.sub.C1(I)+V.sub.C2(I)(4)

[0087] Accordingly, it follows that:

V.sub.C2(I)=V.sub.GS(min)V.sub.C1(I)(5)

[0088] In the static situation we find that:

I=I.sub.GDS(6)

[0089] It is possible to use compensate for the Miller current (e.g. in the range 1-2 A).

[0090] Due to the reverse recovery the VGS is rising very steep. The raise of the VGS and V.sub.GD (dV/dt) causes a current through the miller-capacitance. This current has to be drained by the gate drive unit (GDU). The gate resistors and the inductances of the wires will reduce the current derivative (dl/dt) and the capability to drain the current through the Miller capacitance suddenly. If there is a static current (from the Zener diode into the GDU) through the inductance, this current is not needed to be raised. The bias current can compensate the current through the Miller capacitance. The bias current is limited by the power capability of the GDU, the Diodes (Z, TVS or avalanche type) and the gate resistors.

[0091] While the present disclosure has been illustrated and described with respect to a particular embodiment thereof, it should be appreciated by those of ordinary skill in the art that various modifications to this disclosure may be made without departing from the spirit and scope of the present disclosure.