Thermal detectors using graphene and oxides of graphene and methods of making the same

Abstract

Radiation detecting and sensing systems using graphene and methods of making the same are provided; including a substrate, a single or multiple layers of graphene nanoribbons, first and second conducting interconnects each in electrical communication with the graphene layers. Graphene layers are tuned to increase the temperature coefficient of resistance, increasing sensitivity to IR radiation. Absorption over a wide wavelength range (200 nm to 1 mm) is possible based on the three alternative devices structures described within. Devices can variously include (a) a microbolometer based graphene film where the TCR of the layer is enhanced with selected functionalization molecules, (b) graphene layers with a source and drain metal interconnect and a deposited metal of SiO2 gate which modulates the current flow across the phototransistor detector, and/or (c) tuned graphene layers layered on top of each other where a p-type layer and a n-type layer is created using a combination of oxidation and doping.

Claims

1. A graphene based microbolometer comprising: a thin film of graphene nanoribbon deposited on a substrate between electrical contacts, the thin film of graphene nanoribbon is tuned to be sensitive to Infrared (IR) radiation in the micron band of 1 to 12 microns; first and second conductive terminals in electrical communication with the thin film of graphene nanoribbon; and wherein the thin film of graphene nanoribbon is tuned such that exposure of IR radiation induces a change in impedance between the first and second conductive terminals which is sensed by CMOS readout circuitry; wherein the thin film of graphene nanoribbon is tuned to increase the sensitivity of the detector by exposing the graphene nanoribbon to an oxidation environment, which thereby increases the thermal coefficient of resistance (TCR) to excess of 4 percent per degree centigrade and up to 6 percent per degree centigrade, thereby resulting in a Noise Equivalent Delta Temperature (NEDT) of less than 10 mK.

2. The graphene based detector of claim 1 further comprising sensing circuitry for detecting changes in input impedance using the CMOS readout circuitry.

3. The graphene based detector of claim 1 wherein the thin film of graphene nanoribbon is deposited on the substrate having an insulating layer comprised of dielectric material with a cantilever beam composed of silicon nitride, which is suspended over a channel, thereby providing thermal isolation from surrounding environments.

4. The graphene based detector of claim 1 wherein the thin film of graphene nanoribbon is deposited by chemical vapor deposition and the substrate comprises vanadium oxide and amorphous silicon to assist in the improvement of photon absorption.

5. The graphene based detector of claim 1 wherein the first and second conductive terminals comprise one of: palladium and platinum, thereby enhancing the pi bonding to the thin film of graphene and reducing contact resistance.

6. The graphene based detector of claim 1 wherein the thin film of graphene nanoribbon is optimized for wavelength absorption by use of functionalization molecules or nanoparticles tuned to a predetermined wavelength.

7. A graphene based infrared (IR) detector comprising: a substrate; a thermally isolated graphene nanoribbon suspended by a gap above the substrate, the gap being in the range of approximately 50-350 nm; first and second conductive terminals in electrical communication with the graphene nanoribbon; and wherein the thermally isolated graphene nanoribbon is tuned such that exposure to IR radiation induces a change in impedance between the first and second conductive terminals which is sensed by CMOS readout circuitry; wherein the thermally isolated graphene nanoribbon is tuned by oxidation processing, which thereby increases the thermal coefficient of resistance (TCR) to excess of 4 percent per degree centigrade and up to 6 percent per degree centigrade, thereby resulting in a Noise Equivalent Delta Temperature (NEDT) of less than 10 mK.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The invention description below refers to the accompanying drawings, of which:

(2) FIG. 1 is a schematic diagram of a microbolometer detecting element according to an illustrative embodiment employing a graphene sensing element fabricated on a generic CMOS wafer process;

(3) FIG. 2A is a schematic diagram of the resulting structure after a first step is performed in fabrication of a graphene based thermal detector, in which a film is deposited on a substrate and standard photolithography creates a hole over the tungsten (W) plugs, according to the illustrative embodiment;

(4) FIG. 2B is a schematic diagram of the resulting structure after another step is performed in the fabrication of the thermal detector, in which a thin film of Cu is deposited, according to the illustrative embodiment;

(5) FIG. 2C is a schematic diagram of the resulting structure after another step is performed in the fabrication of the thermal detector, in which a layer of amorphous silicon is deposited, according to the illustrative embodiment;

(6) FIG. 2D is a schematic diagram of the resulting structure after another step is performed in the fabrication of the thermal detector, in which the layer of amorphous silicon is planarized using chemical-mechanical polishing, according to the illustrative embodiment;

(7) FIG. 2E is a schematic diagram of the resulting structure after another step is performed in the fabrication of the thermal detector, in which contact holes are provided through the amorphous silicon and silicon oxide layers, thereby clearing the material down to the underlying tungsten (W) plus, according to the illustrative embodiment;

(8) FIG. 2F is a schematic diagram of the resulting structure after another step is performed in the fabrication of the IR detector, in which standard CMOS interconnect metallurgy is deposited, according to the illustrative embodiment;

(9) FIG. 2G is a schematic diagram of the resulting structure after another step is performed in the fabrication of the IR detector, in which a graphene layer is deposited, according to the illustrative embodiment;

(10) FIG. 2H is a schematic diagram of the resulting IR detector after the final step is performed in the fabrication of the IR detector, in which the graphene layer is masked off to create the image detector design desired and the amorphous silicon in the cavity is etched, according to the illustrative embodiment;

(11) FIG. 3 is a perspective view of the fully assembled graphene based microbolometer using a suspended graphene detecting element, in accordance with an illustrative embodiment;

(12) FIG. 4 is a top view of a matrix of graphene based microbolometers or photo field effect transistor arrays comprising a focal plane array, in accordance with the illustrative embodiments;

(13) FIG. 5 is a schematic diagram of the CMOS readout circuit for the graphene detector elements, in accordance with the illustrative embodiments;

(14) FIG. 6 is a graphical diagram of the measured film resistance of a graphene layer versus temperature, according to the illustrative embodiment;

(15) FIG. 7A is a schematic diagram of a photo-field effect transistor device structure incorporating a graphene layer or multilayer, in accordance with the illustrative embodiments; and

(16) FIG. 7B is a band gap diagram of the structure of FIG. 7A, according to the illustrative embodiments.

DETAILED DESCRIPTION

(17) Devices including graphene single layers or multilayers suspended over gaps (for example, gaps of approximately 50-250 nm) can be employed as Infrared (IR) radiation detectors. In addition, the application of graphene single layer or multilayers on a thermally isolated cantilever beam can be employed as an IR radiation detector.

(18) Graphene based detectors have several important and unique features that are not available with existing technologies. First, arrays of these nanotube light detectors can be formed using patterning technology at minimum dimensions of the lithography node used or dictated by the demands of the optical imaging system. It is possible to create 25, 17, or 8 micron square or less detectors limited only by photolithography techniques.

(19) Illustrative embodiments of the invention allow integration at a level of one light detector per ten or less transistors at the minimum dimension of a given lithography node or the integration of large arrays that are addressed by CMOS pre-amplification or readout and logic circuits. Previously only discrete components, such as silicon p-n diodes, could be used as light detectors for optoelectronic circuits. Other types of detectors require complex and difficult fabrication techniques such as flip-chip processes to integrate with silicon semiconductor technology. Because CNT light sensors can be integrated to form VLSI arrays, which allows for optical interconnects having one light detector per transistor (or waveguide, depending on function), the fabrication of ultra-dense optical circuits is possible.

(20) According to illustrative embodiments, light detecting elements have a suspended region of nanofabric overlying a substrate material. FIG. 1 shows a schematic diagram of an IR detector having a graphene based fabric sensing element fabricated on a generic CMOS wafer. The IR detector incorporates a graphene based fabric sensing element for performing the infrared detection. The IR detector 100 includes a conventional P-N junction substrate 101, which is part of the overall CMOS logic 110. The substrate 101 can comprise silicon using a Bridgman float zone technique. There is a film 120 deposited on the substrate 101 as well as the graphene nanoribbon IR sensors 130, for performing the IR detection. The film 120 can comprise a silicon oxide layer based upon the absorption frequency for the type of device. The IR detector 101 is fabricated in accordance with the procedures outlined in FIGS. 2A through 2I.

(21) Light detectors can be constructed using suspended or non-suspended nanotube-based fabrics in combination with appropriate substrates. Fabrication techniques to develop such horizontally- and vertically-disposed fabrics and devices composed of nanotube fabrics which comprise redundant conducting nanotubes may be created via CVD, or by room temperature operations as described herein. For useful background material on fabrication of carbon nanotubes, refer to U.S. Pat. No. 6,706,402, and published PCT Application No. WO 01/03208, which are expressly incorporated by reference herein. Because creation of suspended graphene-based detector elements is like fabrication of suspended nanotube-based memory elements described in the incorporated U.S. Pat. No. 6,706,402 and WO 01/03208, reference can be made to these materials for background information on the fabrication of suspended graphene-based detector elements. Such detectors can be part of a scheme involving signal transmission or use in a display.

(22) The substrate material 101 can be an insulator such as one described hereinabove or can be a semiconductor (such as, but not limited to, Si (single crystal, polycrystalline and amorphous), Ge, SiGe, SiC, Diamond, GaN, GaAs, GaP, AlGaAs, InP, GaP, CdTe, AlN, InAs, Al.sub.xIn.sub.1-xP, and other III-V and II-VI semiconductors) or a conductor (such as, but not limited to, Al, Cu, W, Al(<1% Cu), Co, Ti, Ta, W, Ni, Mo, Pd, Pt, TiW, Ru, CoSi.sub.x, WSi.sub.2, TiSi.sub.x, TaN, TiN, TiAlN, RuN, RuO, PtSi, Pd.sub.2Si, MoSi.sub.2, NiSi.sub.x). The substrate material systems can be chosen for circuitry technologies and light absorption considerations, the graphene fabric and associated microbolometer structure processing are compatible with all of these materials. The suspended region (see region 272 of FIG. 2H) defines the electromagnetic sensing region of the detecting element 100.

(23) The layers are composed of several layers of overlapping graphene layers to create a multilayered film of greater than approximately 10 nm. The graphene layer(s) can be grown or deposited on a surface, as described hereinabove, to form a contiguous film of a given density. Typically, the lower dimension sizes of the nanotube film are a consequence of lithographic technology limitations and not any limitations of the illustrative embodiments herein. After patterning, the graphene layers can be further integrated with metal interconnects and dielectric passivation layers to create a circuit element. The light detection from the detecting element 130 is controlled by driving circuitry. Refer to FIG. 5 for a diagram of exemplary driving circuitry 510, 520, 521 and 530.

(24) Light detectors can be constructed using suspended or non-suspended graphene-based fabrics in combination with appropriate substrates. Fabrication techniques to develop such horizontally- and vertically-disposed fabrics and devices composed of nanotube fabrics which comprise redundant conducting graphene can be created via CVD, or by room temperature operations as described herein and others known in the art. Refer, for example, to U.S. Pat. Nos. 6,574,130, 6,643,165, 6,706,402, 6,784,028, 6,835,591, 6,911,682, 6,919,592, and 6,924,538, for useful background information on fabrication of graphene-based fabrics.

(25) Light can be impinged on the open area of these bundled carbon nanotube fabrics to cause the generation of heat in the fabric, such as a bolometer. Or in the case of the phototransistor based photodetectors the absorbed light carriers

(26) Suspended graphene layers are ideal structures for monolayered fabrics, which have a high porosity. Since the substrate may influence the detection of radiation, the suspended region should diminish any disadvantageous substrate thermal isolation effects.

(27) Reference is now made to FIGS. 2A-2H, showing the various stages of the fabrication procedure for an IR detector incorporating graphene layers. Standard CMOS microelectronics processing techniques, graphene nanoribbon process flow or the CVD (chemical vapor deposition) process can be employed to fabricate the detector in accordance with the illustrative embodiments herein. As shown in FIG. 2A, using standard CMOS microelectronics processing techniques, a deposited silicon oxide film 201 is deposited on the substrate 202. A standard photolithography method, known in the art, is used to create a hole 205 over the tungsten (W) plugs. The Tungsten plugs 203 serve as interconnects to the underlying CMOS pre-amplification circuitry 204. Refer to FIG. 5 for a diagram of an exemplary CMOS circuitry. The next step, as shown in FIG. 2B, is to use electron beam evaporation or direct current sputtering to deposit a thin film of Copper (Cu) 211 which serves as an IR photon reflector.

(28) As shown in FIG. 2C, in the next step of the fabrication process a layer of amorphous silicon 220 is deposited and planarized using chemical-mechanical polishing to result in the amorphous silicon 230 of FIG. 2D. The next step is use standard photolithography techniques using a photoresist stencil and reactive ion etching to etch contacts holes 240 through the amorphous silicon and silicon oxide layers clearing the material down to the underlying tungsten plugs which serve as interconnects to the underlying CMOS circuitry, as shown in FIG. 2E. The next step is to use direct current sputtering to deposit standard CMOS interconnect metallurgy, aluminum-copper thin films 250. Standard photolithographic/dry etch techniques are used to delineate the interconnect structures, as shown in FIG. 2F. The next step, as shown in FIG. 2G, is to deposit graphene layer(s) 260. The final steps are to mask off the graphene fabric and employ standard photolithographic methods to create the image the detector design required. Finally using XeFl2 (Xenon Difluoride) etching, or other techniques known in the art, the amorphous silicon in the cavity is etched and a gap or cavity 272 is created, which results in the fully fabricated device as shown in FIG. 2H having a suspended region of graphene-based fabric 270 overlying the gap 272. Also refer to FIG. 3 for a perspective view of the fully fabricated device.

(29) One indicator for process optimization is to use CNT based field effect transistors (for example as shown in FIG. 7A) and measure the ratio of the current on over the current off After the optimized space is determined then the process is further optimized by examining the graphene sheets with Transmission Electron Microscope for defects, electronic mobility and degree of CNT rupture.

(30) Reference is now made to FIG. 3, showing a perspective view of a fully assembled graphene based microbolometer, according to an illustrative embodiment. A graphene based microbolometer structure 300 is shown, having readout locations 310. The structure 300 includes a graphene nanoribbon fabric 312 suspended above the substrate 313, in accordance with the techniques described herein and readily apparent to those having ordinary skill. The thermally isolated cantilever structure 314 is also shown, as well as the connection to tungsten (W) plugs 316. An array of graphene nanoribbon based microbolometers is shown in the top view of FIG. 4, in accordance with the illustrative embodiments. The array 400 of microbolometers includes a plurality of microbolometers 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, and 414.

(31) FIG. 5 is a schematic diagram of an exemplary CMOS readout circuit for the graphene nanoribbon IR detector in accordance with the illustrative embodiments. As shown in the diagram 500, there is a common half circuit 510 operatively connected to a unit cell circuit 520 which includes the IR detector 521. A dynamic discharging output stage circuit 530 is operatively connected to the unit cell circuit 520 to define the overall CMOS readout circuit 500.

(32) FIG. 6 is a graphical diagram of the measured film resistance of the graphene layer versus the temperature, according to the illustrative embodiments. As described hereinabove, the electrical resistance of the microbolometers changes as the temperature rises due to the absorption of electromagnetic radiation in the fabric. This is illustrated in the graphical diagram 610 of FIG. 6. As shown, during both the first pass 621 and the second pass 622, as the temperature increases, the resistance of the microbolometer changes. Accordingly, this allows the structure to be employed as an IR detector in accordance with the illustrative embodiments.

(33) Reference is now made to FIG. 7A showing a schematic diagram of a photo-field effect transistor device structure incorporating a graphene layer or multilayer, according to an illustrative embodiment. As shown, the fully assembled IR detector is operatively connected to source and ground where appropriate to provide a photo-field effect transistor. A source 701 and drain contact 702 are deposited and etched onto a silicon oxide layer 703 that is deposited on a substrate 704, such as silicon, GaAs, or other compound semiconductors. Graphene layers 705 are fabricated and deposited on the silicon oxide layer 703. The next step is to expose the graphene layers to an oxidation environment at sufficient temperature. Each layer is then exposed to a dopant either n-type of p-type and then the next graphene layer is exposed to the opposite dopant type creating a n-on-p or p-on-n structure. A CMOS compatible thin film metal 706 is then deposited, such as palladium or platinum, upon which the source and drain contacts 701, 702 are fabricated.

(34) A metal or oxide gate electrode 707 is fabricated on top of the graphene layer or layers. The gate electrode 707 can comprise a deposited metal of SiO2, which modulates the current flow across the phototransistor detector. In some embodiments, it may be necessary to fabricate a space 708 between the top of the graphene and the bottom of the metal or silicon oxide gate electrode.

(35) FIG. 7B shows a band gap diagram of the photo-field effect transistor of FIG. 7A. As shown, with the initiation of photon illumination, electrons move either towards the Vd level or into the conduction band. Holes move toward the Vg level, thereby creating a depletion region in the p-n junction.

(36) The various illustrative embodiments afford efficient thermal detectors by employing graphene layers. Oxidation of the graphene results in semiconducting behavior and, with the addition of a n-type or p-type dopant, results in either n-on-p or p-on-n diode devices with very high mobility. This results in high sensitivity and fast detector response operation. The resulting devices can be optimized for detection of UV and Terahertz radiation, in accordance with the illustrative embodiments.

(37) The teachings herein can be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are therefore to be considered illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description.

(38) The foregoing has been a detailed description of illustrative embodiments of the invention. Various modifications and additions can be made without departing from the spirit and scope of this invention. Each of the various embodiments described above may be combined with other described embodiments in order to provide multiple features. Furthermore, while the foregoing describes a number of separate embodiments of the apparatus and method of the present invention, what has been described herein is merely illustrative of the application of the principles of the present invention. For example, the illustrative embodiments can include additional layers to perform further functions or enhance existing, described functions. Likewise, the electrical connectivity of the cell structure with other cells in an array and/or an external conduit is expressly contemplated and highly variable within ordinary skill. Additionally, it is expressly contemplated that single-wall nanotubes, multi-wall nanotubes, and any combination thereof, can be employed. More generally, while some ranges of layer thickness and illustrative materials are described herein, these ranges are highly variable. It is expressly contemplated that additional layers, layers having differing thicknesses and/or material choices can be provided to achieve the functional advantages described herein. In addition, directional and locational terms such as top, bottom, center, front, back, on, under, above, and below should be taken as relative conventions only, and are not absolute. Furthermore, it is expressly contemplated that various semiconductor and thin film fabrication techniques can be employed to form the structures described herein. Accordingly, this description is meant to be taken only by way of example, and not to otherwise limit the scope of this invention.