Semiconductor Device and Method for Producing a Carrier Element Suitable for a Semiconductor Device

Abstract

A semiconductor device and a method for producing a carrier element suitable for a semiconductor device are disclosed. In an embodiment a semiconductor device includes a carrier element including a carrier layer having a first depression extending from a first main surface of the carrier layer in a direction of a second main surface of the carrier layer opposite the first main surface and a metal substrate and an electrically insulating layer on at least a portion of the metal substrate, a first electrically conductive filling component arranged in the first depression in a form-fitting manner, the electrically insulating layer being arranged between the metal substrate and the first filling component and a semiconductor chip arranged on the carrier element, wherein the electrically insulating layer is an anodization layer.

Claims

1-15. (canceled)

16. A semiconductor device comprising: a carrier element comprising: a carrier layer comprising: a first depression extending from a first main surface of the carrier layer in a direction of a second main surface of the carrier layer opposite the first main surface; and a metal substrate and an electrically insulating layer on at least a portion of the metal substrate; a first electrically conductive filling component arranged in the first depression in a form-fitting manner, the electrically insulating layer being arranged between the metal substrate and the first filling component; and a semiconductor chip arranged on the carrier element, wherein the electrically insulating layer is an anodization layer.

17. The semiconductor device according to claim 16, wherein the metal substrate is made of a metal or a metal alloy and the electrically insulating layer is an oxidized layer of the metal or metal alloy of the metal substrate.

18. The semiconductor device according to claim 16, wherein the metal substrate is made of aluminium or an aluminium alloy and the electrically insulating layer is an oxidized layer of aluminium or an aluminium alloy.

19. The semiconductor device according to claim 16, wherein the metal substrate is completely covered by the electrically insulating layer.

20. The semiconductor device according to claim 16, wherein the first filling component comprises a metal.

21. The semiconductor device according to claim 16, wherein the first filling component consists essentially of copper.

22. The semiconductor device according to claim 16, wherein the first filling component is at least partly electrodeposited in the depression.

23. The semiconductor device according to claim 16, wherein the first depression is a through-hole completely penetrating the carrier layer.

24. The semiconductor device according to claim 16, wherein the semiconductor chip is mounted on a first surface of the first filling component, the first surface laterally projecting over the semiconductor chip.

25. The semiconductor device according to claim 16, wherein the first filling component comprises at least one first region and at least one second region, and wherein the first region follows the second region in a vertical direction and has a greater lateral size than the second region.

26. The semiconductor device according to claim 16, wherein the carrier element comprises a second electrically conductive filling component arranged in a form-fitting manner in a second depression of the carrier layer, and wherein the first filling component has a greater lateral size than the second filling component.

27. The semiconductor device according to claim 26, wherein the first filling component is a first electric terminal of the semiconductor device and the second filling component is a second electric terminal of the semiconductor device.

28. The semiconductor device according to claim 16, wherein the carrier element comprises a structured cover layer overlaying a first surface of the first filling component and/or a second filling component and/or a second surface of the first filling component and/or a second filling component.

29. A method for producing a carrier element suitable for a semiconductor device, the method comprising: providing a metal substrate; producing a first depression in the metal substrate; producing an electrically insulating layer on at least a portion of the metal substrate; and at least partly electrodepositing a first electrically conductive filling component in the first depression in a form-fitting manner, wherein the electrically insulating layer is arranged between the metal substrate and the first filling component, and wherein the electrically insulating layer is produced by anodizing at least a portion of the metal substrate.

30. The method according to claim 29, wherein the first depression is produced by punching or drilling the metal substrate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Further advantages, advantageous embodiments and further developments become clear from the exemplary embodiments described in the following in connection with the figures.

[0041] FIGS. 1 and 2 show schematic sectional views of semiconductor devices according to different exemplary embodiments; and

[0042] FIGS. 3 to 7 show schematic sectional views of various method steps of a method for producing a carrier element according to an exemplary embodiment of a method, and FIGS. 3 to 8 show schematic sectional views of various method steps of a method for producing a semiconductor device according to an exemplary embodiment of a method.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0043] FIG. 1 shows a first exemplary embodiment of a semiconductor device 1, which preferably is a radiation-emitting device. The semiconductor device 1 comprises a carrier element 2 and preferably a radiation-emitting semiconductor chip 3 arranged on the carrier element 2. The carrier element 2 has a first main surface 2A, a second main surface 2B opposite the first main surface 2A and side surfaces 2C, which connect the first and second main surfaces 2A, 2B.

[0044] The carrier element 2 comprises a carrier layer 4, which has a first depression 5 extending from a first main surface 4A of the carrier layer 4 in a direction of a second main surface 4B of the carrier layer 4 opposite the first main surface 4A and has a second depression 6 extending from the first main surface 4A in the direction of the second main surface 4B. In particular, the first and second depressions 5, 6 are through-holes completely penetrating the carrier layer 4. The carrier layer 4 further comprises a metal substrate 7 and an electrically insulating layer 8 on the whole metal substrate 7. Especially, the carrier layer 4 consists of the metal substrate 7 and the electrically insulating layer 8. The electrically insulating layer 8 is an anodization layer, which is made of a compound of the material of the metal substrate 7. Preferably, the metal substrate 7 comprises or consists of aluminium or aluminium alloys, and the electrically insulating layer 8 is an oxidized layer of aluminium or an aluminium alloy.

[0045] The carrier element 2 comprises a first electrically conductive filling component 9 arranged in the first depression 5 in a form-fitting manner and a second electrically conductive filling component 10 arranged in the second depression 6 in a form-fitting manner. The first and second electrically conductive filling components 9, 10 are each at least partly electrodeposited in the depressions 5, 6. Especially, the first filling component 9 serves as a heat sink. And the electrodeposition allows for an economic fabrication method of the heat sink. The first and second electrically conductive filling components 9, 10 comprise or consist of metal. Preferably, the filling components 9, 10 comprise or consist of copper. The filling components 9, 10 can be made of different or the same materials.

[0046] Preferably, the first and second filling components 9, 10 do not protrude over the first main surface 4A of the carrier layer 4. Especially, first surfaces 9A, 10A of the first and second filling components 9, 10 terminate flush with the first main surface 4A of the carrier layer 4. Moreover, the first and second filling components 9, 10 may not protrude over the second main surface 4B of the carrier layer 4. Especially, second surfaces 9B, 10B of the first and second filling components 9, 10 terminate flush with the second main surface 4B of the carrier layer 4. This integration of the heat sink into the carrier layer 4 allows for a compact and small package design.

[0047] Both the first and the second filling components 9, 10 have a lateral size S measured along a first lateral direction L which decreases discontinuously from the first main surface 4A to a center of the carrier element 2 and increases discontinuously from the center to the second main surface 4A. The filling components 9, 10 each comprise a second region 91 arranged between two first regions 90 in the vertical direction V, wherein one first region 90 is arranged at the first main surface 2A and another first region 90 is arranged at the second main surface 2B of the carrier element 2 and wherein the first regions 90 have a greater lateral size S than the second region 91. This structure of the filling components 9, 10 allows for good anchoring of the same within the carrier layer 4. Both the first and the second filling components 9, 10 may have a lateral size measured along a second lateral direction (not shown) running perpendicular to the vertical and first lateral directions V, L which is constant along the vertical direction V or may vary. The first and second regions 90, 91 may be cylinders or cuboids of different lateral sizes S.

[0048] The first and second filling components 9, 10 differ from each other in their lateral sizes S. In other words, the maximum lateral size S of the first filling component 9 is greater than the maximum lateral size S of the second filling component 10.

[0049] The electrically insulating layer 8 is arranged between the metal substrate 7 and the respective filling component 9, 10. Here, not only areas of the metal substrate 7 facing the first and second depressions 5, 6 are completely covered by the electrically insulating layer 8, but the whole metal substrate 7 is covered by the electrically insulating layer 8. The overall coverage of the metal substrate 7 by the electrically insulating layer 8 improves the corrosion resistance of the carrier layer 4.

[0050] The carrier element 2 comprises a structured cover layer 11, which overlays the first surfaces 9A, 10A and the second surfaces 9B, 10B of the first and second filling components 9, 10. Preferably, the cover layer 11 is a metal layer or metal layer sequence comprising or consisting of a metal like Au, Pd, Pt or Ni. For example, the cover layer 11 may comprise a layer sequence of Ni/Au, Ni/Pd/Au or Ni/Pd.

[0051] The semiconductor chip 3 is mounted on the first surface 9A of the first filling component 9, wherein the first surface 9A is arranged at a first main surface 2A of the carrier element 2. The first surface 9A laterally projects over the semiconductor chip 3. This has the advantage that the first filling component 9 works as a heatspreader which distributes the punctual heat of the semiconductor chip 3 over a larger area and thus provides for an effective cooling of the semiconductor chip 3. Moreover, the first filling component 9 is a first electric terminal of the semiconductor device 1 and the second filling component 10 is a second electric terminal of the semiconductor device 1.

[0052] The semiconductor chip 3 comprises a semiconductor body 12 having a first semiconductor region 13 and a second semiconductor region 15 and an active zone 14 for generating radiation during operation arranged between the first and second semiconductor regions 13, 15. Furthermore, the semiconductor body 12 has a first main area 12A and a second main area 12B opposite the first main area 12A. Preferably, the first semiconductor region 13 is a p-type semiconductor region and the second semiconductor region 15 is an n-type semiconductor region.

[0053] The semiconductor chip 3 comprises a first electrode 16 and a second electrode 17, which are provided for electrically contacting the semiconductor body 12, wherein the first electrode 16 forms a p-contact and the second electrode 17 forms an n-contact. The first electrode 16 is arranged on the first main area 12A of the semiconductor body 12 and the second electrode 17 is arranged on the second main area 12B of the semiconductor body 12, wherein the electrodes 16, 17 are electrically conductive layers. The second electrode 17 is electrically connected to the first filling component 9, and the first electrode 16 is electrically connected to the second filling component 10. Especially, the semiconductor device 1 is mechanically and electrically connected to the carrier element 2 by an attachment layer 18. Moreover, the first electrode 16 is electrically connected to the second filling component 10 by a wire bond 19.

[0054] FIG. 2 shows a second exemplary embodiment of a semiconductor device 1, which has a similar structure as the first exemplary embodiment. However, according to the second exemplary embodiment, the first regions 90 of the first filling component 9 have a greater vertical size H than the first regions 90 of the first filling component 9 according to the first exemplary embodiment. Moreover, according to the second exemplary embodiment, the second region 91 of the first filling component 9 has a smaller lateral size S than the second region 91 of the first filling component 9 according to the first exemplary embodiment.

[0055] Both embodiments provide for good heat spreading and show that, the smaller a vertical size H of the first region 90, the bigger is the lateral size S of the second region 91.

[0056] A method for producing a carrier element 2 or a semiconductor device 1 is described in connection with FIGS. 3 to 8.

[0057] First (see FIG. 3), a metal substrate 7 is provided. The metal substrate 7 has a cuboid shape and comprises a planar first main surface 7A and a planar second main surface 7B opposite the first main surface 7A as well as several side surfaces 7C.

[0058] Then (see FIG. 4), a first depression 5 and a second depression 6 are formed in the metal substrate 7 such that they completely penetrate the metal substrate 7 and are at least partly surrounded by the metal substrate 7. The first and second depressions 5, 6 are each formed with the lateral sizes S decreasing discontinuously from the first main surface 7A to the center of the metal substrate 7 and increasing discontinuously from the center of the metal substrate 7 to the second main surface 7B. The first and second depressions 5, 6 can be produced by punching or drilling the metal substrate 7.

[0059] Next (see FIG. 5), an electrically insulating layer 8 is produced on the whole metal substrate 7 by anodizing the metal substrate 7 in the depressions 5, 6 and at all surfaces 7A, 7B, 7C. For the anodization an aqueous solution containing, for example, sulfuric acid is applied at about room temperature to the depressions and on the surfaces 7A, 7B, 7C of the anodically charged metal substrate 7. The advantage of this process is that the lateral and vertical sizes of the depressions 5, 6 remain constant and are not influenced by the production of the electrically insulating layer 8. The metal substrate 7 and the electrically insulating layer 8 together form a carrier layer 4.

[0060] Afterwards (see FIG. 6), a first electrically conductive filling component 9 is produced in the first depression 5 in a form-fitting manner, wherein the electrically insulating layer 8 is arranged between the metal substrate 7 and the first filling component 9. And a second electrically conductive filling component 10 is produced in the second depression 6 in a form-fitting manner, wherein the electrically insulating layer 8 is arranged between the metal substrate 7 and the second filling component 10. In particular, the first and second filling components 9, 10 may be produced by an electroplating process. For example, producing the first and second filling components 9, 10 may involve a first step of producing a seed layer on the surface which laterally delimits the depressions 5, 6. The seed layer may be a metal layer which is sputtered on the respective surface. In a second step a metallization may be applied to the seed layer, by electrodeposition in an electroplating process.

[0061] Next (see FIG. 7), a structured cover layer 11 is produced, for example by electrolytic or electroless plating. Especially, the cover layer 11 is formed to overlay the first surfaces 9A, 10A of the first and second filling components 9, 10 and the second surfaces 9B, 10B of the first and second filling components 9, 10. The so produced element is a carrier element 2 suitable for a semiconductor device 1.

[0062] In order to produce a semiconductor device 1 (see FIG. 8), a carrier element 2 as described above is provided and a semiconductor chip 3 is mounted on the first surface 9A of the first filling component 9 by a die attach process, wherein an attachment layer 18 is used between the semiconductor chip 3 and the carrier element 2. A wire bonding process is carried out in order to electrically connect the first electrode 16 of the semiconductor chip 3 to the second filling component 10.

[0063] The scope of protection of the invention is not limited to the examples given hereinabove. The invention is embodied in each novel characteristic and each combination of characteristics, which particularly includes every combination of any features which are stated in the claims, even if this feature or this combination of features is not explicitly stated in the claims or in the examples.