Voltage reference circuit, voltage detector and voltage detector system

Abstract

A voltage detector (200) for monitoring an input signal and outputting a detection signal at an output when a voltage of the input signal meets a first threshold having: an input configured for receiving the input signal; a voltage reference circuit for receiving an input voltage and producing a reference voltage having a maximum value independent of the input voltage; and a trigger configured to compare the input signal and the reference voltage and to output a detection signal to the output when the voltage of the input signal reaches the first threshold. The voltage reference circuit comprises a reset input connected to either the input or the output and is configured to reduce the reference voltage when a predetermined reset signal is received. The voltage reference circuit may include: an input for receiving the input voltage; a first current controlling element (210), such as a diode, which allows current to flow as an increasing, non-linear function of voltage at least within a first range of voltages; a second current controlling element (240), such as a transistor, which allows current to flow as an increasing, non-linear function of voltage at least with a second range of voltages; and an output at which the output reference voltage is produced. The first current controlling element and the second current controlling element are connected in series between the input and a common reference, with the second current controlling element between the first current controlling element and a common reference, the output comprises a node between the two current controlling elements, the first and second range of voltages overlap and the second current controlling element is configured to vary the function by which it allows current to flow in dependence on the input voltage.

Claims

1. A voltage reference circuit for receiving an input and producing an output reference voltage having a maximum value independent of a voltage of the input, the voltage reference circuit comprising: an input for receiving the input voltage; a first current controlling element which allows current to flow as an increasing, non-linear function of voltage at least within a first range of voltages; a second current controlling element which allows current to flow as an increasing, non-linear function of voltage at least with a second range of voltages; and an output at which the output reference voltage is produced, wherein the first current controlling element and the second current controlling element are connected in series between the input and a common reference, with the second current controlling element between the first current controlling element and the common reference, the output comprises a node between the two current controlling elements, the first and second range of voltages overlap and the second current controlling element is configured to vary the function by which it allows current to flow in dependence on the input voltage; a reset input for receiving a reset signal; and a third current controlling element connected in series between the first current controlling element and the output, wherein the third current controlling element is configured to allow current to flow in dependence on a voltage received at the reset input.

2. A voltage reference circuit according to claim 1 wherein the second current controlling element has a control terminal connected to the input.

3. A voltage reference circuit as claimed in claim 1 wherein the reset input is connected to the input so that the third current controlling element is configured to allow current to flow in dependence on the input voltage.

4. A voltage reference circuit according to claim 1 wherein the third current controlling element has a control terminal connected to the reset input.

5. A voltage reference circuit according to claim 1 arranged to reduce the output reference voltage when a predetermined reset signal is received.

6. A voltage reference circuit according to claim 1 comprising a capacitance connected to the input via the first current controlling element.

7. A voltage reference circuit according to claim 1 comprising a bias-shifting element associated with the second current controlling element.

8. A voltage reference circuit according to claim 1 connected to a trigger configured to compare the input voltage with the output reference voltage and to output a detection signal when the voltage of the input meets a first threshold.

9. A voltage detector for monitoring an input signal and outputting a detection signal at an output when a voltage of the input signal meets a first threshold, the voltage detector comprising: an input configured for receiving the input signal; a voltage reference circuit for receiving an input voltage and producing a reference voltage having a maximum value independent of the input voltage; and a trigger configured to compare the input signal and the reference voltage and to output a detection signal to the output when the voltage of the input signal reaches the first threshold, wherein the voltage reference circuit comprises a reset input connected to either the input or the output and is configured to reduce the reference voltage when a predetermined reset signal is received.

10. A voltage detector according to claim 9 wherein the voltage reference circuit is according to claim 1.

11. A voltage detector according to claim 9 wherein the trigger is an inverter, the voltage reference circuit comprises a capacitance connected to the input via a first current controlling element, and the voltage reference circuit acts as a switch for selectively connecting an input of the inverter to the capacitance or to a common reference, wherein: the switch is operative to connect the input of the inverter to the capacitance during a period in which a voltage of the input signal rises from zero to the first threshold, such that no detection signal is output; the switch is operative to connect the input of the inverter to the common reference when the voltage of the input signal meets the first threshold, such that a detection signal is output while the voltage of the input signal is equal to or greater than the first threshold; and the switch is operative to connect the input of the inverter to the capacitance when the voltage of the input signal drops below a second threshold, such that no detection signal is output.

12. A voltage detector according to claim 9 configured to stop outputting a detection signal when a voltage of the input falls below a second threshold which is lower than the first threshold.

13. A voltage detector system for monitoring an input signal and outputting a detection signal when the voltage of the input signal meets a threshold, the voltage detector system comprising: a first voltage detector having a first reference generator and an input for receiving the input signal and an output for outputting a detection signal, wherein the first voltage detector is configured to output the detection signal when the voltage of the input signal meets a first rising input voltage threshold; a second voltage detector having a second reference generator and an input for receiving the input signal and an output for outputting a detection signal, wherein the second voltage detector is configured to output the detection signal when the voltage of the input signal meets a second rising input voltage threshold which is higher than the first rising input voltage threshold, wherein the output of the second voltage detector controls a connection between the input signal and the input of the first voltage detector such that when the voltage of the input signal meets the second rising input voltage threshold the connection between the input signal and input of the first voltage detector is restricted or disconnected.

14. A voltage detector system according to claim 13 further comprising: a third voltage detector having a third reference generator and an input for receiving the input signal and an output for outputting a detection signal, wherein the third voltage detector is configured to output the detection signal when the voltage of the input signal meets a third rising input voltage threshold which is higher than both the first rising input voltage threshold and the second rising input voltage threshold, wherein the output of the third voltage detector controls a connection between the input signal and the input of the second voltage detector such that when the voltage of the input signal meets the third rising input voltage threshold the connection between the input signal and the input of the second voltage detector is restricted or disconnected.

15. A voltage detector system according to claim 14, wherein the third voltage detector is configured to cease outputting a detection signal when the voltage of the input signal meets a third falling input voltage threshold, wherein the third falling input voltage threshold is lower than the third rising input voltage threshold.

16. A voltage detector system according to claim 14 wherein the first, second and/or third voltage detector comprises a voltage detector according to claim 9.

17. A voltage detector system according to claim 13, wherein the first voltage detector is configured to cease outputting a detection signal when the voltage of the input signal meets a first falling input voltage threshold, wherein the first falling input voltage threshold is lower than the first rising input voltage threshold.

18. A voltage detector system according to claim 13, wherein the second voltage detector is configured to cease outputting a detection signal when the voltage of the input signal meets a second falling input voltage threshold, wherein the second falling input voltage threshold is lower than the second rising input voltage threshold.

19. A voltage detector system according to claim 13 further comprising an open drain output stage, the open drain output stage comprising a plurality of MOSFET devices, each MOSFET device having: a gate terminal connected to the output of a respective one of the voltage detectors; a source terminal connected to a common reference; and a drain terminal connected to an output terminal of the open drain output stage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Embodiments of the invention will now be described, strictly by way of example only, with reference to the accompanying drawings, of which:

(2) FIG. 1 is a schematic representation of a sensor system that is powered by intermittent sources;

(3) FIG. 2 illustrates the operation of a commercially available voltage detector as used in the circuit of FIG. 1;

(4) FIG. 3 illustrates the operation of a basic power on reset (POR) pulse generator circuit;

(5) FIG. 4 illustrates the ideal behaviour of a POR circuit;

(6) FIG. 5 is a schematic representation of a system architecture of a system incorporating a plurality of voltage detectors;

(7) FIG. 6 is a timing diagram illustrating the operation of the system of FIG. 5;

(8) FIG. 7 is a schematic representation of a power-gating circuit suitable for use in the architecture of FIG. 5;

(9) FIG. 8 is a schematic representation of a voltage reference circuit that forms a part of the architecture of FIG. 5;

(10) FIG. 9 is a functional block diagram of a voltage detector used in the system of FIG. 5;

(11) FIG. 10 is a conceptual schematic diagram illustrating an implementation of the subthreshold voltage reference of the voltage detector of FIG. 9;

(12) FIG. 11 is a conceptual schematic diagram illustrating a transistor implementation of the low voltage detector illustrated in FIG. 9;

(13) FIGS. 12 to 14 are timing diagrams illustrating the operation of the circuit of FIG. 11;

(14) FIG. 15 is a functional block diagram illustrating aspects of the operation of the voltage detector illustrated in FIG. 9;

(15) FIG. 16 is a schematic diagram showing the design of a high voltage-range voltage detector for use in the system of FIG. 5;

(16) FIG. 17 is a graph illustrating parameters of devices for use in implementing the voltage detector system disclosed herein;

(17) FIG. 18 is a schematic diagram showing the design of a low voltage-range voltage detector for use in the system of FIG. 5;

(18) FIG. 19 is a schematic diagram showing the design of a medium voltage-range voltage detector for use in the system of FIG. 5; and

(19) FIG. 20 provides a legend for the transistor symbols used in FIGS. 16, 18 and 19.

DESCRIPTION OF THE EMBODIMENTS

(20) FIG. 5 illustrates a voltage detection system which combines all the desired properties of voltage detectors, namely high maximum input voltage, a low voltage detection threshold and low quiescent power consumption. The system, shown generally at 100 in FIG. 5, includes a power gating stage 120, a voltage detection stage 140 and an output stage 160.

(21) The voltage detection stage 140 includes a first voltage detector 142 which is configured to detect input voltages in a high voltage range (e.g. in the range 2.8 volts to 20 volts), a second voltage detector 144 which is configured to detect input voltages in a medium voltage range (e.g. 0.6 volts to 2.8 volts) and a third voltage detector 146 which is configured to detect input voltages in a low voltage range (e.g. 0.45 volts to 0.6 volts). This arrangement of three voltage detectors ensures that the voltage detection system 100 is able to operate in a wide input voltage range, therefore facilitating the capture of energy from pulses with a wide power range.

(22) The power gating stage 120 is configured to prevent potentially damaging input voltages from reaching the second and third voltage detectors 144, 146, and is arranged such that the first voltage detector 142 gates the second and third voltage detectors 144, 146 and the second voltage detector 144 gates the third voltage detector 146. As can be seen in FIG. 5, the voltage input V.sub.IN of the system 100 is connected to an input V.sub.IN(H) of the first voltage detector 142. An output V.sub.OUT(H) of the first voltage detector 142 is connected to the gate terminal of a first P-channel MOSFET 122. The source terminal of the first P-channel MOSFET is connected to the voltage input V.sub.IN and the drain terminal of the first P-channel MOSFET 122 is connected to an input V.sub.IN(M) of the second voltage detector 144, and, via a second P-channel MOSFET 124, to an input V.sub.IN(L) of the third voltage detector 146.

(23) When the first voltage detector 142 detects an input voltage in the high voltage range, its output V.sub.OUT(H) goes high, causing the first P-channel MOSFET 122 to switch off, thereby restricting or preventing the input voltage from reaching the second voltage detector 144 or the third voltage detector 146.

(24) Similarly, the gate terminal of the second P-channel MOSFET 124 is connected to an output V.sub.OUT(m) of the second voltage detector 144, such that when the second voltage detector 144 detects an input voltage in the medium voltage range, its output V.sub.OUT(M) goes high, causing the second P-channel MOSFET 124 to switch off, thereby restricting or preventing the input voltage from reaching the third voltage detector 146.

(25) The output stage 160 of the voltage detection system 100 includes (in the illustrated example) first, second and third N-channel MOSFETS 162, 164, 166. The gate terminal of the first N-channel MOSFET 162 is connected to the output V.sub.OUT(H) of the first voltage detector 142, whilst the gate terminal of the second N-channel MOSFET 164 is connected to the output V.sub.OUT(M) of the second voltage detector 144 and the output of the third N-channel MOSFET 166 is connected to the output V.sub.OUT(L) of the third voltage detector 146.

(26) The drain terminals of the first, second and third N-channel MOSFETs 162, 164, 166 are all connected to an open-drain output terminal V.sub.OD of the output stage 160, whilst the source terminals of the first, second and third N-channel MOSFETs 162, 164, 166 are all connected to ground. Accordingly, if any one of the first, second or third voltage detectors 142, 144, 146 is triggered, the open drain output V.sub.OD of the output stage 160 will be activated.

(27) FIG. 6 is a timing diagram illustrating the operation of the circuit of FIG. 5. The input voltage V.sub.IN is shown as a trapezoidal pulse. As the rising edge of this pulse reaches the voltage detection threshold of the third (low voltage range) voltage detector 146, the third voltage detector 146 turns the third N-channel MOSFET 166 on, activating the system's output V.sub.OD. When the input voltage V.sub.IN reaches the voltage detection threshold of the second (medium voltage range) voltage detector 144, the second voltage detector 144 switches on the second N-channel MOSFET 164, and power-gates off the third voltage detector 146, thus protecting it from a further rise in V.sub.IN, and causing the third N-channel MOSFET 166 to be switched off. As V.sub.IN reaches the voltage detection threshold of the first (high voltage range) voltage detector 142, the first N-channel MOSFET 162 is switched on, and both the second and third voltage detectors 144, 146 are disconnected from the input (or at least the connection restricted), resulting in the turning off of the second N-channel MOSFET 164. The first voltage detector 142 remains active until the input voltage drops below its voltage detection threshold, which leads to the second voltage detector 144 being powered on. A further fall in the input voltage activates the third voltage detector 146.

(28) The thresholds at which the voltage detectors 142, 144, 146 switch on in response to a rising input voltage may be different from (higher than) the thresholds at which the voltage detectors 142, 144, 146 switch off in response to a falling input voltage, in order to provide hysteresis and thus avoid system oscillation. The overall result is a continuous activation of the open-drain output V.sub.OD for the duration of the input pulse. To ensure seamless operation of the voltage detection system 100, the threshold voltage of each MOSFET device 162, 164, 166 should be lower than the detection thresholds at which the respective voltage detectors 142, 144, 146 switch on in response to a rising input voltage and the thresholds at which the respective voltage detectors 142, 144, 146 switch off in response to a falling input voltage.

(29) This illustrates the reason for using an open-drain output. When activated, the voltage outputs V.sub.OUT(H), V.sub.OUT(M) and V.sub.OUT(L) of the voltage detectors 142, 144, 146 are at the same potential as their corresponding inputs V.sub.IN(H), V.sub.IN(M) and V.sub.IN(L)). Since the voltage detector system 100 will interface to other CMOS devices with much lower maximum allowable voltages, V.sub.OUT(H) and V.sub.OUT(M) cannot be used as the output of the overall system. The open drain output stage allows the voltage detector system 100 to output a signal that is usable by, and not damaging to, an external device.

(30) FIG. 6 also illustrates the profile of the total quiescent current I.sub.IN of the voltage detector system 100. I.sub.IN is zero when the input voltage V.sub.IN is zero, and on a rising input voltage the current increases from 42 pA at 0.2V (below the voltage detection threshold of the third voltage detector 146) to 83 pA at V.sub.IN=1V (above the detection threshold of the second voltage detector 144), and to around 236 pA at V.sub.IN=5V (above the detection threshold of the first voltage detector 142), with current surges occurring at the activation points of each of the three voltage detectors 142, 144, 146. The measured total energy loss per transition caused by static current when an input voltage rises from 0 to 2.8V, a voltage slightly higher than the high detection threshold (2.8V) with two typical gradients of 1V/s and 100V/s respectively are 788 pJ and 7.9 pJ respectively. This is lower than prior art voltage detection circuits, which contain circuits that, for a given rail voltage, continuously consume quiescent current. An alternative version of the voltage detector system 100 in which the third voltage detector 144 is disabled draws 1.2 pA at 0.2V, around 6 pA at 1V and 111 pA at 5V. Its total energy consumption at 1V/s and 100V/s transition from 0 to 2.8V of the input voltage is 229 pJ and 23 pJ respectively.

(31) FIG. 7 is a schematic representation of a power-gating circuit 120 suitable for use in the voltage detection system 100 of FIG. 5. The power-gating transistor 122 should be a medium-gate-oxide (5.5 V breakdown) PMOS transistor because its source-gate voltage can be as high as 2.8 V (corresponding to the threshold of the first voltage detector 142) before its gate-drive signal goes high. By contrast, the power-gating transistor 124 can be a thin-gate-oxide PMOS transistor because its source-gate voltage does not exceed 0.6 V (corresponding to the threshold of the second voltage detector 144) and its low gate-threshold voltage helps the third (low voltage range) detector 146 start to operate at a low input voltage.

(32) Ideally, the input voltage V.sub.IN(L) of the third detector 146 will drop after the transistor 122 is switched off for protecting this detector. However, in some thin-gate-oxide CMOS process technologies, the leakage current through the transistor 124 (when OFF) can be sufficiently high so that V.sub.IN(L) can continue to rise and follow the input voltage V.sub.IN(M) of the second (medium voltage range) detector 144. This may cause overvoltage damage to the third detector 146 especially when V.sub.IN(M) has a slow voltage gradient.

(33) A simple but efficient protection solution is to add a route to ground (or a common reference) for the leakage current. In the power gating circuit 120 of FIG. 7, this is implemented with a diode-connected NMOS transistor 126 (labelled MN0), which is a thick-gate-oxide (high gate-threshold) transistor. When the second voltage detector 144 output V.sub.OUT(M) goes high, which switches off the transistor 124 (zero gate-source voltage), the two transistors 124 and 126 are configured as an ultra-low-power two-transistor voltage reference consisting of two stacked transistors 124, 126 with different gate thresholds V.sub.TH as shown in FIG. 8. The first one 410 of the stacked transistors has a lower V.sub.TH and zero gate-source voltage, whilst a second one 420 of the stacked transistors has higher V.sub.TH and is configured as a diode-connected transistor. The reference circuit 400 clamps V.sub.IN(L) to a fixed voltage (seen as a voltage plateau in the graph of FIG. 7) while consuming pico-amperes current only, and by adjusting the W/L ratios of transistors 124 and 126, V.sub.IN(L) can be set at a safe voltage for the third voltage detector 146. Before transistor 124 is switched off and while the third voltage detector 146 is operating normally, transistor 126 draws negligible current from the input V.sub.IN(L) because its gate-threshold is much higher than V.sub.IN(L) and thus this transistor operates in its deep subthreshold region.

(34) FIG. 9 is a schematic block diagram illustrating the desired functionality of the voltage detectors 142, 144, 146 used in the system 100.

(35) As can be seen from FIG. 9, each of the voltage detectors 142, 144, 146 comprises a subthreshold voltage reference, a trigger circuit and optional output buffers. The subthreshold voltage reference seeks to generate a fixed output V.sub.REF, in this example 0.22 V. The trigger comprises an inverter with input V.sub.REF and its supply the varying detector input voltage V.sub.IN. The trigger switches its output to high as the supply voltage V.sub.IN reaches the detection threshold V.sub.TH. Its input V.sub.REF is sufficiently low to ensure that the trigger is still in subthreshold mode when it switches.

(36) The optional output buffers sharpen the response of the detector and feed the output back to the Reset input of the subthreshold voltage reference. On triggering the detector, the low-to-high transition of the output activates the Reset input of the subthreshold voltage reference. This has three beneficial effects. First, it cuts off or at least substantially reduces the static quiescent current draw of the subthreshold voltage reference. Second, the reference output is pulled to the common reference, which virtually eliminates static current in the trigger, as its input is no longer at an intermediate voltage. Third, with a lower (or grounded) input, the trigger switches its output back at a lower V.sub.IN threshold, which inherently provides the detector with hysteresis.

(37) FIG. 10 is an illustrative circuit implementation of the functionality of the subthreshold voltage reference in FIG. 9. It comprises a first current controlling element, diode D, and a capacitance C connected in series between the input terminal and a common reference V.sub.COM such that the capacitance is charged (though the diode) by the input signal. The capacitance may be a parasitic capacitance (e.g. of a transistor gate), or may be provided by a separate component such as a capacitor. The common reference may be ground.

(38) The source of a PMOS transistor 230 is connected to a node between the diode D and capacitance C. Its drain is connected to the drain of an NMOS transistor 240, with its source connected to a common reference. A node in the connection between the drain of the PMOS transistor and the NMOS transistor provides the reference voltage output V.sub.REF of the reference generator. The gate of the PMOS transistor provides the reset input to the reference generator. The gate of the NMOS transistor is connected (directly) to the input terminal.

(39) In operation, with a rising input voltage V.sub.IN, the voltage at the node between the diode D and capacitance C (V.sub.C) follows V.sub.IN minus the diode forward drop voltage across the diode D. With no, or a low, voltage at the Reset input the PMOS transistor 230 is on more strongly than the NMOS transistor 240 so V.sub.REF follows V.sub.C closely.

(40) As V.sub.IN rises further, being connected to the gate of the NMOS transistor 240, it increases the (leakage) current in the NMOS transistor 240 which begins to draw an increased current resulting in V.sub.REF and V.sub.C reaching a plateau and ceasing to rise.

(41) If an input is provided to the Reset terminal of sufficient voltage the PMOS transistor 230 is turned off, causing V.sub.REF to be shorted to the common reference via the NMOS transistor and eliminating or significantly reducing the static current path in the voltage reference, effectively putting it into a low power mode.

(42) The two transistors in the voltage reference serve two functions, depending on the state of the reference generator. Prior to resetting the NMOS transistor 240 operates in subthreshold and thus helps generate a reference voltage together with the diode D. When in subthreshold both components allow current to flow generally exponentially with voltage. After resetting the PMOS transistor 230 power-gates off the quiescent current, and so helps reset the reference voltage to zero (or a common reference voltage).

(43) FIG. 11 is an illustrative circuit implementation 200 of the functionality of the circuit shown in FIG. 9 with the voltage reference circuit implemented as shown in FIG. 10 save that, in this implementation, the diode D of FIG. 10 is a diode-connected transistor 210. As indicated above, the purpose of the diode D is simply to control current flow and so provide a voltage drop between V.sub.IN and V.sub.C. A diode (or diode-connected transistor 210) offers a convenient way of providing a voltage drop, but it will be appreciated by those skilled in the art that any other component or circuit that provides an appropriate voltage drop could equally be employed. The capacitance of FIG. 10 is implemented by a capacitor 220 (though this need not be a separate component; as indicated above, the capacitance may be provided by parasitic capacitance in the circuit 200). The trigger is an inverter implemented by a transistor pair consisting of a PMOS transistor 250 and an NMOS transistor 260. The output of the inverter V.sub.OUT is connected to the gate of the PMOS transistor 230 which forms the reset input of the voltage reference circuit of which it forms a part.

(44) The operation of the circuit of FIG. 11 will now be described with reference to FIGS. 12 to 14, which are timing diagrams illustrating the operation of the circuit of FIG. 11. FIGS. 13 and 14 show expanded views of sections of FIG. 12. FIG. 13 shows the section between times a and b and FIG. 14 the section between times c and d, of FIG. 12, and show detail around the triggering of the inverter for rising and falling input voltages respectively.

(45) The input voltage pulse V.sub.IN from an external voltage source V.sub.IN is assumed to follow a trapezoidal profile, as shown in FIG. 12. The capacitance of the capacitor 220 is two or more orders of magnitude lower than the source's parasitic capacitance. The capacitor is charged via the diode-connected transistor 210, resulting in V.sub.C (the voltage at the node between the transistor 210 and the capacitor 220) generally being a diode forward voltage drop V.sub.Fwd1 below V.sub.IN during the rise and the plateau of the input voltage. During the fall of V.sub.IN, the capacitor 220 discharges into the V.sub.IN rail through the antiparallel parasitic diode of the transistor 210, resulting in V.sub.C generally being a diode forward voltage drop V.sub.Fwd2 above V.sub.IN.

(46) At the start of the pulse, V.sub.OUT is zero, and therefore the PMOS transistor 230 that is controlled by V.sub.OUT connects V.sub.C through to the input VB of the inverter formed by transistors 250, 260, forcing V.sub.REF to follow V.sub.C. As discussed above, as V.sub.IN rises further the NMOS transistor 240 begins to draw increased current resulting in V.sub.REF reaching a plateau (this plateau being visible in FIG. 13) and ceasing to rise and thus determining the voltage threshold at which the trigger circuit switches.

(47) The trigger is an inverter whose input is V.sub.REF. The supply voltage V.sub.IN at which the inverter flips its output high is the detection threshold V.sub.TH of the detector. In the described implementation, on a rising V.sub.IN, V.sub.REF is 0.22 V, providing a detection threshold of 0.46 V. Upon triggering, V.sub.REF is reset to V.sub.COM (which may be zero or ground), which lowers (to 0.29 V where V.sub.COM is zero) the threshold at which the trigger flips back, thereby providing hysteresis.

(48) Due to the low V.sub.REF, the trigger circuit operates in subthreshold prior to triggering. The topology of the trigger stage uses PMOS transistor 250 as a common-gate amplifier, whose gate bias is V.sub.REF, whose input is V.sub.IN and whose active load is NMOS transistor 260 due to its gate being biased to V.sub.REF. The trigger output voltage is also the V.sub.DS of the NMOS transistor 260. Therefore, as the V.sub.DS of 260 exceeds 4.sub.VT (100 mV=4thermal voltage), this transistor enters saturation. Now, with both transistors 250 and 260 in saturation, the increased output impedance results in a large gain of the amplifier, seen by an increase in the gradient of the trigger output voltage. This increase turns off the PMOS transistor 230 forming part of the voltage reference with the result that very soon after the trigger output voltage begins to increase the subthreshold voltage reference circuit begins to reset, and this positive feedback leads to a sharp rise in output voltage. Also, as V.sub.IN reaches the gate threshold V.sub.thS2 of the transistor 240, V.sub.REF is pulled to the common reference, also causing V.sub.out to go high, and minimising leakage through the inverter.

(49) V.sub.out then follows the rail voltage V.sub.IN of the inverter.

(50) On the falling edge the gate voltage of transistor 240 drops, weakening its driving strength. When V.sub.IN reaches the threshold V.sub.thS2 of the transistor 240, it loses capacity to hold V.sub.REF low. Subthreshold leakage through the transistor 230 (stemming from charge stored by the capacitance C) causes V.sub.REF to rise, and therefore V.sub.OUT to begin falling. As V.sub.REF reaches 100 mV transistor 230 is conducting enough current to pull up V.sub.REF rapidly to V.sub.C. This process is accelerated by positive feedback from the output. Once V.sub.OUT has fallen to V.sub.CV.sub.th230 (i.e. V.sub.cthe threshold of the transistor 230), the transistor 230 turns on, pulling V.sub.REF up to beyond the rail voltage V.sub.IN, which in turn causes the inverter to pull V.sub.OUT to the common reference. Once the pulse is over, the remaining charge in the capacitor 220 leaks to the common reference through the transistor 210. In this manner a hysteresis is created between the rising and falling detection thresholds.

(51) The steady-state current consumption of the voltage detector circuit of FIG. 11 is reduced in comparison to prior art systems by means of two features. First, the inverter's input is always pulled either high or low via the two-way switch consisting of the transistors 230, 240, which reduces the inverter's static current leakage (shown as I.sub.inv in FIG. 11) flowing through the transistors 250, 260. Second, the rise and fall input voltage thresholds (i.e. the voltage threshold at which the voltage detector switches on the open-drain output stage 160 in response to a rising input voltage and the voltage threshold at which the voltage detector switches off the open-drain output stage 160 in response to a falling input voltage) are provided by a circuit that draws negligible current in steady state. The rise threshold is a function of the gate voltage threshold of the NMOS transistor 240. The fall threshold is a function of the device parameters of the transistors 230, 240, 250 and 260.

(52) FIG. 15 is an alternate schematic block diagram of the voltage detector of FIG. 9, without the optional buffers, which illustrates an aspect of the operation of the detector. Here, as with FIG. 9, the subthreshold voltage reference is implemented by a diode D, and a capacitance C connected in series between the input terminal and a common reference such that the capacitance is charged (though the diode) by the input signal. The capacitance may be a parasitic capacitance (e.g. of a transistor gate of the switch), or may be provided by a separate component such as a capacitor. The difference to FIG. 9 is that the two transistors 230 and 240 are visualised as a switch S.

(53) The operation of the switch S is such that the input of the inverter is connected to a common reference (or another low-voltage source suitable for causing the inverter to output a voltage that is sufficiently high as to switch on the open-drain output 160) when the input voltage V.sub.IN to the voltage detector system 100 is greater than a voltage V.sub.thN, which is the voltage detection threshold at which the voltage detectors 144, 146 switch on the open-drain output 160 in response to a rising input voltage. The input of the inverter is connected to the node between the voltage reducing element and the capacitance during a period in which the input voltage rises from 0 to V.sub.thN, and when the output voltage V.sub.OUT of the voltage detector 144, 146 is less than a voltage V.sub.CV.sub.thP, where V.sub.C is the voltage across the capacitance and V.sub.thP is a positive value.

(54) The second and third voltage detectors 144, 146 both operate in the manner described above in relation to FIGS. 9 to 15, only that the thresholds are lower for the third voltage detector 146 than the second voltage detector 144, and the plateau is lower while the third voltage detector 146 is power-gated off by the higher-voltage second voltage detector 144. Assuming the transient current surges during the switching events are small, and since there is no static current flow during the detection process, this architecture provides a low power consumption.

(55) The first voltage detector 142 may have the same topology as the second and third voltage detectors 144, 146. Alternatively, the first voltage detector 142 could be parametrically redesigned to trade off speed for reduced static power consumption, since the first voltage detector 142 experiences the highest voltage of all detector levels.

(56) However, a further alternative arrangement, which is a conceptual variant of the second and third detectors, may be employed in the first voltage detector 142, as will now be described with reference to FIG. 16, which is a schematic representation of the first (high voltage range) voltage detector 142, with the relevant design parameters (component values and width/length ratios of the transistors used in the circuit) shown.

(57) The first voltage detector 142 operates as described above in relation to the circuits of FIGS. 11 and 15, with two differences. First, the transistor, which selectively connects the input of the inverter to the capacitance is not controlled by the output signal V.sub.Out, but is instead controlled by the input signal V.sub.in. In FIG. 16, this is seen by the gate of transistor 1432 being connected to the V.sub.in rail. Second, transistor 1432 is connected in series with a voltage reducing element (represented in FIG. 16 by a diode-connected transistor 1434), which shifts the potential relative to the common reference at which the gate of transistor 1432 switches.

(58) Referring back to the schematic representation of FIG. 11, assume that the gate threshold voltage of PMOS transistor 250 is a few hundreds of millivolts higher than the gate threshold of the NMOS switch 240. The aim is to stop an unwanted current path through transistors 210, 230 and 240 from occurring. This short circuit occurs on a rising V.sub.IN, starting at the time when transistor 240 switches on and pulls V.sub.REF down. At this point V.sub.IN is not yet high enough for V.sub.INV.sub.REF to have equalled the gate threshold of transistor 250. Therefore V.sub.Out is still low, and thus transistor 230 still on. This short circuit is only removed once 230 turns off.

(59) Referring again to FIG. 16, the first modification is that transistor 1426, which corresponds to the NMOS switch 230 of FIG. 11, is now controlled by the detector input V.sub.in instead of the inverter output V.sub.OUT. This prevents the occurrence of the short-circuit path through transistors 210, 230, and 240 in FIG. 11, by ensuring that transistor 230 is off all the time. The equivalent of transistor 230 of FIG. 11 in the arrangement shown in FIG. 16 is transistor 1426, which is now controlled by V.sub.in rather than V.sub.OUT as in the lower voltage-level detectors 144, 146, which keeps transistor 1426 off because it has a negative source-gate voltage. However, V.sub.REF does need to rise and follow V.sub.IN for correct operation. Therefore, transistor 1426 is designed with a large W/L ratio 50/0.2, in order to provide sufficient leakage current I.sub.leak to charge the node V.sub.REF in the initial phase of a V.sub.IN rise, as illustrated in FIG. 12 (before t.sub.1). This ensures that the inverter output V.sub.OUT(H) is initially held low as the detector input V.sub.in rises from 0V. Careful design ensures that the equivalent resistance of transistor 1426 is high enough to sufficiently limit the charging current.

(60) The second modification to counteract large gate-threshold differences, e.g. between the NMOS transistor 1432 and the PMOS transistor 1428, is the addition of the diode-connected transistor 1434. The diode-connected transistor 1434 acts as a bias-shifting element, by adding a small bias V.sub.d to the source terminal of the transistor 1432, thus raising the input voltage level at which transistor 1432 pulls V.sub.REF down. This reduces the aforementioned time during which a short-circuit path through 1422, 1426, and 1432 can occur. This speeds up the pulling-up of the inverter output V.sub.OUT(H), since V.sub.in is roughly one gate-threshold (of transistor 1434) higher by the time transistor 1432 turns transistor PMOS 1428 on. This determines the detection threshold of the first (high voltage range) detector 142. This threshold can be increased by adding more diode-connected transistors in series with the NMOS transistor 1432.

(61) Each of the detectors 142, 144, 146 must only trigger when a rising Vin is high enough to actually be able to switch the respective output open-drain transistor. Equally, a falling Vin must trigger the detectors 142, 144, 146 for which the respective open drain transistors are still on.

(62) During an input voltage pulse, the three open-drain output transistors 162, 164, 166 (FIG. 5) need to operate seamlessly to avoid any dead time in which none of the open drain output transistors are on. Seamless operation is achieved by setting both the rising and falling detection thresholds of each internal detector to exceed the gate threshold voltages of their respective open-drain output transistors: both the rising and falling thresholds of the first detector 142 are higher than the gate threshold voltage of the output transistor 162; both the rising and falling thresholds of the second detector 144 are higher than the gate threshold voltage of the output transistor 164; both the rising and falling thresholds of the second detector 146 are higher than the gate threshold voltage of the output transistor 166.

(63) At the rising edge of the input, these parameter settings prevent, for instance, the second detector 144 output from being pulled up to an input voltage that is lower than the gate-threshold of the open-drain transistor 164 when this detector triggers; at this point, the open-drain transistor 164 is still not switched on, but the power-gating transistor 124 and hence the third detector 146 has been switched off, which results in dead time between the transistors 166 and 164. At the falling edge of the input, these parameter settings prevent, for instance, the second detector 144 output from going low too late while the input voltage has dropped below the gate-threshold of the open-drain transistor 164; at this point, the power-gating transistor 124 and hence the third detector 146 is switched on late after the open-drain transistor 164 has been switched off, which results again in dead time between the transistors 166 and 164. Similarly, these parameters avoid undesired switching between the first and second detector 142 and 144, which eliminates dead time between the transistors 162 and 164.

(64) The three-level detector architecture of FIG. 5 places a number of demands on the fabrication process. These are illustrated in FIG. 17, which shows the nominal gate threshold and device voltage ratings of transistors chosen for the third (low voltage range), second (medium voltage range), and first (high voltage range) voltage detectors 146, 144, 142.

(65) There are a number of reasons for choosing these transistor variants. The detector system 100 cannot be designed with only low threshold, 20 V devices of the kind indicated by the bottom-right circle in FIG. 17, as the maximum allowed voltage on the low-threshold gate is less than 5 V. In principle, the detector system 100 could be designed with 20 V devices using all thresholds, however the die size would be significantly larger, and the quiescent current would increase. Equally, the detector could be designed with the three devices shown as filled circles in FIG. 17, however the static and dynamic power consumption would increase. Therefore, in addition to these three devices, the design described here uses the other two devices enclosed by the dashed lines. The reason that three device voltage ratings are required, and why a voltage detector for medium range voltages is needed, is that the absolute maximum gate voltage of the lowest threshold gates is below the gate threshold voltage of the 20 V devices. Without a voltage detector for medium range voltages detector there would be an input voltage range that is destructive to the low threshold transistors' gates, but not able to switch the high threshold transistors to trigger a protection circuit.

(66) The design of the second and third voltage detectors, 144, 146 will now be described, with reference to FIGS. 18 and 19, and to FIG. 20, which provides a legend of transistor symbols used in used in FIGS. 16, 18 and 19 giving transistor gate threshold options and maximum voltage ratings for an example HV CMOS fabrication process.

(67) FIG. 18 is a schematic diagram showing the design of the third (low voltage range) voltage detector 146 with the relevant design parameters (component values and width/length ratios of the transistors used in the circuit). The operation of the third voltage detector 146 is as described above in relation to the circuit of FIG. 11. The circuit of FIG. 18 differs from that of FIG. 11 only by the presence of two additional buffers made up of pairs of transistors in the output stage.

(68) Thus, as can be seen in FIG. 18, the third voltage detector 146 includes a diode-connected transistor 1462 (also labelled MP3 in FIG. 18) having a width/length ratio of 1.5/0.38 connected in series with a capacitor 1464 having a value of 1.7 picofarads between the input terminal of the third voltage detector 146 and a the common reference terminal of the third voltage detector 146.

(69) A node V.sub.C at the connection between the transistor 1462 and the capacitor 1464 connects to the drain terminal of a PMOS transistor 1466 (also labelled MP4 in FIG. 18). As shown, this transistor has a width/length ratio of 4/0.18. The gate terminal of the transistor 1466 is connected to an output V.sub.OUT(L) of the third voltage detector 146, whilst the source terminal of the transistor 1466 is connected to a node V.sub.REF which connects together the gate terminals of a PMOS transistor 1468 (labelled MP5, having a width/length ratio of 0.4/0.2) and an NMOS transistor 1470 (labelled MN6, having a W/L ratio of 2/0.2) which together form an inverter.

(70) A further NMOS transistor 1472 (labelled MN5, having a W/L ratio of 1/1) is provided, to pull the gate terminals of each of the transistors 1468, 1470 to the common reference when the input voltage is above the V.sub.thN threshold. Thus, the gate terminal of the transistor 1472 is connected to the input V.sub.IN of the third voltage detector 146, whilst its source terminal is connected to the common reference and its drain terminal is connected to the gate terminals of the transistors 1468, 1470.

(71) As indicated above, the transistors 1468, 1470 form an inverter, whose output provides, via first and second additional output buffers (the first output buffer being formed of a transistor pair comprising a PMOS transistor 1474 and an NMOS transistor 1476 connected so as to form an inverter and the second output buffer each formed by a transistor pair comprising a PMOS transistor 1478 and an NMOS transistor 1480 connected so as to form an inverter), the output V.sub.OUT(L) of the third voltage detector 146.

(72) The detection threshold of the voltage detector 146 illustrated in FIG. 18 is defined by the gate threshold voltage of the transistor 1472. The transistors 1466 and 1472 are scaled (transistor 1466 has a greater width/length ratio than transistor 1472) such that on a rising input voltage pulse when the output V.sub.OUT(L) is zero and both devices are in the subthreshold region, the transistor 1466 remains stronger for a while in order to allow V.sub.REF to rise. The threshold could be lowered by using a low-threshold device here, however this would require a much longer channel length in order to obtain the correct switch-over between transistor 1466 (on at the onset of an input pulse) and transistor 1472 (off at the start of a pulse). Transistors 1470 and 1468 (MN6 and MP5) are scaled (transistor 1470 has a greater W/L ratio than transistor 1468) so that transistor 1470 is strong enough to hold the output V.sub.OUT(L) low until V.sub.REF starts to decrease, whilst still allowing the output to be pulled up cleanly as soon as V.sub.IN reaches the gate threshold of transistor 1472. This is important in order to minimise the switching duration of the third voltage detector 146 and thus minimise dynamic current. The result is a rapid turn-on of the open-drain transistor 166 (FIG. 5). The output's two-stage buffer (formed by the transistor pairs 1474, 1476 and 1478, 1480) has a taper factor so that it can drive the large open-drain transistor 166 (whose width/length ratio W/L=50 m/2 m). The diode connected transistor 1462 (labelled MP3 in FIG. 18) is sized to allow V.sub.C to follow V.sub.IN and is a function of the value of the capacitor 1464, which in turn requires a minimum capacitance in order that leakage through the transistor 1466 does not discharge it during a typical input pulse.

(73) FIG. 19 is a schematic representation of the second (medium voltage range) voltage detector 144, again with the relevant design parameters (component values and width/length ratios of the transistors used in the circuit) shown. The operation of the second voltage detector 144 is as described above in relation to the circuit of FIG. 11. Again, the circuit of FIG. 19 differs from that of FIG. 11 only by the presence of two additional buffers made up of pairs of transistors in the output stage.

(74) The second (medium voltage range) voltage detector 144 of FIG. 19 is designed in the same manner as the third voltage detector 146 of FIG. 18. The capacitance 1444 (labelled C2 in FIG. 19) is however larger (at 3.2 picofarads) than the capacitance 1464 of FIG. 18, as the transistor 1446 (labelled MP8 in FIG. 19, having W/L ratio 8/0.5) has higher leakage than the equivalent transistor 1466 in FIG. 18. The transistors 1446 and 1442 (MP8 and MP7, W/L ratio 50/1), in turn, are wider than their equivalents (transistors 1466 and 1462) in the third (low voltage range) voltage detector circuit of FIG. 18. They operate in subthreshold mode with a lower effective gate threshold, whilst having a medium thickness gate oxide in order to withstand the higher voltage of the medium voltage range detector 144. The transistors 1448 and 1450 (MP9, W/L ratio 0.5/4 and MN8, W/L ratio 5/0.2) which make up the inverter are scaled (transistor 1450 has a greater W/L ratio than transistor 1448) so that transistor 1448 pulls the inverter output to the common reference and therefore turns the power gating transistor 124 (labelled MP1 in FIG. 5) on, before the input voltage reaches the threshold of the third (low voltage range) voltage detector 146.

(75) The widths of the transistors 1460, 1488 of the output stage of the second (medium voltage range) voltage detector 144 are asymmetrically scaled (i.e. the PMOS transistor 1488 has smaller W/L ratio than the NMOS transistor 1460) in order to speed up the pulling-down of the output V.sub.out(m). This is important during the falling-edge detection, as the power gating transistor 124 needs to be switched on as soon as the input drops below the threshold of the second (medium voltage range) detector 144 to avoid bounce in the open-drain system output V.sub.OD.

(76) The voltage detector system described herein combines ultra-low power consumption, low detection threshold and wide operating range. It is useful for a wide variety of applications including high- and low-side signal monitoring and power-gating, but also for low power control components such as oscillators, gate-drives, and switching devices in low-power converters. For example, due to the voltage detector system's low quiescent input current, capacitive or resistive divider circuits using 100-1000 M resistors can be used to adjust the detection threshold, for example to operate a load only over a desired rail voltage band, commonly referred to as Under-Voltage Lockout. Similarly, high value M pull-up resistors can be used to convert the output into a 2-level output, for example for use in ring oscillators, timers, clocks, wake-up circuits, and pulse generating circuits. This ability to use high-impedance (capacitive or resistive) peripheral components leads to control circuits that use only a few nA of current, which is important for the miniaturisation of wireless sensor nodes, wearable medical health sensors, and internet of things devices.

(77) The above embodiments are described by way of example only. Many variations are possible without departing from the scope of the appended claims.