Integrated serial communication

Abstract

An electric system comprising communication link between a signal transmitting end and a signal receiving end, wherein, at the signal transmitting end, a number of data bits are integrated into a low frequency signal to form an integrated signal. Each data bit is transmitted as part of a symbol. Each symbol comprises a predefined number of bits encoding at least one data bit, the state of some of the bits of each symbol being dependent on the state of the low frequency symbol.

Claims

1. A method for integrating a serial communication message, comprising a plurality of data bits, into a low frequency signal to form an integrated signal at a transmitting end of a communication link of an electric system, the integrated signal being sent from the transmitting end of the communication link to a receiving end of the communication link, wherein: each of the plurality of data bits is transmitted as a part of a symbol, each of symbols comprises a predefined number of bits encoding at least one data bit, the state of some of the bits of each of the symbols are dependent on the state of the low frequency signal, the symbols are formed into bytes, which are identified by a separate start symbol, or by a separate stop symbol, or by both a start and a stop symbol, and the symbols are separated from each other by a time delay which is longer than a filtering delay of the integrated signal at the receiving end of the communication link; wherein each of the symbols comprises two or more bits used to mark the beginning of the symbol and two or more bits used to encode the data bit or to indicate that the symbol is a start symbol or a stop symbol; and wherein the bits used to encode the data bit or to indicate that the symbol is the start symbol or the stop symbol (denoted below as c, d) are: c=1 if the data bit is 0 or if the symbol is a byte start symbol 0 if the data bit is 1 or if the symbol is a byte stop symbol d 1 if the data bit is 1 or if the symbol is a byte start symbol 0 if the data bit is 0 or if the symbol is a byte stop symbol.

2. The method according to claim 1, wherein at the receiving end of the communication link: the data bits, included in the symbols of the integrated signal, are decompressed from an integrated signal bit stream in a decoder.

3. The method according to claim 1, wherein at the receiving end of the communication link: the low frequency signal is separated from the integrated signal by delaying the integrated signal by a filtering delay which is longer than a duration of one symbol.

4. The method according to claim 1, wherein the bits used to mark the beginning of the symbol (denoted below as a, b) are: a=inverted low frequency signal state b=non-inverted low frequency signal state.

5. The method according to claim 1, wherein if a pulse edge of the low frequency signal occurs within a margin of safety of a symbol, the transmission of that symbol from the transmitting end of the communication link to the receiving end of the communication link is delayed.

6. The method according to claim 1, wherein the filtering delay of the integrated signal at the receiving end of the communication link is longer than the duration of each of the symbols.

7. The method according to claim 2, wherein at the receiving end of the communication link: the low frequency signal is separated from the integrated signal by delaying the integrated signal by a filtering delay which is longer than a duration of one symbol.

8. The method according to claim 2, wherein each of the symbols comprises two or more bits used to mark the beginning of the symbol and two or more bits used to encode the data bit or to indicate that the symbol is a start symbol or a stop symbol.

9. An apparatus for integrating a serial communication message, comprising a plurality of data bits, into a low frequency signal to form an integrated signal at a transmitting end of a communication link of an electric system comprising a transmitter, a receiver and the communication link between the transmitter and the receiver, the apparatus comprising at least one logic circuit configured to: encode each of the plurality of data bits to be transmitted into symbols; integrate the symbols in the low frequency signal to form the integrated signal, wherein the state of some of the bits of each of the symbols are dependent on the state of the low frequency signal, form the symbols into bytes, which are identified by a separate start symbol, or by a separate stop symbol, or by both a start and a stop symbol, and separate the symbols from each other by a time delay which is longer than the filtering delay of the integrated signal at the receiving end of the communication link; wherein the at least one logic circuit is further configured to generate each of the symbols such that two or more bits are used to mark the beginning of the symbol and two or more bits are used to encode the data bit or to indicate that the symbol is a start symbol or a stop symbol; and wherein the bits used to encode the data bit or to indicate that the symbol is the start symbol or the stop symbol (denoted below as c, d) are: c=1 if the data bit is 0 or if the symbol is a byte start symbol 0 if the data bit is 1 or if the symbol is a byte stop symbol d 1 if the data bit is 1 or if the symbol is a byte start symbol 0 if the data bit is 0 or if the symbol is a byte stop symbol.

10. The apparatus according to claim 9, wherein the operation of the at least one digital logic circuit is based on a prefixed function or a downloadable software.

11. The apparatus according to claim 9, wherein the apparatus is a power electronic converter, comprising a control unit and a power unit with simultaneous mutual low frequency signal communication at less than 50 kHz frequency and mutual serial communication at higher than 1 Mbit/s data transmission frequency.

12. A system comprising a communication link having a signal transmitting end and a signal receiving end, wherein, at the signal transmitting end, a plurality of data bits is integrated into a low frequency signal to form an integrated signal, the system comprising: at least one digital logic circuit at the signal transmitting end of the communication link, the at least one digital logic circuit configured to encode each of the plurality of data bits into symbols, integrate the symbols in the low frequency signal to form the integrated signal, wherein the state of some of the bits of each of the symbols are dependent on the state of the low frequency signal, form the symbols into bytes, which are identified by a separate start symbol, or by a separate stop symbol, or by both a start and a stop symbol, and separate the symbols from each other by a time delay which is longer than the filtering delay of the integrated signal at the signal receiving end of the communication link, a decoder, at the signal receiving end of the communication link, configured to decompress the data bits included in the symbols of the integrated signal, from an integrated signal bit stream, and a filtering delay block, at the signal receiving end of the communication link, configured to separate the low frequency signal from the integrated signal by delaying the integrated signal by a filtering delay which is longer than the duration of one symbol; wherein the at least one digital logic circuit is further configured to generate each of the symbols such that two or more bits are used to mark the beginning of the symbol and two or more bits are used to encode the data bit or to indicate that the symbol is a start symbol or a stop symbol; and wherein the bits used to encode the data bit or to indicate that the symbol is the start symbol or the stop symbol (denoted below as c, d) are: c=1 if the data bit is 0 or if the symbol is a byte start symbol 0 if the data bit is 1 or if the symbol is a byte stop symbol d 1 if the data bit is 1 or if the symbol is a byte start symbol 0 if the data bit is 0 or if the symbol is a byte stop symbol.

13. The system according to claim 12, wherein the operation of the at least one digital logic circuit is based on a prefixed function or a downloadable software.

14. The system according to claim 12, wherein the system is a power electronic converter, comprising a control unit and a power unit with simultaneous mutual low frequency signal communication at less than 50 kHz frequency and mutual serial communication at higher than 1 Mbit/s data transmission frequency.

Description

BRIEF DESCRIPTION OF FIGURES

(1) Below the invention appears a more detailed explanation using examples with references to the enclosed figures, wherein

(2) FIG. 1 presents communication channels in an electric device,

(3) FIG. 2 presents communication arrangements in an electric device,

(4) FIG. 3 illustrates signal streams suitable for use in the electric device of FIG. 2,

(5) FIG. 4 illustrates details of a combined signal data stream.

DETAILED DESCRIPTION

(6) FIG. 1 presents a simplified schematic illustration of a power electronics device 10 comprising of a control unit 11 and a power unit 13. The control unit 11 includes a controller 12, which may be e.g. a microprocessor executing a program, which determines how the power electronics device 10 operates. The controller 12 sends control signals (e.g. turn on/turn off) to the power electronic switch 14 in the power unit via the control cable CB.sub.12 which comprises a control wire for each power electronic switch. The signal frequency in this kind of a communication link between the control and power units is normally quite low due to the limitations of the operation frequency (called also as the switching frequency) of the power electronic switches. E.g. by IGBTs the normally used switching frequency is below 20 kHz.

(7) The example of FIG. 1 presents also another communication link between the control and power units, a bidirectional communication link CB.sub.11. It may be used e.g. for asking for and sending feedback data FB.sub.1 from the power unit 13 to the control unit. The data is collected by a power unit controller 15, and it is transmitted in form of serial communication messages. A normal communication speed in this kind of an information channel is higher than 100 kbit/s.

(8) FIG. 2 presents a simplified schematic illustration of a power electronics device 20, which is similar to that presented in FIG. 1 comprising a control unit 21 and a power unit 23. The control unit 21 includes a controller 22 and the power unit 23 includes a controller 25. In this arrangement, the controller 22 of the control unit 21 sends a first data stream HF.sub.21, comprising serial communication messages, and a second data stream LF.sub.21, comprising a control signal for a power electronics switch, to an encoder EC.sub.1 that encodes both data streams into an integrated signal stream according to this invention. From the encoder EC.sub.1 the integrated signal stream is sent to the power unit 23 via an unidirectional serial communication link CB.sub.22. The first and second data streams are separated at the power unit 23 end by a delay block DL.sub.2 and a decoder block DC.sub.2. In the delay block DL.sub.2 the serial communication messages are filtered out such that only the second data stream LF.sub.21 is left, as delayed, for controlling a power electronics switch 24. In the decoder block DC.sub.2 the first data stream, i.e. the serial communication messages, is separated from the integrated signal stream and fed to the controller 25 of the power unit 23. The serial communication message may include e.g. a specified request for feedback data from the power unit to the control unit.

(9) The controller 25 of the power unit can use a similar communication method and arrangement as explained above for sending feedback data FB.sub.2 to the control unit 21. In the presented example a serial communication data stream HF.sub.23 and a low frequency data stream LF.sub.23 are encoded in an encoder EC.sub.2 into an integrated signal stream which is sent via an unidirectional serial communication link CB.sub.21 to the control unit 21 and separated there in the delay block DL.sub.1 and the decoder block DC.sub.1, as presented above. The low frequency signal in this data transmission may be e.g. a fault signal.

(10) The logical functions in the control unit 21 as well as in the power unit 23, may be put into practice by using digital logic circuits based on a prefixed function, e.g. a CPLD (complex programmable logic device) or by using digital circuits based on a downloadable software, e.g. a microprocessor.

(11) FIG. 3 illustrates an example of signal bit streams according to the present invention. CBS is an integrated signal, comprising of a low frequency signal LF, which is in logical 0 state until time instant t.sub.1, stays in 1 state from t.sub.1 to t.sub.2, and returns to 0 position after time instant t.sub.2, and a serial communication signal, comprising pulsed signal cycles S5, S6 . . . , called as symbols in this document. The duration of a symbol is constant t.sub.S, and each symbol is separated from the previous symbol by a time delay t.sub.B.

(12) A predefined number of data symbols, in this example 8 (S0 . . . S7), form a data byte (BT1, BT2) which has a specified start symbol SS and a specified stop symbol ES.

(13) According to the invention, if the pulse edge of the low frequency signal LF occurs within a margin of safety from a symbol, that symbol is not sent at its original time slot but one period later (in FIG. 3, S6 is postponed from S6 because of an overlap with LF signal edge at t.sub.2).

(14) In the delay block (DL.sub.1, DL.sub.2 in FIG. 2) the integrated signal is delayed by a constant filtering time t.sub.F. Because delay t.sub.F is longer than duration t.sub.S, the symbol stream does not appear in the delayed signal pattern LFS. Due to the constant filtering delay t.sub.F and the margin of safety rule above the delayed signal pattern LFS always keeps the same form as the original signal pattern LF, which is important when this invention is applied in time-critical applications, e.g. in controlling IGBTs in PWM frequency converters.

(15) In the decoder block (DC.sub.1, DC.sub.2 in FIG. 2) the data bit content HFS (B0 . . . B7) of each byte are separated from the symbols. For clarity, in FIG. 3 all data bit states are marked as 1 and each symbol carries only one data bit.

(16) According to the present invention, the integrated signal CBS is delayed by a constant filtering delay t.sub.F in order to ensure that no symbol is visible in the filtered signal LFS. Advantageously the filtering delay t.sub.F is longer than the duration t.sub.S of a symbol. This rule guarantees that the internal signal edges of a symbol are not mixed with the signal edge of the low frequency signal LF.

(17) Another timing related rule according to the present invention is that the delay t.sub.B between the symbols is longer than the filtering delay t.sub.F. This rule guarantees that the signal edges during a symbol period do not disturb the timing of the low frequency signal delay t.sub.F.

(18) FIG. 4 illustrates an example how the symbols (SS and S0 in FIG. 3) in the integrated signal CBS data stream may be formed according to the present invention. CLK denotes an internal clock of encoder blocks (EC.sub.1, EC.sub.2 in FIG. 2), and each symbol lasts 4 clock cycles, denoted as a, b, c and d. The rules for the signal states during each symbol cycle are in this example the following:

(19) a=inverted low frequency signal state

(20) b=non-inverted low frequency signal state

(21) c=1 in data symbol if either the data bit is 0 or the symbol is a byte start symbol

(22) 0 in data symbol if either the data bit is 1 or the symbol is a byte stop symbol

(23) d=1 in data symbol if either the data bit is 1 or the symbol is a byte start symbol

(24) 0 in data symbol if either the data bit is 0 or the symbol is a byte stop symbol

(25) According to the above rule, the values a and b of the start symbol SS are 10 (since the low frequency signal state before the symbol SS was 0) and the values c and d of the start symbol SS are 11 (since the symbol is a byte start symbol). Thus, the start symbol SS is a bit sequence 1011 as illustrated in FIG. 4.

(26) According to the above rule, the values a and b of the first data symbol S0 are 01 (since the low frequency signal state before the symbol S0 was 1) and the values c and d of the first data symbol S0 are 01 (since the data bit being transmitted is 1. Thus, the first data symbol S0 if a bit sequence 0101 as illustrated in FIG. 4.

(27) According to the present invention, the rule how to form the symbol may be other than the above, as long as the byte start and/or stop and the data bit(s) can be recognized. E.g. the byte stop bits may be left out when the number of symbols after the byte start is fixed. It is also possible that different types of symbols comprise different number of bits, e.g. such that more than one data bit is included in a data symbol.

(28) A dimensioning example: According to the example above each symbol lasts 4 clock cycles. Thus in case of 10 MHz clock frequency a symbol duration is is 400 ns. The filtering delay t.sub.F should be clearly longer than this, e.g. 1 s, in order to avoid misinterpretation of a symbol signal edge as a low frequency signal edge. And further, the delay t.sub.B between the bytes should be clearly longer, e.g. 4 s, than the filtering delay in order to avoid disturbance of the filtering delay timing. Transmitting of one symbol in this example takes 4 s+400 ns, i.e. the data signal transmission frequency is 1/4.4=0.23 Mbit/s.

(29) The operating principle of the present invention does not set any strict limits for the frequency of the signals, but in practice it is best applicable if the signal frequency of LF is less than 10% of the clock frequency CLK (e.g. LF less than 50 kHz and CLK higher than 1 MHz).

(30) The specific examples provided in the description above are not exhaustive unless otherwise explicitly stated, nor should they be construed as limiting the scope and/or the applicability of the accompanied claims. The features recited in the accompanied dependent claims are mutually freely combinable unless otherwise explicitly stated. The verbs to comprise and to include are used in this document as open limitations that neither exclude nor require the existence of also un-recited features. Furthermore, it is to be understood that the use of a or an, i.e. a singular form, throughout this document does not exclude a plurality.

(31) While the present disclosure has been illustrated and described with respect to a particular embodiment thereof, it should be appreciated by those of ordinary skill in the art that various modifications to this disclosure may be made without departing from the spirit and scope of the present disclosure.