WAFER ARRANGEMENT, METHOD OF MAKING SAME AND HYBRID FILTER

Abstract

A wafer arrangement comprises a carrier wafer (CW) having a top surface divided into a regular pattern (RP) of first CA (SA1, ARS) and second surface areas (SA2, PES), wherein each first surface area is assigned to an adjacently applied respective separate second surface area to form together a combined filter area. Spots of thin film piezoelectric material are bonded to the first surface areas. Circuits of LC elements (PES) are formed integrally on the second surface areas from a multi-level metallization (ML1, ML2). The LC elements of each metallization level being embedded in a dielectric.

Claims

1. A wafer arrangement comprising a carrier wafer (CW) having at least an electrically isolating top surface, which surface is divided into a regular pattern (RP) of first and second surface areas (SA1,SA2), wherein each first surface (SA1) area is assigned to an adjacently applied respective separate second surface area (SA2) to form together a combined filter area spots of thin film piezoelectric material (TF) bonded to the first surface areas (SA1) circuits of LC elements (LC) that are formed integrally on the second surface areas from a multi-level metallization, the LC elements of each metallization level (ML) being embedded in a dielectric.

2. The wafer arrangement of claim 1 wherein thin film SAW devices (TFS) are formed on the spots of thin film piezoelectric material (TF) such that each first surface area comprises one thin film SAW device (TFS) wherein each thin film SAW device is electrically interconnected with an assigned circuit of LC elements (LC) to form a combined filter circuit comprising LC elements and thin film SAW devices (TFS).

3. The wafer arrangement of claim 1 wherein the regular pattern of first and second surface areas is a) a checkerboard pattern formed by spots comprising thin film SAW devices (TFS) and circuits of LC elements, or b) an alternating pattern of first and second parallel stripes, each first stripe comprising a row of thin film SAW devices, each second stripe comprising a row of LC circuits, or c) a parallel arrangement of first and second stripes, wherein a first and an adjacent second stripe form a first pair of stripes, wherein a second pair of a second and an adjacent first parallel stripe is mirror-inverted relative to the first pair, and wherein first and second pairs of stripes are arranged alternatingly.

4. The wafer arrangement of claim 1, wherein those spots of thin film piezoelectric material that comprise more than one TFSAW device are provided with a pattern of trenches (TR) wherein the trenches are cut into the bottom surface of the spots of thin film piezoelectric material (PM) bonded to the carrier wafer wherein the depth of the trenches ranges from half the layer thickness of the thin film piezoelectric material up to the total thickness d2 thereof such that the top surface of the carrier wafer is exposed in the separation lines from the top.

5. The wafer arrangement of claim 1, wherein the thin film SAW devices (TFS) are enclosed under a capping layer of a thin film package (TFP) providing a cavity between the thin film SAW devices (TFS) and the capping layer.

6. The wafer arrangement of claim 1, wherein the dielectric (DE) the LC elements (LC) are embedded in is an organic dielectric.

7. The wafer arrangement of claim 1, wherein the dielectric (DE) the LC elements (LC) are embedded in is an oxide such as silicon dioxide.

8. The wafer arrangement of claim 1, wherein the LC elements (LC) are formed from a multi-level metallization, each metallization level (ML) of the LC elements is embedded in a dielectric (DE) LC elements that are formed in the same metallization level are electrically connected by conductor lines LC elements that are formed in different metallization levels are interconnected by vias the TFSAW devices are electrically connected to a LC circuit respectively by conductor lines guided on top of the thin film SAW devices (TFS) and on top of the uppermost dielectric (DE) of the multi-level metallization.

9. A method of manufacturing the wafer arrangement of claim 1, comprising the steps a) providing a functional wafer (FW) comprising a crystalline functional layer (FL) b) dividing the functional wafer (W1) into a regular array (RA) of virtual functional chip sections (FCS) and separating the functional wafer (W1) into smaller spots, each spot comprising a single functional chip section only, or a stripe with several functional chip sections arranged in a row, or a stripe with functional chip sections arranged in two parallel rows, c) providing a carrier wafer (CW) d) dividing a main surface of the carrier wafer (W2) into a regular pattern of virtual carrier chip sections (CCS), each comprising area for a virtual functional chip section and a virtual passive element section e) bonding the spots to the main surface (BS) of the carrier wafer (W2) such that each functional chip section of a spot totally covers a first surface area of a respective virtual carrier chip section while the second surface area of the respective carrier chip section (CCS) is left exposed f) reducing the thickness d1 of the functional layer of all spots until a thin film functional layer (TF) of a desired thickness d2 in each spot is achieved.

10. The method of claim 9 comprising a step h h) forming a first partial circuit (PC1) of a hybrid filter from a circuit of LC elements (LS) produced on the exposed second surface (SA2) area of each such virtual carrier chip section.

11. The method of one of the claim 9, comprising a step i) performed before or after step h) i) forming a second partial circuit of a filter circuit from a circuit of SAW resonators produced on each of the functional chip sections k) integrally connecting first and second partial circuit on each of the carrier chip sections to form a combined filter circuit l) separating the carrier wafer into single carrier chip sections by dicing.

12. A hybrid filter comprising a combined filter circuit singulated from a wafer arrangement of any of claims 1-8.

Description

[0057] In the following the invention is explained in more detail with reference to specific embodiments and the accompanying figures. The figures are schematic only and are not drawn to scale such that single parts of the figures may be depicted as greater than they really are for better understanding. Hence neither absolute nor relative dimension can be taken from the figures.

[0058] FIG. 1 shows a functional wafer in a top view and in a cross-sectional view;

[0059] FIG. 2A shows a schematic top view of a carrier wafer with a checkerboard pattern of first and second surface areas;

[0060] FIG. 2B shows a carrier wafer with a regular pattern comprising rows of functional chip sections in a top view;

[0061] FIG. 2C shows a carrier wafer with a regular pattern comprising stripes of two parallel rows of functional chip sections in a top view;

[0062] FIG. 3A to 3i show different stages of a manufacturing process in a cross-sectional view;

[0063] FIG. 4 is a schematic cross-section through a hybrid filter;

[0064] FIG. 5 is a block diagram of a first and a second partial circuit of LC elements and acoustic resonators;

[0065] FIG. 6 is a more detailed cross-section through a multilevel metallization comprising a circuit of LC elements;

[0066] FIG. 7 shows a cross-section through a hybrid filter comprising interconnected first and second partial circuits,

[0067] FIG. 8 is a block diagram of a ladder-type filter from acoustic resonators;

[0068] FIG. 9 is a block diagram of a lattice filter of acoustic resonators.

[0069] A method for producing a wafer arrangement starts with a functional wafer FW. The functional wafer FW is divided into a regular array of virtual functional chip sections FCS shown in the top view on the left side of FIG. 1. The according cross-section through the functional wafer FW is shown on the right side of FIG. 1. The functional wafer has a thickness d1.

[0070] In the next step the functional wafer FW is separated into smaller sized spots such that each spot comprises [0071] a single functional chip section only, or [0072] a stripe with several functional chip sections arranged in a row, or [0073] a stripe with functional chip sections arranged in two parallel rows.

[0074] From one functional wafer different sized spots can be retrieved. However, it is preferred to retrieve spots that comprise a maximum number of functional chip sections to facilitate the handling of the spots.

[0075] Independently therefrom carrier wafer CW is divided into a regular pattern (RP) of carrier chip sections (CCS), each carrier chip section comprising a first surface area SA1 and a second surface area SA2.

[0076] FIGS. 2A to 2C show different arrangements of first and second surface areas and respective carrier sections comprising a first and a second surface area.

[0077] FIG. 2A show a carrier wafer where first and second surface areas SA2, SA2 are arranged in a checkerboard pattern. This means that in a horizontal row first and second surface areas are alternating. In each vertical column first and second surface areas are alternating too such that each row is shifted against the adjacent row. A first and an adjacent second surface area SA1, SA2 form a virtual carrier chip section CCS. In the figure, only two such virtual carrier chip section CCS are marked with a thick-lined rectangular.

[0078] FIG. 2B shows a carrier wafer CW with the second arrangement of first and second surface areas SA1, SA2. The row of first surface areas SA1 and a row of second surface areas SA2 are arranged in an alternating sequence parallel to each other. The rows are dimensioned to cover a maximum amount of the carrier wafer CW such that a maximum number of carrier chip sections CCS is retrieved.

[0079] FIG. 2C shows a third possible arrangement where first surface areas SA1 are arranged in two adjacent parallel rows. Between two pairs of rows two rows of second surface areas are inserted such that carrier chip sections CCS are formed each comprising a first surface area SA1 and an adjacent second surface area SA2.

[0080] Onto such a divided carrier wafer CW spots of piezoelectric material cut from the functional wafer FW are arranged that each first surface area SA1 is covered by a virtual functional chip section of a spot of piezoelectric material. To cover all first surface areas SA1 of the carrier wafer with the respective virtual functional chip section FCS, different sized spots of piezoelectric materials can be used. This means that any of the rows of first surface areas of FIGS. 2B and 2C can be covered by a number of different spots where each spot can comprise one or more virtual functional chip sections FCS.

[0081] FIG. 3A shows a cross-section of a carrier wafer CW provided with spots of piezoelectric material PM according to an arrangement as shown in FIG. 2A or 2B. The piezoelectric material PM has the original thickness d1 of the original functional wafer FW. To achieve a thin film piezoelectric material TF, the thickness of the spots of piezoelectric material PM is reduced to a thickness d2. FIG. 3B shows the arrangement at this stage.

[0082] In the next step on each exposed second surface area SA2 of FIG. 3B a circuit of LC elements is formed. The LC elements form a first partial circuit of the desired hybrid filter. FIG. 3C shows a cross-section through the carrier wafer at this stage where first surface areas are covered by thin film piezoelectric material and second surface areas are covered by a circuit of LC elements LC.

[0083] Another embodiment comprises a sequence of steps and stages as shown in FIGS. 3D, 3E and 3C. The method starts with a carrier wafer as shown in FIG. 2. Onto the second surface areas SA2 thereof circuits of LC elements LC are produced and first surface areas SA1 are left exposed as shown in FIG. 3D.

[0084] Into these exposed first surface areas spots of piezoelectric material PM of a thickness d1 are arranged and bonded to the carrier wafer CW. FIG. 3E shows the arrangement at this stage.

[0085] After thinning the spots of piezoelectric material PM to a thickness d2 an arrangement according to FIG. 3C is achieved. This stage complies with the respective stage of the first variant.

[0086] According to an alternative embodiment not shown in the figures the arrangement shown in FIG. 3B is subjected to a process of forming thin film SAW devices TFS on the spots of thin film piezoelectric material.

[0087] A further intervening step comprises packaging the thin film SAW devices TFS with a thin film SAW package that leaves pads PD of the thin film SAW devices TFS exposed for electrical interconnection with the later circuit of LC elements.

[0088] Electrical contact can be made integrally when producing the circuit of LC elements LC.

[0089] In a step following the stage shown in FIG. 3B or 3C thin film SAW devices TFS are produced by forming metallic electrode structures on the top surface of the thin film piezoelectric material TF. Then, the thin film SAW devices TFS of a carrier chip section are connected with the respective circuit of LC elements LC of the same carrier chip section CCS by respective conductor lines. In this way a hybrid filter is achieved in each carrier chip section CCS comprising a thin film SAW device and a respective circuit of LC elements.

[0090] In a later step the thus produced hybrid filters are singulated by dicing the carrier chip and the respective structures formed thereon along separation lines SL, as shown in FIG. 3F.

[0091] FIG. 3G shows a single hybrid filter comprising exact one carrier chip section CCS comprising a thin film SAW device TFS and an interconnected circuit of LC elements LC.

[0092] Alternatively packaging of the hybrid filters can be done at the stage as shown in FIG. 3F. The packaging is not shown in the figures.

[0093] FIGS. 3H and 3i show a preferred method of handling spots of piezoelectric material PM comprising more than one functional chip section FCS. To ease the later separation into single chips the spots are provided with trenches TR at the bottom surface thereof. The trenches divide adjacent functional chip sections. As shown in FIG. 3H each trench TR may have a thickness between d1 and d2 but leaves sufficient mechanical stability to the spot for secure handling thereof.

[0094] FIG. 3i shows the arrangement after thinning the piezoelectric material PM to a thickness d2. Hereby the trenches are exposed from the top and form gaps GP between adjacent functional chip sections of thin film piezoelectric material TF. Second surface areas SA2 on the carrier wafer CW remain exposed. A step of polishing the surface may follow.

[0095] FIG. 4 schematically shows a hybrid filter. The hybrid filter comprises a passive element section PES and an acoustic resonator section ARS. The acoustic resonator section ARS comprises a circuit of SAW resonators that form a SAW device that is a second partial circuit of a hybrid filter. Exact structures of the SAW device that forms a second partial circuit PC2 of the hybrid filter are not shown.

[0096] The passive element section PES comprises several metallization levels ML1, ML2, two of which are shown in FIG. 4. In a first metallization level ML1, for example, a capacitor MIM may be formed. In the second metallization level ML2 an inductance or coil may be formed and interconnected with the passive elements of the first metallization level ML1 by vias. Alternatively the structures of the first metallization level ML1 to be connected with structures of the second metallization level ML2 need to be exposed after embedding the first metallization level ML1 in a dielectric. The figure does not show the conductor lines and vias connecting passive elements of the passive element sections PES and the SAW resonators SR of the acoustic resonator sections ARS.

[0097] FIG. 5 shows a block diagram of a hybrid filter with a minimum number of elements. A real circuit may comprise a higher number of such structures. In FIG. 5 a first partial circuit PC1 comprises a series impedance element IE.sub.S and a parallel impedance element IE.sub.P. The series impedance element IE.sub.S can be embodied as a capacitor and the parallel impedance elements IE.sub.P can be embodied as a coil. A second partial circuit PC2 comprises at least one series SAW resonator SR.sub.S and at least one parallel SAW resonator SR.sub.P. Within the combined circuit first and second partial circuits PC1, PC2, as shown in FIG. 5, can alternate or be arranged in an arbitrary sequence. The exact design of such a hybrid filter can be optimized according to the requirements of the desired hybrid filter. Such an optimization can easily be done by a skilled worker by means of an optimizing computer program.

[0098] FIG. 6 shows a schematic cross-section through the passive element section PES of a hybrid filter. This passive element section may be formed according to a method as described in the above-mentioned US 2017/0077079 A1. On a carrier wafer CW that is preferably a plane glass wafer, first LC elements are formed and embedded in a first dielectric DE1. In the figure a LC elements is embodied as a metal-isolator-metal capacitor MIM that is a first metal structure covered by a dielectric layer DL and a further metal structure as a second capacitor electrode.

[0099] Above the first dielectric DE1 a second metallization level ML2 is formed, structured and embedded in a second dielectric DE2. Both dielectrics DE1 and DE2 may be identical for both metallization levels or different. One element of the capacitor MIM may be structured in the second metallization level as the top electrode.

[0100] The metal structures may be made of Al or an AlCu alloy. The dielectric layer DL may be an oxide like silicon oxide.

[0101] Above the first dielectric DE1 a second metallization level ML2 is formed, structured and embedded in a second dielectric DE2. Besides the top electrode of the capacitor MIM, a coil IND is structured from the second metallization level ML2. For forming a planar coil IND a single mask step is used to structure the second metallization level ML2 accordingly.

[0102] Structuring a metallization level ML can be done by first forming and structuring a resist mask and then depositing a metal in areas exposed by the resist mask. Deposition of a metal may be done by plating a metal onto a seed layer that is applied onto the entire surface of substrate SU for the first metallization level or onto the first dielectric DE1 or a higher level of dielectric. After the plating step the resist mask is removed thereby exposing remaining seed layer areas that are then removed as well.

[0103] A three-dimensional coil IND (not shown in the figure) needs to be formed within two neighboured metallization levels. One of them may be the first metallization level ML1.

[0104] For interconnecting the two metallization levels ML1, ML2 a respective metallization in the lower metallization level ML1 is exposed by forming an opening in the top surface of the first dielectric DE1. Structures of the second metallization level ML2 applied thereon can now contact respective structures in the first metallization level ML1. All structures that need not have an electrical inter-level connection are isolated against each other by the first dielectric DE1.

[0105] A circuit of LC elements LC is integrally formed in a two-level metallization.

[0106] In an area of interconnection ICN a via may provide electric contact between different metallization levels and a contact area CA the top surface of the circuit of LC elements. Alternatively, an electrical interconnection of the LC circuit is provided at the bottom by a conductor line on the top surface of the carrier wafer or at any higher level dependent on the structures present on the carrier wafer CW.

[0107] FIG. 7 shows a cross-section through a carrier chip section CCS of the wafer arrangement that may be singulated from the wafer arrangement. As already shown schematically in FIG. 4, the combined filter circuit is arranged on a carrier wafer CW and comprises a passive element section PES and an acoustic resonator section ARS. The acoustic resonator section ARS comprises a thin film SAW device TFS that is achieved by providing electrode structures on top of the functional layer FL of the thin film piezoelectric layer layer. The thin film SAW device TFS is enclosed by a thin film package TFP providing a cavity enclosing the electrode structures of the thin film SAW device.

[0108] The thin film package TFP may expose a pad PD connected to the electrode structures of the thin film SAW device TFS to enable electrical contact to the circuit of LC elements arranged in the passive element section PES. In this embodiment the thin film SAW device TFS is completely packaged before manufacturing and depositing the multilevel metallization of the circuit of LC elements in the passive element section PES. In the figure a metallic structure of the second metallization level ML2 is in direct contact with the pad PD to interconnect passive element section PES and acoustic resonator section ARS.

[0109] The acoustic resonator section ARS may comprise a circuit of thin film SAW resonators SR connected in a ladder-type or a lattice-type topology as shown schematically in FIGS. 8 and 9.

[0110] FIG. 8 shows a ladder-type arrangement comprising series SAW resonators SR.sub.S and parallel SAW resonators SR.sub.P. In this embodiment a respective series SAW resonator SR.sub.S and an according parallel SAW resonator SR.sub.P form a basic section BS.sub.LT of the ladder-type arrangement. A ladder-type arrangement comprises a number of basic sections BS.sub.LT that can be circuited in series to achieve a desired filter function of a second partial filter circuit PC2.

[0111] FIG. 9 shows a lattice-type arrangement of SAW resonators comprising series and parallel SAW resonators. In contrast to the ladder-type arrangement, the parallel SAW resonators SR.sub.P are arranged in parallel branches that interconnect two series signal lines with series SAW resonators SR.sub.S. The parallel branches are circuited in a crossover arrangement such that the basic section of the lattice-type arrangement BS.sub.LC comprises a first and a second series SAW resonator SR.sub.S arranged in two different signal lines and two crossover circuited parallel branches with a respective parallel SAW resonator SR.sub.P arranged therein. A lattice-type filter may also comprise a number of basic sections according to the filter requirements.

[0112] The invention has been explained by a limited number of examples only and is thus not restricted to these examples. The invention is defined by the scope of the claims and may deviate from the provided embodiments.

[0113] Such further embodiments may comprise further details not shown in the presented embodiments. Further, the wafer arrangement and also every hybrid filter may comprise an arbitrary circuit of LC elements and SAW devices of an arbitrary structure. The hybrid filter may realize an arbitrary one of a series of different filter functions. Examples are bandpass, high pass and low pass as well as combined filters like an extractor, duplexer or multiplexer.

TABLE-US-00001 List of used reference symbols ARS acoustic resonator section BS.sub.LT, BS.sub.LC basic section of ladder type and lattice filter CA contact area CW carrier wafer d1 first thickness (of FW) d2 second thickness (of TF) DE1, DE2 dielectric DL dielectric layer FCS (virtual) functional chip section FL functional layer FW functional wafer GP gap ICN interconnection IE.sub.S, IE.sub.P series and parallel impedance elements IND coil LC circuit of LC elements MIM MIM capacitor ML1, ML2 metallization levels, embedded in a PC1, PC2 first and second partial circuit of hybrid filter PD Pad PES passive element section PM spots of piezoelectric material RP regular pattern SA1, SA2 first and second surface areas SL separation lines SR.sub.S, SR.sub.P series and parallel SAW resonators TF thin film piezoelectric material TFP thin film package TFS thin film SAW device TR trench