Cell balancing method and system

Abstract

The invention relates to a system for battery cell balancing comprising a cell monitoring block (16) configured to monitor the voltage or a related quantity across individual cells (C.sub.1, C.sub.2, . . . C.sub.N) in a battery cell module; a microcontroller (18) configured for monitoring the positive terminal voltage (12) and the negative terminal voltage (13) of said battery cell module, and for monitoring (11) the output current I.sub.mod of said module, and monitored cell voltage of said individual cells (C.sub.1, C.sub.2, . . . C.sub.N), where the microcontroller (18) is configured to provide a control signal (20) based at least said positive terminal voltage (12), said negative terminal voltage (13), said output current I.sub.mod of said module, and said monitored cell voltage of said individual cells; and a hybrid module balancing block configured to provide either an active or a passive cell balancing or a combination of active and passive cell balancing of the cells (C.sub.1, C.sub.2, . . . C.sub.N) in the specific module under the control of the control signal provided by the microcontroller. The invention further relates to a method for battery cell balancing in a battery comprising one or more modules each comprising one or more cells.

Claims

1. A system for battery cell balancing comprising: a cell monitoring block configured to monitor the voltage or a related quantity across individual cells (C.sub.1, C.sub.2, . . . C.sub.N) in a battery cell module; a microcontroller configured for monitoring the positive terminal voltage and the negative terminal voltage of said battery cell module, and for monitoring the output current I.sub.mod of said module, and monitored cell voltage of said individual cells (C.sub.1, C.sub.2, . . . C.sub.N), where the microcontroller is configured to provide a control signal based on at least said positive terminal voltage, said negative terminal voltage, said output current I.sub.mod of said module, and said monitored cell voltage of said individual cells; and a hybrid module balancing block configured to provide either an active or a passive cell balancing or a combination of active and passive cell balancing between the individual cells (C.sub.1, C.sub.2, . . . C.sub.N) in the specific battery cell module under the control of the control signal provided by the microcontroller, wherein the microcontroller and the hybrid module balancing block are configured to, subsequent to providing the active cell balancing between the individual cells (C.sub.1, C.sub.2, . . . C.sub.N) of said specific battery cell module, responsive to state of charge (SOC) of one or more of the individual cells (C.sub.1, C.sub.2, . . . C.sub.N) being above a predefined upper limit, provide the passive cell balancing of the individual cells (C.sub.1, C.sub.2, . . . C.sub.N) of said specific battery cell module, and wherein the predefined upper limit is a maximum allowable SOC of the cells (C.sub.1, C.sub.2, . . . C.sub.N) or a SOC average value of the said specific battery cell module.

2. The system according to claim 1, wherein said hybrid module balancing block comprises: a switching array configured to provide active or passive or a combination of active and passive balancing to one or more of said individual cells (C.sub.1, C.sub.2, . . . C.sub.N) in said specific module under the control of said control signal; a passive cell balancing means configured to provide said passive balancing under the control of said control signal; an active cell balancing means configured to provide said active balancing under the control of said control signal.

3. The system according to claim 1 comprising a passive module balancing means coupled between the positive and negative terminals of said specific module.

4. The system according to claim 2, wherein said active cell balancing means is a flyback DC/DC converter.

5. The system according to claim 2, wherein said passive cell balancing means is a resistor in series with a switch, such as for instance a MOSFET.

6. The system according to claim 3, wherein said passive module balancing means is a resistor in series with a switch, such as for instance a MOSFET.

7. The system according to claim 4, wherein the flyback DC/DC converter extracts power from all of the cells (C.sub.1, C.sub.2, . . . C.sub.N) of a module, and injects a controlled current to balance the most discharged cell until it is in balance with the other cells.

8. The system according to claim 7, wherein said controlled current is constant.

9. The system according to claim 1, wherein said microcontroller is a microcontroller in a battery management system (BMS) that manages the overall performance of the battery.

10. The system according to claim 1, wherein active balancing as applied in the modules making up a battery, whereas passive balancing is applied between two or more modules making up the battery.

11. The system according to claim 10, wherein the system comprises module SOC monitoring means or voltage monitoring means that monitors the SOC or voltage of the modules in a battery and when an imbalance between the SOC or voltage is detected between two or more modules, passive balancing between the two or more modules in the battery is performed.

12. The system according to claim 10, wherein the passive balancing between two or more modules in a battery is controlled by said hybrid module balancing block or said battery management system (BMS).

13. A method for battery cell balancing in a battery comprising at least one module comprising a plurality of cells, the method comprising the steps of: determining if a charging process is in progress; choosing a module (M1); applying active cell balancing between the individual cells of said module (M1); subsequent to providing the active cell balancing between the individual cells of said module (M1): determining if one or more of the individual cells of said module (M1) are charged above a predefined upper limit, wherein the predefined upper limit is a maximum allowable state of charge (SOC) of the cells or a SOC average value of the cells in said module (M1); if the one or more cells in said module (M1) are charged above said upper limit, applying passive cell balancing to the one or more individual cells in said module (M1) in order to reduce their respective charge to a value at or below said upper limit; when all cells within said module (M1) are charged, determine if there are further modules (M2, M3 . . . ) in the battery, and if this is the case repeat the above steps for the remaining modules (M2, M3 . . . ); when all modules of the battery have been charged, determine if there is an imbalance between the SOC or a similar parameter of the respective modules in the battery, and if this is the case, apply either passive or active balancing between respective modules in order to reduce said imbalance between modules to a required level.

14. The method according to claim 13, wherein active balancing as applied in modules making up a battery, whereas passive balancing is applied between modules making up the battery.

15. The method according to claim 14, wherein the SOC or voltage is monitored by monitoring means that monitors the SOC or voltage of two or more modules in a battery and when an imbalance between the SOC or voltage is detected between two or more modules, passive balancing between the two or more modules in the battery is performed.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Further benefits and advantages of the present invention will become apparent after reading the detailed description of non-limiting exemplary embodiments of the invention in conjunction with the accompanying drawings, wherein

(2) FIG. 1 shows an embodiment of a cell balancing system according to the present invention;

(3) FIG. 2 shows a flow chart illustrating the basic steps of an embodiment of a method according to the present invention;

(4) FIGS. 3A and B show a schematic diagram of an isolated fly-back converter used in embodiments of the present invention;

(5) FIG. 4 shows a fly-back control block used in embodiments of the present invention;

(6) FIG. 5A through G show a schematic diagram of the interface with a Hercules microcontroller used in an embodiment of the invention;

(7) FIG. 6A through E show a schematic diagram of a dual switch isolated flyback converter used in an embodiment of the invention;

(8) FIG. 7A through G show a schematic diagram of a relay selection circuitry comprising a de-multiplexer used in an embodiment of the invention;

(9) FIG. 8 shows a plot of simulation results for a 16 cell module; and

(10) FIG. 9 shows a plot of simulation results for a 8 cell module.

DETAILED DESCRIPTION OF THE INVENTION

(11) A non-limiting embodiment of a cell balancing system according to the invention is described in detail in the following. It is however understood that the invention may be implemented in other ways and that all such embodiment of the invention will fall within the scope of protection defined by the patent claims.

(12) It is expressly noted that although specific numerical values for various parameters etc. will be mentioned in the following, such specific numerical values are only to be regarded as examples and they do not, consequently, limit the scope of the patent protection.

(13) With reference to FIG. 1 there is shown an embodiment of a cell balancing system according to the present invention generally indicated by reference numeral 1 comprising means for applying a combination of active and passive cell balancing.

(14) The system shown in FIG. 1 comprises a battery module that in the shown embodiment contains a series connection of ten cells C1, C2, . . . C10. It is of cause understood that a different number of cells could be present in the module and that the principles of the invention would apply equally well to such modules.

(15) It is further understood that although the term module is used repeatedly in the description of the embodiment shown in FIG. 1, the present invention is not restricted to one or more physical modules making up a total battery. A battery could thus simply comprise a number of cells coupled in series without any subdivision into specific modules or a module may simply be a fictive subdivision of a given number of cells in a battery. Thus, reference to the term module implies no restriction to the scope of the present invention.

(16) The system comprises a hybrid module balancing block 3 that comprises a switching array 4, a passive balancing means, such as the resistor 5 that can be activated through a controllable switch 6, such as a MOSFET, and an active balancing device, such as a DC/DC converter 7.

(17) Coupled across the entire module there is further connected a module passive balancing means, such as the resistor 8 that can be activated through the switch 9, such as a MOSFET.

(18) The switching array 4, the cell passive balancing means 5 and 6, the DC/DC converter 7 and the module passive balancing means 8 and 9 are controlled by appropriate control signals, as symbolically indicated be control lines 20 through 25.

(19) The voltages over each respective cells C1 through C10 are measured by means of a cells monitoring block 15 that in the shown embodiment comprises the two ASIC's 16 and 17 connected to the terminals of the respective cells through cell voltage measuring lines Vcells.

(20) In order to optimize the performance of the system according to this embodiment of the invention and to maximize the balancing current and thus reducing the balancing time, the flyback converter can be controlled from the main microcontroller in the battery management system (BMS). An example of such a microcontroller is the HERCULES MCU 32-bit ARM Cortex R4 manufactured by Texas Instruments. The system and method according to the present invention can be implemented in the BMS main microcontroller, but could alternatively be implemented in a separate microcontroller. The controlling microcontroller is in the shown embodiment designated by reference numeral 18 and is in connection with the ASIC's 16 and 17 in the cells monitoring block 15 through the serial peripheral interfaces SPI.

(21) The microcontroller 18 receives a signal indicating the positive module voltage Vmod+ via signal line 12 and a signal indication the negative module voltage Vmod via signal line 13. Further, the microcontroller 18 received a signal indicating the output current I.sub.mod 26 from the module via signal line 11. The output current 26 is measured by suitable means as symbolically indicated by 25. The microcontroller 18 provides, based inter alia on these signals the control signal 20 to the various functional blocks of the balancing system, i.e. the control signals 21, 22, 23 and 24.

(22) This Switched DC/DC converter that is used in the shown embodiment of the invention is based on a Module to Cell topology and allows, without too much extra costs, to monitor the current injected on each cell while balancing, thus enabling to obtain a better SOC considering the current injected during the balancing process.

(23) The DC/DC Converter 7 is an isolated flyback converter that extracts the power from all the module cells (C1 through C10 in the embodiment shown in FIG. 1) and injects a controlled constant current (CC) to balance the most discharged cell until it is in balance with the other cells. The connection of the isolated flyback converter to the most discharged cell is done with an array of relays 4 and only one can be switched at the same time to avoid dangerous short circuits.

(24) The design of the DC/DC converter that can be used in embodiments of the invention is described in some detail in the following. The converter can as mentioned above for example be implemented into the HERCULES microcontroller, if desired.

(25) The converter control needs an analog signal for measuring the balancing current (and close the feedback loop for control), a PWM digital output, and a digital output per cell (built using an external de-multiplexing system) to activate the switches that connect the DC/DC converter to the cell that requires balancing.

(26) The Switched DC/DC converter according to an embodiment of the invention is based on a Module to Cell topology and allows, without limited extra costs, to monitor the current injected on each cell while balancing, thus making it possible to obtain a more optimal state of charge (SOC) considering the current injected during the balancing process.

(27) Referring to FIG. 2 there is shown a flowchart illustrating an embodiment of a cell balancing method according to the invention that can for instance be applied for a battery comprising one or more modules, each comprising a number of cells, as for instance shown in FIG. 1.

(28) The balancing method is initiated at step 27 and a given battery module is chosen at step 28. In step 29 it is determined by appropriate means if a charging process is in taking place and if this is the case the method proceeds to step 30, thereby applying active cell balancing between cells in the given module, i.e. the module chosen in step 28.

(29) Towards the end of the charging it may happen that one or a few cells of the given module are charged above a predefined upper limit L.sub.u of SOC or cell voltage. If this is detected in step 31, according to the embodiment of the method shown in FIG. 2, that this or these cells are charged above the predefined upper limit L.sub.u, passive cell balancing is applied to these cells in step 32 in order to reduce their charge to the required value. If it is determined in step 31 the no cells are above the upper limit the process proceeds to step 33 in which it is determined if further modules that have to be charged are present in the battery, after which the above described process is repeated for the next module.

(30) If no further modules are present in the battery, it is in step 34 determined, if there is an imbalance between the SOC of voltage between modules. If this is the case, the process applies either passive or active balancing between modules, for instance (in case of passive balancing) by means of the resistor 8 shown in FIG. 1. This inter module balancing proceeds until a required balance between modules have been obtained, after which the process terminates in step 38.

(31) In functional block 36, the upper limit L.sub.u can be determined and provided as indicated by 39 to the functional step 31.

(32) Referring to FIGS. 3A and B there is shown a schematic circuit diagram of an embodiment of an isolated flyback converter circuitry (MOSFETS, filters, isolation transformer, etc.), where the flyback Control block and the cell C1, C2 and C3 connected to the output of the flyback converter. It is noted that other numbers of cells than the three actually shown in the figure could be used according to the invention. There are other parts in the schematic used to measure currents and voltages all along the circuit. The energy needed to correct the unbalance status of one specific cell is obtained from all the cells of the module and is then injected on that specific cell.

(33) The DC/DC converter topology is an isolated flyback converter, acting like a buck converter with isolation. The PWM signal allows controlling the output current and voltage of the DC/DC converter.

(34) An objective of the system and method of the present invention is to re-charge the unbalanced cell with a controlled current, for instance a 1 A current, that is extracted from the full array of cells that composes a module.

(35) In order to design the control algorithm that later will be implemented in the HERCULES microcontroller, the simulation schematic includes filtering and discretization of the output current feedback measurement. This resembles the way an analog stage and an Analog to Digital Converter (ADC) work in a real electronic system. Also, the flyback control block works in the way it is expected to work in the HERCULES microcontroller, this means that the control code is executed one time for each sample acquisition of the analog signal.

(36) The sampling frequency has in the results of the simulations shown in the following been set to 2 kHz and the resolution of the ADCs is 12 bits. The output current will be sensed using a shunt resistor (in this example 50 mOhm) and an instrumentation amplifier (for instance INA282) with a fixed gain of 50 in the results shown in the following. The PWM switching frequency has been set at 100 kHz, but other switching frequencies could also be used.

(37) Referring to FIG. 4 there is shown a flyback_Control block that implements the control algorithm that allows re-charging a specific cell from its initial unbalanced state up to the desired balanced state. The parameters needed to control the start-stop and current injection are: Desired output current: fixed at 1 A (Iout) Output current feedback: IoutDC Cell SOC: SOC_1 Desired final SOC: Final_SOC

(38) There are other control parameters in the flyback_Control block related with the simulation process in PSIM (fs) and PI regulator parameters (Kp, Ki) for controlling the output current. The flyback_Control block is in an embodiment programmed in C code to make it easily portable to the HERCULES microcontroller, but it is understood that other programming languages could alternatively be used.

(39) The most important part of the control algorithm (PI controller) implemented in the flyback_Control block is shown in the following:

(40) TABLE-US-00001 ... if (SOC <= Final_SOC) //run the algorithm until Final_SOC is reached { // do nothing until 1ms. Simulates initialsation state of the uController if (Tdis <= 0.001) { Iout = 0; IoutDC_s = 0; Tdis = 0; Kp = 0; Ki = 0; err = 0; err_k1 = 0; Int = 0; Out = 0; PI_out = 0; y1= 0; y2 = 0; y3 = 0; y4 = 0; } else // Flyback PI control algorithm { Iout = x1; // output current objective IoutDC_s = x2; // discretized output current feedback // PI Controller err = Iout IoutDC_s; // Error calculation Int = Int + (err/fs); // Integral calculation Out = Kp*err + Ki*Int; // PI result PI_out = Out; // Saturation to avoid excesive PWM duty cycle or below 0 if (PI_out >= 0.44) { PI_out = 0.44; sat = 1; } else if (PI_out <= 0) { PI_out = 0; sat = 2; } else sat=0; y1 = PI_out; y2 = err; y3 = sat; y4 = 1; }// end if }// end if SOC else { y1 = 0; y4 = 0; }

(41) The Hercules C generates the PWM signal, switch (relay) selection signals, possible passive balancing activation signal/signals? for the full module and receives the feedback of the balancing output current signal to close the control loop.

(42) The PWM signal will control? the isolated flyback DC/DC converter in order to generate the desired amount (magnitude) of current to re-charge the selected cell.

(43) With reference to FIG. 5A through G there is shown the interface with the Hercules C evaluation board, and also the power supply needed to generate the different supply levels, including the isolated voltage (such as 5V) needed for the output current and cell voltage measuring operational amplifiers. The schematic in FIG. 2 also shows the interface components needed to manage the different voltage levels in all the signals present in this embodiment of the invention. The analog and digital signals can be routed to different pins in the C to allow compatibility with different combinations and configurations.

(44) In this embodiment of the invention, the connection with the TI BQ76PL536EVM is done with an SPI bus and some digital signals, and it is present in connector J1 and J2.

(45) With reference to FIG. 6A through E there is shown the Dual Switch isolated flyback converter. To manage both MOSFETs PWM signal, the IC U114 (UCC27201) acts as a High and Low Gate Driver, receiving the PWM signal from the C.

(46) The current sensor used to send the current signal to the microcontroller is in this embodiment a combination of a 25 mOhm shunt resistor and two analog amplifiers. The first one in the chain is the AMC1200-Q1. It is a balanced isolation amplifier with a fixed gain of 8 and it is powered with 5V by the TMV-1205SHI isolated DC/DC converter. The balanced output of this isolation amplifier is amplified again by the INA332 (11 for the current measurement and 5 for the voltage measurement). Both signals are given to the HERCULES C ADC inputs on Ieq_Out and Veq_Out ports. The Module voltage is also measured by the resistor divider network and is given to the uC on Vmod port.

(47) In thisand possibly also further embodiments of the invention, a Wurth WE750312503 isolation transformer for the flyback converter that works between 36V and 72V input voltage is used. The selected topology is the dual switch flyback and the MOSFETs reference is STN2NF10. The output diode D19 (PMEG3030EP) has been selected for its low Vf to reduce conduction looses.

(48) With reference to FIG. 7A through G there is shown an embodiment of a Relay selection circuitry provided with de-multiplexer to avoid having 2 relays connected at the same time to different parts of the cell that would lead to a short circuit between two or more cells. The selection of the relay that connects one single cell to the flyback output is done with a logic circuitry based on SN74HC238D de-multiplexers. In this way it is ensured that only one single relay is activated at the same time, avoiding dangerous short-circuits between cells. Finally the relay is driven by a ULQ2003A darlington array that manages the relay coil activation.

(49) There last two relays (RLY17 and RLY18) are in this embodiment used to connect a resistor in series with a single cell or with the full module to allow passive balancing and thus obtaining the Hybridized Balancing prototype. The relay selected for this application is the IMR6

(50) Software Design

(51) The HERCULES C has been configured and programmed in order to control the flyback converter, using the following peripherals: General Purpose In/Out (GPIO) pins to manage the logic circuitry that controls the Relays. Analog to Digital Converter (ADC) Module to measure the output current. High-End Timer (HET) Module to generate internal interruptions for the control algorithm. Enhanced Pulse Width Modulator (ePWM) Module to generate the PWM signal.

(52) The uC peripherals are configured as follows:

(53) GIO: PORT A (A5, C2, C1, E1, A6, B5, H3, M1)

(54) ADC: JUMPER J8 TO SELECT ADREFHI 3.3V PIN->ADC1IN2 (V18) TRIGGER->HET1 8 RESOLUTION->12BIT SAMPLE TIME->1 s

(55) HET: PIN->HET1 8 (E18) PWM1 PERIOD->500 s

(56) ETPWM: PERIOD->100 kHzPIN->ETPWM6B (P2)

(57) With the ePWM module the HERCULES C generates a PWM signal capable to control the flyback converter. With the HET Module a signal is generated to trigger the conversion of the ADC at an appropriate frequency, such as 2 kHz, which captures the measured value of the current sensor. The C receives the analog signal from the current sensor in order to close the control loop, performing as a PI controller. Using the GPIO of the Port A, the C selects the cell to be recharged. If desired, the C also enables the passive balancing for one cell or for the full module.

(58) Tests have been carried out with the Dual Switch flyback converter charging one Cell at a fixed and controlled current of 1 A. The core of the active balancing circuitry is the isolated flyback converter. The flyback converter is controlled by the HERCULES C with a PWM signal (ETPWM 6B pin) and the control loop is feed by the analog signal that corresponds with the output current (AD1IN2 pin).

(59) The HERCULES uC is able to select the cell that needs to be recharged thanks to the logic circuitry attached to GIOA port. Lines GIOA0 to GIOA3 are used to select the cell from 1 to 16 and GIOA5 is used to enable the output from the 3.3V-to-5V buffer and GIOA4 is used to enable the output of the de-multiplexers. Both enable signals are active low signals.

(60) Once the cell is selected, the C starts to control the PWM signal of the flyback converter in order to recharge the selected cell at 1 A rate. The cell model used in these tests is the Kokam SLPB90255255H.

(61) The measurements done during the balancing tests show that the circuitry and control code designed are able to control the amount of current injected into the selected cell.

(62) The precision of the output current value is 1.5%.

(63) The efficiency of the power conversion in the flyback converter is above 82.5% in most input/output conditions, arriving to efficiency peaks of around 87.5% when the input voltage is around 55V.

(64) Passive balancing has also been tested by connecting one 4 resistor (5 W) to discharge a single cell at a rate of around 1 A, and one 68 resistor (100 W) to discharge the full 16 cell module at a rate of around 1 A. It is understood that different resistor values could be used and that passive balancing could be carried out by other means than by resistors.

(65) Simulation Results.

(66) In the following results of PSIM simulations for 16 and 8 cells modules are shown.

(67) Referring to FIG. 8 there is shown results obtained for a simulation of a balancing process of 1 cell that needs to go from a 90% SOC until a 95% SOC. The input voltage for the flyback is 64.45V, equivalent to 16 cells where 15 cells are charged at SOC 95% and 1 cell is charged at 90%. This last cell is the one that will be balanced.

(68) The current IoutDC is increased until it reaches 1 A and then remains steady until the SOC reaches a charge of 95%, then it stops.

(69) The SOC (SOC_1) and the Cell Voltage (VoutDC) as a function of time are also shown.

(70) Finally the bottom graph of FIG. 8 shows the power conversion efficiency in the simulation considering conduction losses, during the time when the flyback converter is ON. The value of the efficiency in this simulation is 89%.

(71) Referring to FIG. 9 there is shown results obtained for a simulation of a balancing process of 1 cell that needs to be charged from a 90% SOC until a 95% SOC. The input voltage for the flyback is 32.18V, equivalent to 8 cells where 7 cells are charged at 95% SOC and 1 cell is charged at 90%. This last cell is the one that will be balanced. The rest of the signals are the same as for the results shown in FIG. 8.

(72) In summary, it can be seen from the plots shown in FIGS. 8 and 9 that the controlled flyback power supply according to an embodiment of the invention is able to recharge the specific cell at a constant current of 1 A until its SOC reaches the desired value.