CIRCUIT FOR A BUS SYSTEM AND METHOD FOR OPERATING A CIRCUIT

Abstract

A circuit for a bus system. The circuit includes: a measuring circuit, which is configured to measure a first resistance value between two bus-side terminals of the circuit; an ascertainment circuit, which is configured to ascertain a second resistance value as a function of the first resistance value; and a resistive circuit, which is configured to set a resistor connectable between the two bus-side terminals to the second resistance value.

Claims

1-10. (canceled)

11. A circuit for a bus system, comprising: a measuring circuit configured to measure a first resistance value between two bus-side terminals of the circuit; an ascertainment circuit configured to ascertain a second resistance value as a function of the first resistance value; and a resistive circuit configured to set a resistor connectable between the two bus-side terminals to the second resistance value.

12. The circuit as recited in claim 11, wherein the ascertainment circuit is configured to increase the second resistance value when the first resistance value decreases.

13. The circuit as recited in claim 11, wherein the measuring circuit is configured to ascertain at least one time window as a function of a message received via the two bus-side terminals and as a function of an a priori known position in relation to the received message, the resistive circuit being configured to set the resistor connected between the two bus-side terminals to a last ascertained second resistance value during the ascertained time window, and the measuring circuit is configured to wait out a waiting period after a beginning of the time window and subsequently to the waiting period and, still before the end of the time window, to measure the first resistance value between the two bus-side terminals during a measurement period.

14. The circuit as recited in claim 13, wherein the length of the waiting period and/or the measurement period is one bit time or shorter.

15. The circuit as recited in claim 13, wherein the resistive circuit is configured to ascertain the time window for connecting the resistor, and to connect the resistor during the time window using the last ascertained second resistance value, and the measuring circuit is configured to ascertain the first resistance value during the time window.

16. The circuit as recited in claim 11, wherein the ascertainment circuit is configured to ascertain the second resistance value as a function of a comparison of the first resistance value to a setpoint value for the first resistance value.

17. The circuit as recited in claim 11, wherein the ascertainment circuit is configured to ascertain the second resistance value using a lookup table as a function of the first resistance value.

18. The circuit as recited in claim 17, wherein the circuit further comprises: a configuration circuit configured to provide a number of user stations of the bus system; wherein the ascertainment circuit is configured to ascertain the second resistance value using the lookup table as a function of the first resistance value and as a function of the provided number of user stations.

19. A transceiver for a user station of a bus system, the transceiver comprising: a circuit, including: a measuring circuit configured to measure a first resistance value between two bus-side terminals of the circuit; an ascertainment circuit configured to ascertain a second resistance value as a function of the first resistance value; and a resistive circuit configured to set a resistor connectable between the two bus-side terminals to the second resistance value.

20. A method for operating a circuit for a bus system, the method comprising the following steps: measuring a first resistance value between two bus-side terminals of the circuit; ascertaining a second resistance value as a function of the first resistance value; and setting a resistor connectable between the two bus-side terminals to the second resistance value.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] FIGS. 1, 2a, 2b each show a circuit in schematic form in accordance with the present invention.

[0016] FIG. 3 shows a schematic protocol diagram in accordance with the present invention.

[0017] FIGS. 4a, 4b each show a schematic block diagram in accordance with the present invention.

[0018] FIG. 5 shows an exemplary bus system in schematic form in accordance with the present invention.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0019] FIG. 1 shows a circuit 100 for a bus system in accordance with an example embodiment of the present invention. Circuit 100 includes a measuring circuit 101, an ascertainment circuit 102, and a resistive circuit 104, measuring circuit 101 and resistive circuit 104 being situated in parallel to one another between two bus-side terminals 106 and 108 of circuit 100. Circuit 100 is connected to a first bus line CAN H via a terminal 106. Circuit 100 is connected to a second bus line CAN L via terminal 108. A voltage V DIFF drops between the two terminals 106 and 108.

[0020] Measuring circuit 101, ascertainment circuit 102, and resistive circuit 104 are designed, for example, as an ASIC, FPGA, or as a discrete circuit. Furthermore, measuring circuit 101, ascertainment circuit 102, and resistive circuit 104 include, for example, a processor, which is equipped with software to carry out the particular functions defined by software. Of course, mixed forms including a physical circuit and the processor on which the software is executed are also possible. The software is stored on a corresponding memory element. Circuit 100 is, for example, part of a transceiver for a user station of a bus system. In another specific embodiment, circuit 100 is designed in addition to an existing transceiver.

[0021] Shown in schematic form, resistive circuit 104 includes a switch 110 and a resistor 112 situated in series thereto. Of course, resistive circuit 104 may also be designed differently and may include, for example, a MOSFET. Resistor 112 is connected, for example, between the two bus-side terminals 106, 108 if a state transition takes place from a first state (for example, dominant) of an absolute value of voltage V DIFF to a second state (for example, recessive), for example, within an ascertained time window. Resistive circuit 104 is used to suppress or damp oscillations of voltage V DIFF.

[0022] Measuring circuit 101 ascertains a first resistance value R1 between the two bus-side terminals 106 and 108. The ascertainment of first resistance value R1 takes place, for example, at regular intervals. Thus, the ascertainment may be carried out, for example, in each data frame or only once per minute. This first resistance value R1 reflects the total resistance connected between the two terminals 106 and 108, which results, for example, due to the parallel connection of a bus resistance Rb and resistor 112. Ascertainment circuit 102 ascertains a second resistance value R2 for resistor 112 of resistive circuit 104 as a function of supplied first resistance value R1. Upon the start of the circuit, a predefined value is used for second resistance value R2. Second resistance value R2 is applied to resistive circuit 104 to set resistor 112 to second resistance value R2. Resistive circuit 104 connects resistor 112 between the two terminals 106 and 108 either on request from the outside or independently, resistor 112 being set to last ascertained resistance value R2.

[0023] FIG. 2a shows circuit 100, measuring circuit 101 activating resistive circuit 104 with the aid of a signal S1, so that in the measurement subsequently carried out, the resistor connected between the two terminals 106, 108 is also measured. Measuring circuit 101 ascertains at least one time window as a function of a message which is received via the bus or which is transmitted on the bus, and as a function of a previously known position in relation to the message. For this purpose, knowledge about the protocol is used, in particular the presence of a message and its position with respect to time are ascertained as a function of voltage V DIFF. Resistive circuit 104 is operated with the aid of signal S1 in such a way that during the ascertained period, second resistance value R2 is set for the resistor connected between terminals 106, 108. After the resistor is interconnected, a waiting period is waited out and subsequently the first resistance value is measured with the aid of measuring circuit 101 during a measurement period. During the measurement period, a profile of the first resistance value is ascertained and the minimum of the profile is output as the first resistance value. Both the waiting period and the measurement period are, for example, one nominal bit time long, because the nominal bit time is made up of approximately 70% of a round-trip time which necessarily has to be waited out. In another example, the waiting period and also the measurement period are shorter than the nominal bit time.

[0024] A configuration circuit 202 provides a number 204 of user stations of the bus system. Number 204 may either be preconfigured or the configuration circuit independently ascertains number 204 of user stations. For the independent ascertainment of number 204, configuration circuit 202 exchanges messages with other bus users. Ascertainment circuit 102 may, for example, define second resistance value R2 to be shorter for an increased number 204 than if a reduced number 204 is present.

[0025] FIG. 2b shows circuit 100. In contrast to FIG. 2a, a signal S2 is transmitted from resistive circuit 104 to measuring circuit 101. Resistive circuit 104 independently ascertains the time window for connection of the resistor. The ascertainment of the time window may be considered to be a basic function for operating the resistive circuit. Via signal S2, measuring circuit 101 is signaled that the resistor is connected; the time window is thus transferred to measuring circuit 101. As long as signal S2 signals the connection of the resistor, the measuring circuit carries out a measurement of the first resistance.

[0026] FIG. 3 shows a structure of a CAN message and the temporal arrangement of the measurement of the first resistance value. The message shown includes the following fields: start of frame (SOF), message identifier (MID), remote transmission request (RTR), control field (CONTROL), data field (DATA), CRC field (CRC), acknowledge field (ACK), end of frame (EOF). For example, at the beginning of third bit B3, the resistor of resistive circuit 104 is connected to carry out the measurement of the first resistance value in subsequent fourth bit B4. Alternatively or additionally, the connection of the resistor of the resistive circuit and the measurement of the first resistance value take place within the intermission field, which is located between end of frame EOF and start of frame SOF. Third and fourth bit B3, B4 and the intermission field are particularly well suitable due to the recessive bus level for connection of the resistor of resistive circuit 104.

[0027] FIG. 4a shows ascertainment circuit 102 in a schematic detail. A block 402 generates a setpoint value R1s and supplies it to an addition point 404. Measured first resistance value R1 is subtracted at addition point 404 from setpoint value R1s to ascertain actuating variable d. A controller 406 ascertains second resistance value R2, which functions in the present case as a control variable, as a function of actuating variable d. Controller 406 may be, for example, a PID controller or a differently designed controller.

[0028] FIG. 4b shows ascertainment circuit 102 in a schematic detail. Configuration circuit 202 provides number 204 of bus users to a block 410. Block 410 encompasses a lookup table, which ascertains second resistance value R2 as a function of number 204 and as a function of first resistance value R1. The lookup table is stored in a memory element. A still simpler variant is also possible in which resistance R2 is ascertained with the aid of block 410, which contains a lookup table, as a function of resistance R1.

[0029] FIG. 5 shows a bus system configured by way of example including two user stations 502, 504. Each of user stations 502, 504 encompasses particular circuit 100, which is connected using first terminal 106 to first bus line CAN H and using second terminal 108 to second bus line CAN L. Bus lines CAN H and CAN L are connected to one another at their ends via a particular terminating resistor Rb1 and Rb2. By connecting and disconnecting the resistor between bus-side terminals 106, 108, particular circuits 100 of user stations 502 and 504 cause oscillations in the event of a state change from dominant to recessive to be damped and thus reduced. Bus system 500 operates according to the exemplary embodiments according to the CAN standard, for example, ISO 11898. Circuit 100 and the operation of the circuit may also readily be transferred to other bus systems, however. In addition, other bus topologies are also possible.