H-BRIDGE POWER AMPLIFIER ARRANGEMENT

Abstract

An H-bridge power amplifier arrangement with envelope tracking is disclosed. The power amplifier arrangement comprises four elements form the four corner bars of a first H-bridge structure with a load formed as the cross bar of the first H-bridge structure. The power amplifier arrangement further comprises a rectifier circuit coupled between the first positive power supply and the third positive power supply configured to recycle the sinking envelope current.

Claims

1. An H-bridge power amplifier arrangement with envelope tracking comprising: a first element comprising a first, a second and a third terminals, wherein the first terminal is configured to receive an envelope signal (Ven) as a control signal, the second terminal is coupled to a first positive power supply (V.sub.H), and the first element is configured to generate a sourcing envelope current; a second element comprising a first, a second and a third terminals, wherein the first terminal is configured to receive an inverse-phase version of the envelope signal (Ven), the second terminal is coupled to the first positive power supply (V.sub.H), and the second element is configured to generate a sinking envelope current to compensate a redundant sourcing current generated by the first element; a third element comprising a first, a second and a third terminals, wherein the first terminal is configured to receive input signals (V.sub.RF), the second terminal is coupled to the third terminal of the second element to form a first interconnection node, the third terminal is coupled to a negative power supply (V.sub.N), and the third element is configured to amplify the received input signals, and the first interconnection node is coupled to a second positive power supply (V.sub.CM); a fourth element comprising a first, a second and a third terminals, wherein the first terminal is configured to receive an inverse-phase version of the input signals (V.sub.RF), the second terminal is coupled to the third terminal of the first element to form a second interconnection node, the third terminal is coupled to the negative power supply (V.sub.N) via a third positive power supply (V.sub.L), and the fourth element is configured to amplify the received inverse-phase version of the input signals, and the second interconnection node is coupled to the second positive power supply (V.sub.CM); a load coupled between the first and second interconnection nodes to form a path for both the sourcing and sinking envelope currents; wherein the first, second, third and fourth elements form the four corner bars of a first H-bridge structure with the load formed as the cross bar of the first H-bridge structure; and the H-bridge power amplifier arrangement further comprising: a rectifier circuit coupled between the first positive power supply (V.sub.H) and the third positive power supply (V.sub.L) configured to recycle the sinking envelope current by converting a redundant sinking current power to a direct current, DC, voltage and feeding the DC voltage to the first positive power supply (V.sub.H) with the same voltage level.

2. The power amplifier arrangement according to claim 1, wherein the voltages of the first, second and third positive power supplies (V.sub.H, V.sub.CM, V.sub.L) are ranging in high, middle and low levels with respect to each other.

3. The power amplifier arrangement according to claim 1, wherein the first, second, third and fourth elements are transistors or switches.

4. The power amplifier arrangement according to claim 3, wherein the first and third elements are controlled to be on, the second and fourth elements are controlled to be off.

5. The power amplifier arrangement according to claim 3, wherein the first and second elements are controlled to be off, the third and fourth elements are controlled to be on.

6. The power amplifier arrangement according to claim 3, wherein the first, second third and fourth elements are controlled to be on.

7. The power amplifier arrangement according to claim 1, wherein the input signals are analog radio frequency signals, whose frequency is much higher than the envelope signal frequency.

8. The power amplifier arrangement according to claim 1, wherein the input signals are binary digital signals.

9. The power amplifier arrangement according to claim 1, wherein the input signals are digital signals comprising multiple levels.

10. The power amplifier arrangement according to claim 9, wherein the power amplifier arrangement comprises multiple H-bridge structures in cascade, and wherein the power amplifier arrangement comprises more than four elements to form the four corner bars of H-bridge structures cascaded with the four corner bars of the first H-bridge structure.

11. An electronic circuit comprising a power amplifier arrangement according to claim 1.

12. An electronic apparatus comprising a power amplifier arrangement according to claim 1.

13. The electronic apparatus according to claim 12, wherein the electronic apparatus is a wireless communication device for a cellular communication system.

14. The electronic apparatus according to claim 12, wherein the electronic apparatus is a radio base station for a cellular communication system.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Examples of embodiments herein are described in more detail with reference to attached drawings in which:

[0027] FIG. 1 is a schematic block illustrating an H-bridge power amplifier arrangement according to embodiments herein;

[0028] FIG. 2 is a simplified schematic view of an example implementation of a linear H-bridge power amplifier arrangement according to embodiments herein;

[0029] FIG. 3 is a diagram illustrating envelope modulation scheme according to embodiments herein;

[0030] FIG. 4 is a schematic block illustrating a Direct Digital to RF Conversion Envelope Tracking (DDRFET) system with a digital H-Bridge ET PA scheme;

[0031] FIG. 5 is a schematic block illustrating multiple H-bridges power amplifier arrangement according to embodiments herein;

[0032] FIG. 6 is a block diagram illustrating an electronic circuit or apparatus in which embodiments herein may be implemented.

DETAILED DESCRIPTION

[0033] FIG. 1 shows an H-bridge power amplifier arrangement 100 with envelope tracking according to embodiments herein, hereafter refereed as H-bridge ET PA. Unlike traditional prior arts which treat the envelope tracking system as a supply modulator and an RF power amplifier as two separated elements, the present embodiment considers supply modulator and RF power amplifier as a whole via a novel H bridge structure for integration. As shown in FIG. 1, the H-bridge power amplifier arrangement 100 comprises a first element A comprising a first, a second and a third terminals. The first terminal is configured to receive an envelope signal Ven as a control signal, the second terminal is coupled to a first positive power supply V.sub.H. The first element A is configured to generate a sourcing envelope current represents the main power amplification supply current sourcing.

[0034] The H-bridge power amplifier arrangement 100 further comprises a second element B comprising a first, second and third terminals. The first terminal is configured to receive an inverse-phase version of the envelope signal Ven, the second terminal is coupled to the first positive power supply V.sub.H. The second element B is configured to generate an inverted polarity supply or generate a sinking envelope current to compensate a redundant sourcing current generated by the first element A.

[0035] The first and second elements A and B are very high frequency (VHF) band operating transistors or circuitry to handle envelope domain signals.

[0036] The H-bridge power amplifier arrangement 100 further comprises a third element D comprising a first, second and third terminals. The first terminal is configured to receive input signals V.sub.RF, the second terminal is coupled to the third terminal of the second element B to form a first interconnection node 101, the third terminal is coupled to a negative power supply V.sub.N. The third element D is configured to amplify the received input signals. The first interconnection node 101 is coupled to a second positive power supply V.sub.CM via e.g. a diode.

[0037] The H-bridge power amplifier arrangement 100 further comprises a fourth element C comprising a first, second and third terminals. The first terminal is configured to receive an inverse-phase version of the input signals V.sub.RF, the second terminal is coupled to the third terminal of the first element A to form a second interconnection node 102, the third terminal is coupled to the negative power supply V.sub.N via a third positive power supply V.sub.L. The fourth element C is configured to amplify the received inverse-phase version of the input signals. The second interconnection node 102 is coupled to the second positive power supply V.sub.CM via e.g. a diode.

[0038] The third and fourth elements D and C are RF power transistors, which receive its power supply both current and voltage from the first and second elements A and B respectively. The third element D is the main RF power amplification stage for RF input signals. The fourth element C is weak auxiliary RF power amplifier to amplify the inverse version of the RF signals for signal correction due to redundant power supply effect from the first element A. The third element D is always ON for power amplification, whereas the fourth element C is periodically ON and OFF during envelope cycles for signal correction and sinking process.

[0039] H-bridge structure is so named because it has four elements at the corners of an H and an RF load forms the cross bar. So the H-bridge power amplifier arrangement 100 further comprises a load 103 coupled between the first and second interconnection nodes 101/102 to form a path for both the sourcing and sinking envelope currents. The first, second, third and fourth elements form the four corner bars of a first H-bridge structure with the load 103 formed as the cross bar of the first H-bridge structure.

[0040] The first, second, third and fourth elements A, B, D, C may be transistors, current sources (CSs) or switches. Anything that can carry a current will work, from four single-pole-single-throw (SPST) switches, one double-pole-double-throw (DPDT) switch, to enhancement mode power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and Bipolar Junction Transistors (BJTs). H-bridge architecture will absorb the drain-source parasitic capacitance (Cds) related distortion and efficiency degradation issue.

[0041] The H-bridge power amplifier arrangement 100 further comprises a rectifier circuit 104 coupled between the first positive power supply V.sub.H and the third positive power supply V.sub.L configured to recycle the sinking envelope current by converting a redundant sinking current power to a direct current (DC) voltage and feeding the DC voltage to the first positive power supply V.sub.H with the same voltage level.

[0042] The H-bridge power amplifier arrangement 100 with envelope tracking may be either linear mode or switch mode which depends on what kind of the ABCD elements and input signal pattern will be applied. Therefore, the present embodiment does not limit to neither linear/analog nor switch/pulse mode signal application scenarios.

[0043] In operation, the four elements/CSs/switches ABCD are turned on in pairs, either A and D, or C and D. However what is different from any other H-bridge prior arts who never both switches ON the same side of the H-bridge, the present embodiment utilizes both ON but different gain or scaling factor and phase to let one pair of elements e.g. B and C to sink the redundant current generated from the other envelope tracking pair e.g. A and D. It means the scenario that A may provide more current than what D demand. Then it might introduce distortion via supply modulation effect to the final RF PA output. When both elements/CSs/switches on one side of the H-bridge are turned on, it will create a short circuit between the power source positive supply and power source negative supply. Although this phenomena is called shoot through in the Switch-Mode Power Supply (SMPS) prior arts, it can be utilized under envelope tracking scheme to sink the redundant current generated and alleviate supply modulation related distortion by means of controlling On and Off condition/intervals and the current amplitude of shoot through. If the H-bridge is sufficiently powerful it will absorb that differential load and the power sources will simply drain quickly. Hence, there is a sinking current recycling rectification scheme to handle the wasted power and boost system efficiency as shown in FIG. 1.

[0044] Therefore there are three signal paths in the H-bridge power amplifier arrangement 100. Firstly, an envelope tracking sourcing path, i.e. the first element A, the load 103 and the third element D, which provides the main ET PA function supplied by dual supply rails, i.e. the first positive power supply V.sub.H and the second positive power supply, i.e. the common mode supply V.sub.CM. Secondly, an envelope tracking sinking path, i.e. the second element B, the load 103 and the fourth element C, which provides the signal correction due to the redundant current generated from the sourcing path to provide the auxiliary sinking function for ET PA to improve its linearity by triple supply rails, i.e. the first, second and third positive power supplies V.sub.H, V.sub.CM, V.sub.L. Finally, a sinking power recycling path, i.e. the rectifier circuit 103, which provides sinking power reuse for the whole ET PA system via a RF to DC rectification process.

[0045] For supply rails, there are four supplies nominal. However, in practice it can be simplified to fewer numbers. They are power source positive V.sub.H, power source negative V.sub.N, common mode supply V.sub.CM which provide the root mean squared supply voltage level of ET PA output; and low supply source V.sub.L which is provided for power recycling scheme functionality. The first, second and third positive power supplies V.sub.H, V.sub.CM, V.sub.L may be ranging in high, middle and low levels with respect to each other.

[0046] To power the H-bridge power amplifier arrangement 100, it is necessary turn on two elements that are diagonally opposed. In the FIG. 1, when the first element A and third element D are turned on. The current flow is shown in a solid line. At the same time, the other diagonally opposed path will not be turned on until the redundant current is generated, as shown in a dashed line. Then, it will slightly be turned on and drain the redundant current into the recycling path for RF to DC rectification. The condition of triggering sinking path working is realized by controlling the dynamic gate bias driven levels.

[0047] Both the sourcing and sinking current will flow through the load 103. The current flows and the load begins to turn in a positive direction when the sourcing path starts to work. On the other hand, when turning on the second and fourth elements, current flows the other direction through the load 103 and counteracts the distortions on the load 103 caused by the redundant sourcing current. Here, the load 103 can be seen as a summing node, which have the positive direction current and the opposite direction current flowing through at the same time. However, when there is NO redundant current generated, the opposite current flowing is zero and the sinking path is totally shut down.

[0048] In theory, the operation quadrants of the present embodiment may be very flexible. It depends on how to control the H-bridge power amplifier arrangement 100 well for efficiency and linearity trade-off. If each element can be controlled independently then some flexible control and configuration schemes with the H-bridge ET PA may be realized. Hence, an H-bridge in the present embodiment should be a four quadrant device. For example, if it is built out of a single DPDT switch, it may be only controlled forward or reverse. As each switch has one of two states, and there are four switches, there are 16 possible states. However, since any state that turns both switches on one side at some moments is no longer bad, there are in fact only three useful states, i.e. three operation modes, where the transistors are turned on, compared to any other H-bridge prior arts, as shown in Table 1.

TABLE-US-00001 TABLE 1 A B C D Quadrant Operation Description On Off Off On Perfect ET operation without any redundant current generated in sourcing path. No sinking is needed. Off On On Off ET not working, but sinking path ON. An error state needs to be avoided. On On Off Off Supply modulator is all ON; but RF PAs are all OFF. ET PA does not work. Off Off On On Supply modulators are all OFF; but RF PAs are all ON with fixed DC supply V.sub.CM, working for low power mode. This is a state which transformed from envelope tracking (ET) to average power tracking (APT). On On On On ET operation with any redundant current generated in sourcing path. Sinking function is needed to remove distortion.

[0049] Therefore, based on the quadrant operation descriptions in Table 1, according to some embodiments herein, the first and third elements A and D may be controlled to be on, the second and fourth elements B and C may be controlled to be off.

[0050] According to some embodiments herein, the first and second elements A and B may be controlled to be off, the third and fourth elements D and C may be controlled to be on.

[0051] According to some embodiments herein, the first, second, third and fourth elements A, B, D, C may be controlled to be on.

[0052] The present embodiment may provide additional benefit to traditional ET PA by adding sinking path function to linearize the ET PA and mode transition from ET to APT when the average power requirement is greatly reduced.

[0053] The ET and APT mode transition is widely realized by turning off the linear part of hybrid structure supply modulator. Only switch mode part will work to provide DC supply. In present embodiment, V.sub.CM is replacing switch mode part in prior art hybrid supply modulator, V.sub.CM may be variable and changing slowly to realize APT function to satisfy ET and APT requirements.

[0054] All in all, the present embodiment is addressing the sinking current issue of all prior arts ET solutions. Most of them are using sinking current to keep high linearity of envelope tracking supply modulator. However, the sinking current are wasted or recycled to power supply. All of these not direct reuse the sinking current. Hence, the present embodiment proposed to use H-bridge envelope tracking to make the sinking current direct to RF load for signal correction and for further efficiency enhancement as shown in FIG. 1. On the other hand, the present embodiment can be easily transferred into APT mode by simply turning off supply modulation elements e.g. A and B, using V.sub.CM as DC supply voltage directly and V.sub.CM may also be slowly changeable supply source.

[0055] The technical implementation of the present invention can be categorized as two types as linear mode and switch mode. Linear mode H-Bridge ET PA handles analog signal with linear amplification; switch mode H Bridge ET PA handles pulse mode stimulus as full digital transmitter.

[0056] FIG. 2 shows an example implementation of a linear H-Bridge ET PA. The input signal V.sub.RF is an analog RF signal, whose frequency is much higher than the envelope signal frequency. The first and second elements A and B are transistors working at envelope frequency e.g. DC 100 MHz; while the fourth and third elements C and D are RF power transistors working at high frequencies e.g. 7002700 MHz for telecommunications purpose. Between the envelope domain and RF domain configurations, there is common mode voltage source V.sub.CM which is typical root mean squared value of the ET PA output. The value of V.sub.CM may be approximate half or lower values of the sum of positive and negative supply rails V.sub.H and V.sub.N. A pair of Schottky diodes Diode is employed between V.sub.CM and the joint junction to provide dual supply rails for envelope tracking supply modulation. The principle of this operation is that if the instant supply voltage is greater than V.sub.CM value, the first element A will provide tracking supply to the third element D. If instant supply voltage is equal or lower than V.sub.CM, then the first element A will be shut down and V.sub.CM is supplied via the Schottky diode to the third element D. In this case, the lower part of ET supply will be clipped by V.sub.CM values. While the instant supply voltage lower than V.sub.CM supply waveform will be provided by the sinking path BC, which will provide some compensation of troughs of the ET PA system. However, the second and fourth elements B and C are not working all the time, when the envelope supply waveform is below a certain threshold, it will trigger them to turn on to sink current. The sinking current is not go to the negative power source or ground directly. There is a lower supply source V.sub.L, which is lower than the minimum value of the ET supply voltage V.sub.H. V.sub.L is inserted between the source of C transistor and the negative power supply V.sub.N. There is a rectifier to pull out the sinking power from V.sub.L to a feedback path named sinking current recycling path, which can avoid dissipate too much power by sinking current operation. The recycling circuitry is a rectenna rectifier circuit to convert RF power into proper DC level which may be suitable to be provided to V.sub.H and reused again.

[0057] The RF transistors C and D may be matched into either linear mode power amplifier such as Class-A/AB/B or switch mode power amplifier such as Class-E/F/F.sup.1/J/P etc. to boost the peaking efficiency of the ET PA system. Linearization scheme such as digital pre-distortion may be added into the chains of the fourth and third elements C and D as well for linearity enhancement.

[0058] FIG. 3 shows transistors A and B plus Diode envelope modulation scheme according to embodiments herein, where (a) is linear mode H-bridge configuration and (b) is switch mode H-bridge configuration. As shown in FIG. 3, for the envelope domain signal processing, transistor A/B plus Diode modulation scheme may provide better supply modulation efficiency than single A and B supply modulation scheme, because it uses multiple supply rails and switching between them to boot average efficiency to fit for the probability density function (PDF) of high peak to average power ratio (PAPR) envelope amplifications. To deal with efficiency challenge from high-PAPR signal, the present embodiments have usually two supply voltage levels as V.sub.H and V.sub.CM, they can adapt power supply voltages to fit the required output power to some extent. When the amplitude of the output voltage is lower than V.sub.CM, then transistor A will be shut down and V.sub.CM is supplied via the Schottky diode to transistor D. When the amplitude of the output voltage is higher than V.sub.CM, then transistor A is turned on, V.sub.H will be supplied to transistor D. The higher and lower supply voltages V.sub.H and V.sub.CM are defined by both the maximum output power required and the minimum supply voltage that the supply modulation circuitry can operate above a predefined threshold for the total harmonic distortion (THD) performance defined. Switching supply voltages between two rails minimizes the amount of energy that needs to be dissipated by reducing the difference between the supply voltage and the output voltage. The ratio between the higher and lower supply voltages V.sub.CMm/V.sub.H may be adjusted to move peak efficiency point to fit to the average envelope power and achieve the best efficiency. With the intention to move peak efficiency point to tolerate more back-offs, the V.sub.CM/V.sub.H ratio may be set to a smaller value, e.g. 0.5, so the peak efficiency point is moved to lower voltage region. Whereas, there may be a peak efficiency drooping effect and deeper drop-down between two peak-efficiency points while tuning V.sub.CM/V.sub.H ratio value into smaller values because of various non-ideal effects in practical components, backed off peak efficiency points may droop to some extent which may cause overall efficiency deviation from theoretical values.

[0059] According to some embodiments herein, the H-bridge ET PA may be implemented as fully digital solution which may be seen as a digital polar transmitter from system perspective.

[0060] FIG. 4 shows a Direct Digital to RF Conversion Envelope Tracking (DDRFET) system with a digital H-Bridge ET PA scheme 400. The input signal may be binary digital signals or multiple levels digital signals with various digital modulation schemes. The base band digital signal, I-Q Data, is processed in a FPGA/ASIC 410 under synchronization of a reference clock 420. Then it outputs serial data and clock in differential mode. After digital flip flop circuitry DFF 430, digital envelope and RF signal are split and synchronized for the two arms 441, 442 of the H bridge 440. The H bridge 440 outputs the differential signal and being low pass filtered in LPF 450 to filter out the harmonic components to restore the analog waveform of RF/Microwave signal. A balun 460 works as a differential to single end converter to connect the antenna 470 and the H-bridge power amplifier system via a bandpass reconstruction filter 480.

[0061] Table 2 shows an example for Code Division Multiple Access (CDMA) modulation, where signal levels, H-Bridge gain reduction and peak to average power ratio (PAPR) of various digital signal modulation schemes are shown. By controlling the number of digital levels and digital encoding schemes, the PAPR and gain reduction may be achieved by selecting different signal coding format. From this perspective, the advantage of digital H-bridge ET PA may be more flexible to advanced system such as 5G and beyond.

TABLE-US-00002 TABLE 2 Gain Reduction Psat/Pavg Signaling Format Generation Modulation Levels (dB) (dB) Conventional Analog analog upmix CDMA 0 8 Binary PWM digital upmix 2 13.5 13.5 Binary PDM direct launch 2 7.9 7.9 Ternary PDM direct launch 3 1.7 6.1 Quaternary PDM direct launch 4 0.6 6.1 Quinternary PDM direct launch 5 0.25 6.05

[0062] Multiple levels signaling, such as ternary PDM, quaternary PDM, quintenary PDM with 3, 4, 5 levels respectively as shown in FIG. 4, has following advantages: [0063] Less gain reduction since gain reduction is detrimental to Power Added Efficiency (PAE) [0064] Well suited for non-constant envelope modulation since binary formats, i.e. constant envelope, are poorly suited for non-constant envelope modulation [0065] Ternary pulse-density modulation (PDM) offers good compromise between performance and system complexity.

[0066] The principle of the multi-level signaling may be explained with reference to FIG. 5, where a multiple H-bridges power amplifier arrangement 510 together with digital signal processing unit is shown. To handle multilevel signals, the power amplifier arrangement 510 may comprise multiple H-bridge structures in cascade. The first H-bridge structure comprises transistors Q1-Q4 to handle signal levels V1-V4, the second H-bridge structure comprises transistors Q5-Q8 to handle signal levels V5-V8. The two H-bridge structures share the load 512. So the power amplifier arrangement may comprise multiple elements, e.g. more than four elements to form the four corner bars of a second H-bridge structure cascaded with the four corner bars of the first H-bridge structure

[0067] As shown in FIG. 5, the quadrature digital signals I and Q are up-converted to carrier frequency Fc in a direct digital to RF converter 520, and then converted to 5-level digital signals in a bandpass delta-sigma converter 530. The 5-level digital signals are inputted to a mapper 540 to generate 8 voltage levels which are input signals to the cascaded multiple H-bridges power amplifier 510. Table 3 shows operating states of all 8 transistors in the multiple H-bridges power amplifier 510.

TABLE-US-00003 TABLE 3 State Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 +2 ON OFF OFF ON OFF OFF OFF OFF +1 OFF OFF OFF ON ON OFF OFF ON 0 OFF OFF OFF OFF OFF OFF ON ON 1 OFF OFF OFF OFF OFF ON ON OFF 2 OFF ON ON OFF OFF OFF OFF OFF

[0068] To summarize, according to embodiments herein, some advantages of the H-bridge power amplifier 100, 200, 410, 510 include:

[0069] Simplicity of the ET PA system;

[0070] Enable analog or full digital transmitter under the same transmitter architecture;

[0071] Use sinking current branch to improve linearity of the ET PA system by controlling scheme. The H-bridge structure makes the sinking current direct to the RF load for signal correction and further efficiency enhancement;

[0072] Enable easy ET mode to average power tracking (APT) mode transformation when average output power is greatly backed off by turning off the first and second elements A and B, and using the second positive power supply V.sub.CM directly and changing it slowly to realize APT function; and

[0073] Enable efficiency enhancement by introducing H bridge sinking current recycling.

[0074] The H-bridge power amplifier arrangement 100, 200, 410, 510 according to the embodiments herein may be employed in various electronic circuits or apparatus. FIG. 6 shows a block diagram for an electronic circuit or apparatus 600. The electronic circuit or apparatus 600 comprises an H-bridge power amplifier arrangement 100, 200, 410, 510. The electronic circuit or apparatus 600 may be a transmitter or a transceiver in a cellular communications system/network. The electronic apparatus 600 may comprise other units, where a memory 620, a processing unit 630 are shown. The electronic apparatus 600 may be a user equipment or a mobile device, a wireless communication device, a radio base station for a cellular communication system.

[0075] Those skilled in the art will understand that the H-bridge power amplifier arrangement 100, 200, 410, 510 according to embodiments herein may be implemented by any semiconductor technology.

[0076] When using the word comprise or comprising it shall be interpreted as non- limiting, i.e. meaning consist at least of.

[0077] The embodiments herein are not limited to the above described preferred embodiments. Various alternatives, modifications and equivalents may be used. Therefore, the above embodiments should not be taken as limiting the scope of the invention, which is defined by the appended claims.