Method and circuit for current integration

Abstract

An input current (I.sub.in) is transformed into an output integrated voltage (V.sub.out_int) using a parallel connection of an operational transconductance amplifier and an integration capacitor. The output integrated voltage is reduced by repeatedly discharging the integration capacitor through a feedback loop via a digital-to-analog converter generating feedback pulses, a feedback clock period (T.sub.clk_DAC) defining time intervals between successive rising edges of the feedback pulses. Sampling is performed during an extended feedback clock period (T*) after a lapse of a plurality of feedback clock periods (T.sub.clk_DAC).

Claims

1. A method of current integration, comprising: transforming an input current into an output integrated voltage using a parallel connection of an operational transconductance amplifier and an integration capacitor, reducing the output integrated voltage by repeatedly discharging the integration capacitor through a feedback loop via a digital-to-analog converter generating feedback pulses, a feedback clock period defining time intervals between successive rising edges of the feedback pulses, and sampling during an extended feedback clock period after a lapse of a plurality of feedback clock periods.

2. The method of claim 1, wherein the extended feedback clock period is N times as long as the feedback clock period.

3. The method of claim 1, further comprising: reducing a gain-bandwidth product of the operational transconductance amplifier during sampling.

4. The method of claim 1, further comprising: performing a range check for the output integrated voltage before sampling, the range check being based on a number of feedback pulses prior to sampling.

5. The method of claim 1, wherein the digital-to-analog converter is a switched capacitor digital-to-analog converter.

6. The method of claim 1, wherein the digital-to-analog converter is a switched current source digital-to-analog converter.

7. The method of claim 1, further comprising: generating further feedback pulses between the feedback pulses generated by the digital-to-analog converter by applying a further digital-to-analog converter in the feedback loop.

8. A method of current integration, comprising: transforming an input current into an output integrated voltage using a parallel connection of an operational transconductance amplifier and an integration capacitor, reducing the output integrated voltage by repeatedly discharging the integration capacitor through a feedback loop via a digital-to-analog converter generating feedback pulses, applying an electric power for the operational transconductance amplifier, and elevating the applied electric power only for sampling during a sampling time.

9. A circuit for current integration, comprising: a parallel connection of an integration capacitor, an operational transconductance amplifier and a feedback loop, the operational transconductance amplifier being configured to transform an input current into an output integrated voltage, a digital-to-analog converter in the feedback loop, the digital-to-analog converter being configured to generate feedback pulses triggering discharges of the integration capacitor, a feedback clock period defining time intervals between successive rising edges of the feedback pulses, and a controller configured to provide an extended feedback clock period after a lapse of a plurality of feedback clock periods.

10. The circuit of claim 9, wherein: the controller is configured to perform a range check for the output integrated voltage before sampling, the range check being based on a number of feedback pulses prior to sampling.

11. The circuit of claim 9, wherein the digital-to-analog converter is a switched capacitor digital-to-analog converter.

12. The circuit of claim 9, wherein the digital-to-analog converter is a switched current source digital-to-analog converter.

13. The circuit of claim 9, further comprising: a further digital-to-analog converter in the feedback loop, the controller being configured to enable an alternative operation of the digital-to-analog converter and the further digital-to-analog converter.

14. The method of claim 1, wherein the extended feedback clock period is provided when an input level of the input current is less than half of a signal range of the input current.

15. The circuit of claim 9, wherein the controller configured to provide the extended feedback clock period when an input level of the input current is less than half of a signal range of the input current.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The following is a more detailed description of examples of the method and the circuit in conjunction with the appended figures.

(2) FIG. 1 shows timing diagrams for unmodulated operation, sampling time modulation and power modulation.

(3) FIG. 2 shows timing diagrams for sampling time modulation.

(4) FIG. 3 shows circuit diagrams for GBW reduction of the OTA.

(5) FIG. 4 shows an embodiment of the circuit.

(6) FIG. 5 shows a timing diagram for the embodiment according to FIG. 4.

(7) FIG. 6 shows a circuit diagram for a current integrator with feedback and a corresponding timing diagram.

DETAILED DESCRIPTION

(8) According to one embodiment, doubling the T.sub.clk_DAC takes place during the last cycle, just before sampling, depending on the input current level. As the noise of the OTA is not integrated, only the instantaneous noise during the sampling instant is relevant. The OTA noise power during the rest of the integration time is irrelevant. For input levels below half range of the input current, the frequency of the feedback pulse is smaller than the clock frequency (in the example of FIG. 1b, the frequency of the pulses shown as V.sub.out_fb is half the frequency of the clock signal clk).

(9) When the OTA is allowed to settle longer by increasing the feedback clock period T.sub.clk_DAC, a smaller transconductance g.sub.m is required and therefore less power for the same output noise. However, the feedback clock period T.sub.clk_DAC is tied to the frequency of feedback pulses needed to keep the output integrated voltage V.sub.out_int in the required voltage range.

(10) Hence, the speed of the OTA can be set high during the major integration time but lower for higher noise filtering during the last cycle right before the sampling instant, if the signal range during that cycle is below half range. The last condition is important, because the last DAC clock cycle has to be doubled, thus allowing only one feedback pulse to occur.

(11) As a result, low noise performance is achieved for the lower signal range where high SNR (signal-to-noise ratio) is most important. For the larger input range, the noise of the DAC is dominant, making the higher OTA noise insignificant. Increasing the DAC period for the last cycle by a factor N increases the available time for settling by N, thus resulting in a factor N power saving for the same output noise (assuming the power is proportional to g.sub.m which is the case for OTA input transistors close to weak inversion).

(12) A timing diagram for a conventional operation is depicted in FIG. 1a, which shows the temporal variation of the relevant signals, quantities and parameters on a time line pointing towards the right. The signal indicated as clk is the clock signal providing the clock period T.sub.clk as the minimum time unit employed in the circuit. The signal indicated as sample is high only during the sampling time, which in this example equals the clock period T.sub.clk. The signal indicated as clk.sub.DAC is the clock signal provided for the feedback loop and is the same as the signal clk during conventional operation. Hence in FIG. 1a the feedback clock period T.sub.clk_DAC is the same as the clock period T.sub.clk. V.sub.out_fb is the feedback voltage indicated in FIG. 6a. I.sub.in is the input current, which is assumed to be constant in the example of FIG. 1a. V.sub.out_it is the output integrated voltage, which is indicated in the circuit diagram of FIG. 6a. GBW is the gain-bandwidth product of the OTA, g.sub.m is the transconductance of the OTA and P is the consumed power of the OTA.

(13) A timing diagram for operation by sampling time modulation is depicted in FIG. 1b. Compared with the conventional operation according to FIG. 1a, the feedback clock period T.sub.clk_DAC that corresponds to the sampling time T.sub.sample is increased. In the example shown in FIG. 1b, sampling is performed during an extended feedback clock period T*, which is N times as long (in the example of FIG. 1b especially twice as long) as the regular feedback clock period T.sub.clk_DAC. Moreover, the GBW is reduced during sampling. Thus the sampling time is increased, especially doubled.

(14) In a prescribed time interval, which is highlighted in FIG. 1b, a range check is performed based on the number of feedback pulses immediately prior to sampling. Important for the feasibility is the assumption that the time constant of the input current is significantly below the sampling time. This constraint does not result in loss of signal information, because the total integration time is a multiple of the feedback clock period T.sub.clk_DAC.

(15) In FIG. 2 two different scenarios are exemplified. The worst case scenario in terms of the range of the output integrated voltage V.sub.out_int, which is depicted in FIG. 2a, occurs for half range input when the output integrated voltage V.sub.out_int is just below the reference voltage V.sub.ref (indicated in FIG. 6a) upon entering the sample period, i. e. feedback is not triggered. This results in the maximal possible value of the output integrated voltage V.sub.out_int at the moment when sampling is required, because the next feedback pulse is delayed by two clock periods T.sub.clk. However, as shown in FIG. 2a, by limiting the application of the extended feedback clock period T* to input signals below half range, the risk of exceeding the allowed output range can be obviated.

(16) For signals above half range, T.sub.clk_DAC is kept equal to T.sub.clk to avoid out of range conditions, according to FIG. 2b, corresponding to a conventional operation according to FIG. 1a. As in this regime DAC noise is typically dominant, the power consumption can still be reduced to one half compared to the power consumption for conventional operation.

(17) A timing diagram for an alternative operation by power modulation is depicted in FIG. 1c. In the method according to FIG. 1c, the feedback clock period T.sub.clk_DAC is kept constant, but the supply power P and the transconductance g.sub.m are increased during sampling in combination with a reduction of the GBW of the OTA. In this way the majority of clock cycles can run at reduced power. However, the increase in supply current in the last cycle can result in supply noise, thus deteriorating accuracy. If a large number of parallel integrators with shifted sampling times is integrated on one chip, the supply current pulsing might smooth out on the main supply line.

(18) The GBW of the OTA during sampling can either be reduced by implementing additional load capacitance, which may be achieved with the circuit according to FIG. 3a, or by attenuating the output current of the OTA during sampling, which may be achieved with the circuit according to FIG. 3b. The GBW can also be reduced by lowering the transconductance g.sub.m, but this would not yield any benefit regarding noise.

(19) FIG. 3a is a diagram of a circuit for adding a load capacitor, which can be implemented in the OTA. The inputs and the output of the OTA are indicated by the corresponding voltages V.sub.in.sup., V.sub.in.sup.+ and V.sub.out_OTA. FIG. 3a also shows the connection of the integration capacitor C.sub.int between the negative Input (V.sub.in.sup.) and the output (V.sub.out_OTA) of the OTA.

(20) FIG. 3b is a diagram of a circuit for reducing the output current, which can be implemented in the OTA. The inputs and the output of the OTA are indicated by the corresponding voltages V.sub.in.sup., V.sub.in.sup.+ and V.sub.out_OTA. FIG. 3b also shows the connection of the integration capacitor C.sub.int between the negative Input (V.sub.in.sup.) and the output (V.sub.out_OTA) of the OTA.

(21) FIG. 4 is a circuit diagram for a device wherein the described method can be employed. The device may be a photocurrent readout circuit. The photodiode current is converted to a voltage by a current controlled oscillator. The total number of feedback pulses n.sub.count1+n.sub.count2 during one full integration period T.sub.int provides a coarse analog to digital conversion value, which is combined with a fine conversion result by digitization of the output voltage residue V.sub.residue of the current integrator. DAC feedback is realized by precharged capacitors that are periodically discharged into the virtual ground node. Two equivalent switched capacitor digital-to-analog converters SC DAC1, SC DAC2 are implemented. The first switched capacitor digital-to-analog converter SC DAC1 is always active by default. The second switched capacitor digital-to-analog converter SC DAC2 is activated in case two consecutive DAC pulses are required. In this way, after triggering the first switched capacitor digital-to-analog converter SC DAC1, at least the time interval of one clock period is provided for precharging before the first switched capacitor digital-to-analog converter SC DAC1 is triggered again. According to this concept, the second switched capacitor digital-to-analog converter SC DAC2 is only activated for input currents above half range. Activation of the second switched capacitor digital-to-analog converter SC DAC2 triggers an out_of_range flag that prevents activation of the double sampling time scheme for large input currents.

(22) FIG. 5 is a timing diagram for the operation of a device comprising the circuit according to FIG. 4. T.sub.int is the integration period between two sampling events. V.sub.pulse1 and V.sub.pulse2 are the pulsed voltages provided by the controller as indicated in FIG. 4. An out-of-range condition is present when the signal out_of_range is high. FIG. 5 shows how the second switched capacitor digital-to-analog converter SC DAC2 is used after triggering the first switched capacitor digital-to-analog converter SC DAC1 in out-of-range conditions, when immediately successive feedback pulses are required and there is no time for sufficient recovery of the first switched-capacitor digital-to-analog converter SC DAC1 after triggering. In an out-of-range condition, sampling is only performed for a time interval corresponding to the regular feedback clock period T.sub.clk_OTA (which is indicated at position A in FIG. 5), whereas the sampling time is increased when no such condition is met (which is indicated at position B in FIG. 5).

(23) This invention enables to reduce the power consumed in an integration stage for output residual sampling by a factor N, in particular by a factor of two.