Error amplifier

Abstract

An error amplifier for a pulse width modulation circuit is described. The amplifier includes an operational amplifier configured as an integrator and a feedback loop coupled between a signal output of the operational amplifier and an inverting input of the operational amplifier. The feedback loop comprises a feedback capacitor coupled to the signal output, a feedback resistor coupled to the feedback capacitor, and an integrator resistor coupled to the feedback resistor and the inverting input of the operational amplifier. A junction between the feedback resistor and the integrator resistor is configured to receive an input signal and a junction between the feedback capacitor and the feedback resistor is configured to receive a feedback signal from the pulse width modulation circuit.

Claims

1. An error amplifier for a pulse width modulation circuit, comprising: an operational amplifier configured as an integrator; and a feedback loop coupled between a signal output of the operational amplifier and an inverting input of the operational amplifier, the feedback loop comprising a feedback capacitor coupled to the signal output, a feedback resistor coupled to the feedback capacitor, and an integrator resistor coupled to the feedback resistor and the inverting input of the operational amplifier, wherein a junction between the feedback resistor and the integrator resistor is configured to receive an input signal and a junction between the feedback capacitor and the feedback resistor is configured to receive a feedback signal from the pulse width modulation circuit, wherein the integrator comprises a feedforward capacitor coupled between the signal output and the inverting input of the operational amplifier.

2. The error amplifier of claim 1, wherein the feedback capacitor is arranged to compensate for excess phase shift at the switching frequency.

3. The error amplifier of claim 1, wherein the integrator resistor is arranged to separate an integration function from a feedback summing function of the error amplifier.

4. The error amplifier of claim 1, comprising a first low pass filter coupled to the junction between the feedback capacitor and the feedback resistor, and arranged to receive the feedback signal from the pulse width modulation circuit, wherein the first low pass filter is configured to attenuate a modulation component of the feedback signal.

5. The error amplifier of claim 4, comprising a second low pass filter coupled to the junction between the feedback resistor and the integrator resistor and arranged to receive the input signal, wherein the second low pass filter is configured to attenuate aliasing frequency components from the input signal.

6. The error amplifier of claim 5, comprising a shunt capacitor arranged at a signal input of the error amplifier thereby forming a pi input filter with the second low pass filter, wherein the pi input filter is configured to prevent switching energy from the feedback signal being conducted to a signal driving component.

7. A pulse width modulation circuit, comprising: a driver circuit configured to output a modulated signal; a switching device arranged to receive the modulated signal from the driver circuit; and an error amplifier according to claim 1, wherein an output signal of the switching device is the feedback signal and wherein the signal output of the operational amplifier is coupled to the driver circuit.

8. The pulse width modulation circuit of claim 7, comprising two switching devices configured in a push pull arrangement.

9. The error amplifier of claim 2, wherein the integrator resistor is arranged to separate an integration function from a feedback summing function of the error amplifier.

10. The error amplifier of claim 2, comprising a first low pass filter coupled to the junction between the feedback capacitor and the feedback resistor, and arranged to receive the feedback signal from the pulse width modulation circuit, wherein the first low pass filter is configured to attenuate a modulation component of the feedback signal.

11. The error amplifier of claim 3, comprising a first low pass filter coupled to the junction between the feedback capacitor and the feedback resistor, and arranged to receive the feedback signal from the pulse width modulation circuit, wherein the first low pass filter is configured to attenuate a modulation component of the feedback signal.

12. The error amplifier of claim 1, comprising a low pass filter coupled to the junction between the feedback resistor and the integrator resistor and arranged to receive the input signal, wherein the low pass filter is configured to attenuate aliasing frequency components from the input signal.

13. The error amplifier of claim 2, comprising a low pass filter coupled to the junction between the feedback resistor and the integrator resistor and arranged to receive the input signal, wherein the low pass filter is configured to attenuate aliasing frequency components from the input signal.

14. The error amplifier of claim 3, comprising a low pass filter coupled to the junction between the feedback resistor and the integrator resistor and arranged to receive the input signal, wherein the low pass filter is configured to attenuate aliasing frequency components from the input signal.

15. An error amplifier for a pulse width modulation circuit, comprising: an operational amplifier configured as an integrator; a feedback loop coupled between a signal output of the operational amplifier and an inverting input of the operational amplifier, the feedback loop comprising a feedback capacitor coupled to the signal output, a feedback resistor coupled to the feedback capacitor, and an integrator resistor coupled to the feedback resistor and the inverting input of the operational amplifier, wherein a junction between the feedback resistor and the integrator resistor is configured to receive an input signal, and wherein a junction between the feedback capacitor and the feedback resistor is configured to receive a feedback signal from the pulse width modulation circuit; a first low pass filter coupled to the junction between the feedback capacitor and the feedback resistor, and arranged to receive the feedback signal from the pulse width modulation circuit, wherein the first low pass filter is configured to attenuate a modulation component of the feedback signal; a second low pass filter coupled to the junction between the feedback resistor and the integrator resistor, and arranged to receive the input signal, wherein the second low pass filter is configured to attenuate aliasing frequency components from the input signal; and a shunt capacitor arranged at a signal input of the error amplifier thereby forming a pi input filter with the second low pass filter, wherein the pi input filter is configured to prevent switching energy from the feedback signal being conducted to a signal driving component.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present disclosure can be understood with reference to the description of the embodiments set out below, in conjunction with the appended drawings in which:

(2) FIG. 1, described above, illustrates an example of an audio pulse width modulation (PWM) amplifier;

(3) FIG. 2 illustrates an error amplifier according to a first aspect of the invention;

(4) FIG. 3 illustrates an error amplifier according to a second aspect of the invention;

(5) FIG. 4 illustrates an audio pulse width modulation (PWM) amplifier according to a third aspect of the invention;

(6) FIG. 5 illustrates a DC or AC motor control circuit according to a fourth aspect of the invention; and

(7) FIG. 6 illustrates a DC or AC motor control circuit according to a fifth aspect of the invention.

DESCRIPTION

(8) According to a first embodiment of the invention there is provided an error amplifier for a pulse width modulation circuit, comprising an operational amplifier configured as an integrator, and a feedback loop coupled between a signal output of the operational amplifier and an inverting input of the operational amplifier, the feedback loop comprising a feedback capacitor coupled to the signal output, a feedback resistor coupled to the feedback capacitor, and an integrator resistor coupled to the feedback resistor and the inverting input of the operational amplifier, wherein a junction between the feedback resistor and the integrator resistor is configured to receive an input signal and a junction between the feedback capacitor and the feedback resistor is configured to receive a feedback signal from the pulse width modulation circuit. Thus, an error amplifier is provided with a single stage of circuitry which takes account of the design requirements discussed above without the use of multi circuit blocks.

(9) The feedback capacitor may be arranged to compensate for excess phase shift at the switching frequency.

(10) The integrator resistor may be arranged to separate an integration function from a feedback summing function of the error amplifier.

(11) The error amplifier may comprise a first low pass filter coupled to the junction between the feedback capacitor and the feedback resistor, and arranged to receive the feedback signal from the pulse width modulation circuit, wherein the first low pass filter is configured to attenuate a modulation component of the feedback signal.

(12) The error amplifier may comprise a second low pass filter coupled to the junction between the feedback resistor and the integrator resistor and arranged to receive the input signal, wherein the second low pass filter is configured to attenuate aliasing frequency components from the input signal.

(13) The error amplifier may comprise a shunt capacitor arranged at a signal input of the error amplifier thereby forming a pi input filter with the second low pass filter, wherein the pi input filter is configured to prevent switching energy from the feedback signal being conducted to a signal driving component. The integrator may comprise a feedforward capacitor coupled between the signal output and the inverting input of the operational amplifier.

(14) According to a second embodiment of the invention there is provided a pulse width modulation circuit, comprising a driver circuit configured to output a modulated signal, a switching device arranged to receive the modulated signal from the driver circuit, and an error amplifier according to the first embodiment with one or more of the optional features mentioned above. An output signal of the switching device is the feedback signal and wherein the signal output of the operational amplifier is coupled to the driver circuit.

(15) The pulse width modulation circuit may comprise two switching devices configured in a push pull arrangement.

(16) The pulse width modulation circuit may be coupled to a loudspeaker or a motor.

(17) An error amplifier designed to be used for PWM amplifiers typically include summation, and an integrator or a feed forward path filter, and may optionally include a feedback path filter. There are several requirements that should be considered when designing an error amplifier circuit stage, which are discussed below.

(18) An error amplifier for use with a PWM amplifier is typically based on an operational amplifier, integrated or discrete, circuit which should include a suitably high GainBandwidth product to operate linearly up to the maximum frequencies of interest (e.g. 400 kHz or 20 to 40 times higher than the highest audio frequency of the audio signal, switching frequency and its harmonics). The error amplifier should have a high performance within the audio signal frequency range, since the error amplifier will define the limits of signal performance of the PWM circuit. Furthermore, the power supply rails of the error amplifier should match the PWM circuit voltage switching levels or include signal conditioning to ensure a low voltage rail operational amplifier does not see voltages on its inputs which exceed its power supply rails, as this will lead to destruction of the operational amplifier and reduce reliability of circuit.

(19) A pre-conditioning circuit block configured to filter out, or attenuate the bus voltage level PWM circuit sampling frequency from the fed-back scaled version of the modulated signal. The output voltage rail to rail switching levels are likely to exceed the power supply of the signal level voltages and power supplies of the error amplifier stage. A pre-filtering circuit block for the input audio signal to ensure the input audio signal which is fed to the PWM circuit does not contain aliasing frequency components which exceed half the sampling (i.e. switching) frequency of the PWM circuit, for example. This is because frequencies that exceed half the sampling (i.e. switching) frequency of the PWM circuit will be effectively introduced back into the input signal, causing signal distortion, and due to in-band foldback are not possible to remove.

(20) The PWM high-voltage switching gate driver 18 and output power switching devices 20, 22 of the circuit are inserted between the output of the error amplifier and the feedback to allow high powers to be delivered to the output load (e.g. loud speaker 30).

(21) A summing operation is required within the error amplifier to enable negative feedback to be used, since negative feedback reduces non-linearity and also reduces output impedance, as in the case with a typical feedback control circuit. For low PWM amplifier output distortion, global negative feedback can be applied to allow the error amplifier to correct for any non-linearity in the output from the PWM power output stage.

(22) The error amplifiers presented below are configured to take account all of the requirements mentioned above. The error amplifier circuits described below have been devised as a new specialist class of filter suitable for PWM switching amplifiers, which combine the design considerations discussed above into a single stage of circuitry. This configuration offers improved circuit performance using a single operational amplifier stage. Furthermore, when the resistance values are optimised the configuration provides an inherent reliability against overvoltage conditions applied to the error amplifier terminals.

(23) FIG. 2 illustrates an error amplifier 40 according to a first aspect of the invention. The amplifier 40 is fed an input audio signal at terminal or junction 42, and generates an output audio signal at terminal or junction 48. Terminal or junction 44 is connected to ground. Terminal or junction 46 is coupled to an output of a power stage of a PWM amplifier.

(24) The error amplifier 40 includes an operational amplifier 50 selected for desired bandwidth and signal distortion characteristics, for example a AD8651, which is coupled to the same bus voltage supplies lines (i.e. +Vcc and Vcc) as the switching stage of a PWM amplifier (not shown). The op-amp 50 is configured as an integrator with a feed-forward capacitor 52 coupled between a signal output of the op-amp 50 and an inverting input of the op-amp 50, and an integrator resistor 58. The amplifier also includes a feedback loop coupled between the signal output of the operational amplifier 50 and the inverting input of the operational amplifier 50. The feedback loop includes a feedback capacitor 54 coupled to the signal output of the op-amp 50, a first feedback resistor 56 coupled to the feedback capacitor 54 and the integrator resistor 58. The integrator resistor 58 is typically greater than or equal to 100 ohms and separates the integration function of the op-amp arrangement from the feedback summing function of the op-amp arrangement, and provides a pole multiplication of the integrator frequency.

(25) The audio signal is fed to the error amplifier 40 via input resistor 60. The input resister 60 is coupled to the integrator resistor 58 and the first feedback resistor 56. That is to say that the input resistor 60 is coupled to a junction or terminal of/between the integrator resistor 58 and the first feedback resistor 56. A signal is fed back from the switching stage of the PMW amplifier via a second feedback resistor 66.

(26) A low pass filter is arranged at the feedback input 46 of the error amplifier. The low pass filter includes a third feedback resistor 62 and a low-pass capacitor 64 shunted to ground. The low-pass capacitor 64 is tuned to the 3 dB frequency of the circuit, typically in the region of F.sub.switching/10 allowing for loop reduction to minimise aliasing.

(27) The low-pass capacitor 64 can be selected according the following expression:
C.sub.Low-pass capacitor 64=1/(2*R.sub.Third feedback resistor 62*F)
where F is the 3 dB frequency of the circuit.

(28) The low-pass capacitor 64 has a dual function, additionally to providing loop gain reduction this capacitor also provides an open-loop zero allowing phase shift correction of the switching signal output by the PWM power, output stage of the amplifier. A design assessment should be made to prioritise function between low-pass capacitor 64 acting as a switching frequency filter giving 20 dB of rejection pre-conditioning the switching frequency present in the feedback signal and a phase correction contribution to the feedback signal presented to the error amplifier input terminal.

(29) Increasing the value of capacitor 64 from the value calculated for 3 dB frequency=fs/10, increases the phase advance of the fed-back signal.

(30) The gain of the error amplifier 40 is determined using the following expression:
AV=((R.sub.First feedback resistor 56+R.sub.Second feedback resistor 66+R.sub.Third feedback resistor 62)/R.sub.Input resister 60).

(31) The feed forward or integrator capacitor 52 is selected according to the following expression:
C.sub.Feed forward capacitor 52=1/(((AV*R.sub.Integrator resistor 58)+R.sub.First feedback resistor 56+R.sub.Second feedback resistor 66+R.sub.Third feedback resistor 62)*2*F.sub.Integrator)
where F.sub.Integrator=F.sub.switching/a.sub.x. For an audio application having a maximum frequency of 20 kHz and switching frequency (F.sub.switching) of 400 kHz, a.sub.x=3 provides an optimal filter shape and roll off.

(32) The feedback capacitor 54 is added to provide a local compensation for any excess phase shift at the switching frequency and multiples thereof. This may improve the stability and reduce the effect of phase shift which may result from the PWM power, output stage of the amplifier. The feedback capacitor 54 effectively adds a pole and a zero in the closed loop frequency response of the error amplifier.

(33) The following expression can be used to determine the capacitance value of the feedback capacitor 54 according the frequency of a desired pole position:
C.sub.Feedback capacitor 54=1/(2*(R.sub.Second feedback resistor 66+R.sub.Third feedback resistor 62)*F.sub.Pole)
where F.sub.Pole=F.sub.Switching/b.sub.x.

(34) The following expression can be used to determine the zero frequency provided by the capacitance value of the feedback capacitor 54:
F.sub.Zero=1/(2*R.sub.First feedback resistor 56*C.sub.Feedback capacitor 54)

(35) The gain of the error amplifier at the switching frequency should be preferably limited to approximately 6 dB. For an audio application having a maximum frequency of 20 kHz and switching frequency (F.sub.switching) of 400 kHz, b.sub.x=2 provides an optimal filter shape and roll off. The feedback capacitor 54 reduces the requirement of the GainBandwidth product of the error amplifier circuitry at the switching frequency without affecting linearity in the range of signal frequencies.

(36) The expressions discussed above provide i) a greater than 20 dB gain reduction at the switching frequency, and ii) flat passband response up to 20 kHz with minimal phase shift at 20 kHz (i.e. audio the upper limit of the signal frequency range). Optimisation of the component values of the error amplifier can provide a desired error amplifier gain and phase characteristics depending on the application.

(37) In an example, a gain (AV) of 10.4 was selected and the following component values were selected:
R.sub.Input resister 60=1,000R;
R.sub.Integrator resistor 58=100R;
R.sub.First feedback resistor 56=1,000R;
R.sub.Second feedback resistor 66=4,700R;
R.sub.Third feedback resistor 62=4,700R;
F.sub.Switching=400,000 Hz:

(38) Based on the expressions provided above, and an integrator frequency of 42,441 Hz (i.e. F.sub.Integrator=400,000/3) the following capacitor values can be determined:
C.sub.Low-pass capacitor 64=1/(2/4,700R*400,000 Hz)=847 pF
C.sub.Feed forward capacitor 52=1/(((10.4*100R)+1,000R+4,700R+4,700R)*2*42,441 Hz)=327 pF
C.sub.Feedback capacitor 54=1/((4,700R+4,700R)*400,000 Hz)=266 pF

(39) It will be appreciated that capacitors close to the theoretical values will be used.

(40) FIG. 3 illustrates an error amplifier 70 according to a second aspect of the invention. The components and features described in association with FIG. 2 are labelled using the same reference numerals in FIG. 3. The error amplifier 70 illustrated in FIG. 3 includes a input filter at its input. In the figure the input filter is fed by the audio input signal at terminal 42 and is coupled to the input resistor 60. The input filter includes a first shunt capacitor 72 and a second shunt capacitor 74 which are separated by a second, series resistor 76. The addition of the input filter may protect the PWM amplifier from aliasing frequency components presented to the input of the error amplifier. It is noted that the combination of the second, series resistor 76 and the input resistor 60 in FIG. 3 is equivalent to the single input resistor 60 in FIG. 2. An inductor may also be included in series with terminal 42 or in series with series resistor 76 to improve rejection. Furthermore, the first shunt capacitor 72 is optionally included, such that a low pass filter would be formed in its absence.

(41) FIG. 4 illustrates an audio pulse width modulation (PWM) amplifier 80 according to a third aspect of the invention. The amplifier 80 includes an error amplifier 82 which may be either the error amplifier 40 described in association with FIG. 2 or the error amplifier 70 described in association with FIG. 3. The other numbered components of FIG. 4 are the same as the like numbered features illustrated in FIG. 1. In the amplifier 80, an input audio signal is received at terminal or junction 42, and terminal or junction 48 is coupled to the gate driver 18 via the comparator 12. The output of the switches 20, 22 is coupled to terminal or junction 46 of the error amplifier 82.

(42) FIG. 5 illustrates a DC or AC motor control circuit 100 according to a fourth aspect of the invention. The circuit 100 includes an error amplifier 102 which may be of the form of the error amplifier 40 described in association with FIG. 2 or the error amplifier 70 described in association with FIG. 3. Each of error amplifier 40 and error amplifier 70 have been described in association with an audio amplifier, but the form of these amplifiers can be used as part of a DC or AC motor control circuit and it would be apparent to the skilled person how to select the appropriate component values based on the general description of those error amplifiers. The output of the error amplifier 102 is fed via the comparator 12 to a power stage 104, which includes a gate driver or switching controller 106 which outputs a signal comprising square pulses of fixed amplitude with a varying width and separation. It will be appreciated that the gate driver 106 generates a signal and a level shifted and inverted version of the same separated by a protective delay or dead time. The power stage 104 includes two switching devices 108, 110 (e.g. field effect transistors (FET)). The two switches 108, 110 are arranged so as to be either fully on or fully off such that the output of the switching devices is at either +Vcc or Vcc (i.e. the bus voltages). This type of arrangement utilises the property that if the push-pull output devices are either fully on or fully off they dissipate their minimum power leading to high amplifier efficiency. The output of the power stage 104 is fed back to the error amplifier 102, as is described above in respect of the audio amplifier.

(43) The output of the power stage 104 is low pass filtered using a passive filter 112 to filter out the switching frequency and is then fed to a motor 118. The passive filter 112 is a two-pole inductor-capacitor (LC) filter including a series inductor 114 and a capacitor 116 shunted to ground. The component values for the series inductor 114 and the shunt capacitor 116 can be determined using the expression F.sub.3 dB=1/2*(L.sub.Series*C.sub.Shunt), where L Series is the inductance of series inductor 114 and C shunt is the capacitance of shunt capacitor 116, and F.sub.3 dB is typically a division of between 2 and 10 of the switching frequency.

(44) FIG. 6 illustrates an alternative DC or AC motor control circuit 120 according to a fifth aspect of the invention. The circuit 120 includes an error amplifier 122 which is of the form of error amplifier 102 described in association with FIG. 5. The output of the error amplifier 122 is fed to a gate driver or switching controller 124 which outputs a signal comprising square pulses of fixed amplitude with a varying width and separation. In this example, a single switch 126 (e.g. field effect transistors (FET)) is used in series with a motor 128, which are arranged between voltage supplies (i.e. +Vcc or Vcc), and the output signal of the controller 124 is fed to the control input (i.e. gate) of the switch 126.

(45) It will be appreciated that the foregoing discussion relates to particular embodiments. However, in other embodiments, various aspects and examples may be combined.