Circuits, devices and methods related to amplification with active gain bypass

Abstract

Circuits, devices and methods related to amplification with active gain bypass. In some embodiments, an amplifier can include a first amplification path implemented to amplify a signal, and having a cascode arrangement of a first input transistor and a cascode transistor to provide a first gain for the signal when in a first mode. The amplifier can further include a second amplification path implemented to provide a second gain for the signal while bypassing at least a portion of the first amplification path when in a second mode. The second amplification path can include a cascode arrangement of a second input transistor and the cascode transistor shared with the first amplification path. The amplifier can further include a switch configured to allow routing of the signal through the first amplification path in the first mode or the second amplification path in the second mode.

Claims

1. A radio-frequency amplifier comprising: a first amplification path implemented to receive and amplify a signal with a first gain, and including a cascode arrangement of a first input transistor and a cascode transistor; a second amplification path implemented to receive and amplify a signal with a second gain, and including a cascode arrangement of a second input transistor and the cascode transistor shared with the first amplification path, the first and second amplification paths having separate input nodes, the signal received by the first amplification path through the respective input node substantially the same as the signal received by the second amplification path through the respective input node; and a control circuit configured to allow operation of the first amplification path when in a first mode and to allow operation of the second amplification path when in a second mode.

2. The radio-frequency amplifier of claim 1 further comprising one or more switches implemented for either or both of the first and second amplification paths, the one or more switches configured to support the operation of the first amplification path when in the first mode and to support the operation of the second amplification path when in the second mode.

3. The radio-frequency amplifier of claim 2 wherein the control circuit is configured to control the one or more switches.

4. The radio-frequency amplifier of claim 3 wherein the control circuit is further configured to control operation of the some or all of the first input transistor, the second input transistor and the cascode transistor.

5. The radio-frequency amplifier of claim 4 wherein the control circuit is configured to disable the second input transistor when in the first mode, and to disable the first input transistor when in the second mode.

6. The radio-frequency amplifier of claim 3 wherein the one or more switches includes a switch implemented along an input path to the second input transistor.

7. The radio-frequency amplifier of claim 6 wherein the switch along the input path to the second input transistor is configured to be open when in the first mode, and to be closed when in the second mode.

8. The radio-frequency amplifier of claim 6 wherein the one or more switches further includes a switch implemented between the first input transistor and the cascode transistor, and a switch implemented between the second input transistor and the cascode transistor.

9. The radio-frequency amplifier of claim 8 wherein the switch between the first input transistor and the cascode transistor is configured to be closed when in the first mode, and to be open when in the second mode, and the switch between the second input transistor and the cascode transistor is configured to be open when in the first mode, and to be closed when in the second mode.

10. The radio-frequency amplifier of claim 6 wherein the second amplification path further includes an attenuator implemented along the input path to the second input transistor.

11. The radio-frequency amplifier of claim 6 wherein the second amplification path further includes a matching network implemented along the input path to the second input transistor.

12. A radio-frequency module comprising: a packaging substrate configured to receive a plurality of components; and an amplifier implemented on the packaging substrate, the amplifier including a first amplification path implemented to receive and amplify a signal with a first gain, and including a cascode arrangement of a first input transistor and a cascode transistor, the amplifier further including a second amplification path implemented to receive and amplify a signal with a second gain, and including a cascode arrangement of a second input transistor and the cascode transistor shared with the first amplification path, the first and second amplification paths having separate input nodes, the signal received by the first amplification path through the respective input node substantially the same as the signal received by the second amplification path through the respective input node, the amplifier further including a control circuit configured to allow operation of the first amplification path when in a first mode and to allow operation of the second amplification path when in a second mode.

13. The radio-frequency module of claim 12 wherein the amplifier is implemented on a semiconductor die that is mounted on the packaging substrate.

14. A wireless device comprising: an antenna; an amplifier in communication with the antenna and including a first amplification path implemented to receive and amplify a signal with a first gain, and including a cascode arrangement of a first input transistor and a cascode transistor, the amplifier further including a second amplification path implemented to receive and amplify a signal with a second gain, and including a cascode arrangement of a second input transistor and the cascode transistor shared with the first amplification path, the first and second amplification paths having separate input nodes, the signal received by the first amplification path through the respective input node substantially the same as the signal received by the second amplification path through the respective input node, the amplifier further including a control circuit configured to allow operation of the first amplification path when in a first mode and to allow operation of the second amplification path when in a second mode; and a transceiver configured to process an amplified signal generated by the amplifier.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 depicts a radio-frequency amplifier having a plurality of amplifying transistors and an active gain bypass circuit.

(2) FIG. 2 shows an example of a low-noise amplifier (LNA) implemented in a cascode configuration.

(3) FIG. 3 shows that in some embodiments, an LNA can include a second amplification path configured to selectively divert a signal away from a primary input transistor of a cascode arrangement.

(4) FIG. 4A shows the LNA of FIG. 3 being operated in a first gain mode (G.sub.0 mode) to provide a high gain.

(5) FIG. 4B shows the LNA of FIG. 3 being operated in a second gain mode (G.sub.2 mode) to provide a low gain.

(6) FIG. 5 shows that in some embodiments, a first input transistor and a second input transistor of an LNA do not necessarily need to share a common input.

(7) FIG. 6A shows the LNA of FIG. 5 being operated in a first gain mode (G.sub.0 mode) to provide a high gain.

(8) FIG. 6B shows the LNA of FIG. 5 being operated in a second gain mode (G.sub.2 mode) to provide a low gain.

(9) FIG. 7 shows that in some embodiments, an LNA having one or more features as described herein can include a switch between an input transistor and a cascode transistor for each of the first and second amplification paths.

(10) FIG. 8A shows the LNA of FIG. 7 being operated in a first gain mode (G.sub.0 mode) to provide a high gain.

(11) FIG. 8B shows the LNA of FIG. 7 being operated in a second gain mode (G.sub.2 mode) to provide a low gain.

(12) FIG. 9 shows an example LNA in which each of first and second input transistors has its own degeneration inductance to ground.

(13) FIG. 10 shows that in some embodiments, an LNA having one or more features as described herein can be controlled by a controller.

(14) FIG. 11 shows that in some embodiments, some or all of an LNA having one or more features as described herein can be implemented on a semiconductor die.

(15) FIG. 12 shows an example where some or all of an LNA having one or more features as described herein can be implemented on a packaged module.

(16) FIG. 13 shows another example where some or all of an LNA having one or more features as described herein can be implemented on a packaged module.

(17) FIG. 14 shows that in some embodiments, the packaged module of FIG. 12 or 13 can be a diversity receiver module.

(18) FIG. 15 depicts an example wireless device having one or more advantageous features described herein.

DETAILED DESCRIPTION OF SOME EMBODIMENTS

(19) The headings provided herein, if any, are for convenience only and do not necessarily affect the scope or meaning of the claimed invention.

(20) In many wireless applications, receivers typically require large dynamic ranges, and such a requirement can be achieved through multiple gain states with varying levels of gain, noise figure, and linearity. For example, a smaller signal may require a gain state with a higher gain, a lower noise figure, and a reasonable but not extremely high linearity performance. A higher signal level may require a lower gain, a significantly relaxed noise figure, and a high linearity to amplify the signal with good fidelity. These gain states may also have some requirement to maintain a similar phase shift as changes are made from one gain state to another.

(21) It is noted that in wireless designs, a high gain state with a low noise figure typically cannot tolerate insertion loss placed in series with a low-noise amplifier (LNA). It is also noted that a low gain state with a relaxed noise figure typically requires a series switch and potentially an attenuator to achieve high linearity levels. It is further noted that an LNA can be entirely bypassed; however, phase shift can be difficult to maintain as one switches from an active gain mode to a full passive bypass mode.

(22) Described herein are architectures, circuits, devices and methods related to, among others, a radio-frequency (RF) amplifier having an active gain bypass circuit. FIG. 1 depicts an RF amplifier 100 having a plurality of amplifying transistors 102 and an active gain bypass circuit 104. Such an RF amplifier can receive an input RF signal (RF_in) and amplify such a signal to generate an output RF signal (RF_out). For the purpose of description, various examples related to such an RF amplifier are described in the context of a low-noise amplifier (LNA). However, it will be understood that one or more features of the present disclosure can also be implemented for other types of RF amplifiers, including power amplifiers (PAs).

(23) FIG. 2 shows an example of an LNA 10 implemented in a cascode configuration. Such an LNA can include first and second transistors (collectively indicated as 12) implemented in a cascode configuration. For example, the first transistor M.sub.1 can be configured to operate as a common source device (also referred to as an RF stage), and the second transistor M.sub.CAS can be configured to operate as a common gate device (also referred to as a cascode stage). More particularly, an input RF signal (RF_in) is shown to be provided to a gate of the first transistor M.sub.1 through an input inductance L.sub.IN, and the amplified signal is shown to be output through its drain. The source of the first transistor M.sub.1 is shown to be coupled to ground, typically through an inductance indicated as Ls. The amplified signal from the drain of the first transistor M.sub.1 is shown to be provided to a source of the second transistor M.sub.CAS for further amplification, and such further amplified signal is shown to be output through the drain of the second transistor M.sub.CAS. The gate of the second transistor M.sub.CAS can be provided with an appropriate gate voltage V.sub.G for operation. In the example of FIG. 2, the LNA 10 is shown to be provided with a supply voltage V.sub.DD at the drain of M.sub.CAS through an inductance L.sub.D. In the example of FIG. 2, the amplified signal from the LNA 10 can be provided to an output node (RF_out) through an output matching network N.sub.L (14).

(24) In some embodiments, an LNA can include a second amplification path configured to selectively divert a signal away from a primary input transistor (e.g., the first transistor M.sub.1 in FIG. 2) of a cascode arrangement. FIG. 3 shows an example of such a second amplification path depicted as 104. As described herein, such a second amplification path can be configured to function as an active gain bypass circuit 104 of FIG. 1. In the example of FIG. 3, the cascode arrangement of M.sub.1 and M.sub.CAS can be similar to the example of FIG. 2.

(25) FIG. 3 shows that in some embodiments, the second amplification path (also referred to herein as active gain bypass circuit) 104 can include a low parasitic shunt switch S.sub.2 that can be engaged to divert a signal from an input node 110 of M.sub.1. The second amplification path 104 can include an attenuator 114 (e.g., a tunable attenuator) in series with the switch S.sub.2, with the series combination of S.sub.2 and the attenuator 114 being between the input node 110 of M.sub.1 and a gate of a second input transistor M.sub.2.

(26) In the example of FIG. 3, the source of the second input transistor M.sub.2 is shown to be coupled to ground through an inductance indicated as Ls. In some embodiments, the source of the first input transistor M.sub.1 and the source of the second input transistor M.sub.2 can share the inductance Ls as a common degeneration inductance. For example, a common node 122 is shown to be coupled to the source of the first input transistor M.sub.1 and the source of the second input transistor M.sub.2, and such a common node is shown to be coupled to ground through the inductance Ls.

(27) In the example of FIG. 3, the amplified signal from the drain of the second input transistor M.sub.2 is shown to be provided to a source of the cascode transistor M.sub.CAS for further amplification, and such further amplified signal is shown to be output through the drain of the cascode transistor M.sub.CAS. In some embodiments, a common node 116 can be coupled to the drain of the first input transistor M.sub.1 and the drain of the second input transistor M.sub.2, and such a common node can be coupled to the source of the cascode transistor M.sub.CAS.

(28) In some embodiments, the second amplification path 104 can further include a capacitance C.sub.2 and a matching network N.sub.2 (112) in series with the switch S.sub.2. For example, the capacitance C.sub.2 and the matching network N.sub.2 can be implemented in series between the switch S.sub.2 and the attenuator 114. In some embodiments, the matching network N.sub.2 can be configured to provide matching of an input impedance approximately the same as the input impedance for a first-gain operation involving the first amplification path involving the cascode arrangement of M.sub.1 and M.sub.CAS. The matching network N.sub.2 can also be configured to provide a phase shift that is approximately the same as the phase shift associated with the first amplification path.

(29) In some embodiments, the switch S.sub.2 can be configured to provide a low parasitic effect (e.g., low parasitic capacitance). Thus, when S.sub.2 is OFF during operation of the first amplification path (through M.sub.1), S.sub.2 provides a minimal or reduced parasitic impact to such a first amplification path. Accordingly, when the LNA 100 is in the first gain mode (G.sub.0 mode), an optimum or desired combination of gain and noise figure (NF) can be achieved. It is noted that in the first amplification path involving the cascode arrangement of M.sub.1 and M.sub.CAS, the foregoing G.sub.0 mode can be achieved by an absence of losses associated with a series switch (such as S.sub.2 in the second amplification path 104) and a series attenuator (such as the attenuator 114 in the second amplification path 104). In such a configuration, linearity may not be ideal; however, an optimum or desired combination of gain and noise figure can be achieved.

(30) In some embodiments, the foregoing first gain mode (G.sub.0 mode) can be a high gain mode; and such a gain mode can be utilized, for example, when the received signal is relatively weak. As described herein, the second amplification path 104 can be configured (e.g., with a low parasitic switch S.sub.2) so as to allow the first amplification path to achieve such a high gain for the weak signal.

(31) In some embodiments, the LNA 100 of FIG. 3 can be configured to operate in a second gain mode (G.sub.2 mode) through the second amplification path 104. Such a mode can be utilized, for example, when the received signal is relatively strong. As shown in the example of FIG. 3, the adjustable attenuator 114 in the second amplification path 104 can be implemented in front of the second input transistor M.sub.2 to facilitate a lower gain for the relatively strong signal. Accordingly, a desirable very high linearity performance can be achieved. Noise figure may be relatively high in such a configuration; but such a high noise figure can be acceptable for the strong signal and the low gain mode.

(32) FIG. 3 shows that in some embodiments, the first input transistor M.sub.1 and the second input transistor M.sub.2 can share a common degeneration inductance Ls. Such sharing of the common degeneration inductance can be appropriate, for example, when the two input transistors (M.sub.1 and M.sub.2) are similar or substantially the same. As described herein, in some embodiments, each of the first input transistor M.sub.1 and the second input transistor M.sub.2 can have its own degeneration inductance.

(33) FIG. 4A shows the LNA 100 of FIG. 3 being operated in the first gain mode (G.sub.0 mode) to provide a high gain. FIG. 4B shows the LNA 100 of FIG. 3 being operated in the second gain mode (G.sub.2 mode) to provide a low gain.

(34) Such gain modes can be achieved by operating the first input transistor M.sub.1, the second input transistor M.sub.2, and the switch S.sub.2 as listed in Table 1.

(35) TABLE-US-00001 TABLE 1 Gain mode Gain achieved M1 state M2 state S2 state G0 High ON OFF OFF G2 Low OFF ON ON

(36) In FIG. 4A, the first gain mode (G.sub.0 mode) is shown to result in a signal being routed and amplified as indicated by a path 130. In FIG. 4B, the second gain mode (G.sub.2 mode) is shown to result in a signal being routed and amplified as indicated by a path 132.

(37) In the example of FIG. 3, the first input transistor M.sub.1 and the second input transistor M.sub.2 are shown to share a common input node 110. In some embodiments, such an input node can be implemented as, or be electrically connected to, a single input pad on a die (e.g., a silicon-on-insulator (SOI) die) on which the LNA 100 is implemented.

(38) FIG. 5 shows that in some embodiments, the first input transistor M.sub.1 and the second input transistor M.sub.2 do not necessarily need to share a common input pad. For example, a signal to be processed by the LNA 100 of FIG. 5 may be routed appropriately before reaching the LNA. Thus, a first input node (In.sub.1) can be provided to receive a signal to be processed by the first amplification path involving the first input transistor M.sub.1. Similarly, a second input node (In.sub.2) can be provided to receive a signal to be processed by the second amplification path involving the second input transistor M.sub.2. In the example of FIG. 5, the first and second amplification paths are generally the same as those of the example of FIG. 3.

(39) In the example of FIG. 5, the LNA 100 is depicted as including a node 110 after the input inductance L.sub.IN, and a node 140 before the switch S.sub.2. Assuming that such an LNA is implemented on a die such as an SOI die, the die may or may not include the input inductance L.sub.IN. Assuming that the input inductance L.sub.IN is external to the LNA die, the nodes 110 and 140 associated with the first and second amplification paths can be implemented as or be electrically connected to two separate input pads on the die.

(40) FIG. 6A shows the LNA 100 of FIG. 5 being operated in the first gain mode (G.sub.0 mode) to provide a high gain. FIG. 6B shows the LNA 100 of FIG. 5 being operated in the second gain mode (G.sub.2 mode) to provide a low gain. Such gain modes can be achieved by operating the first input transistor M.sub.1, the second input transistor M.sub.2, and the switch S.sub.2 as listed in Table 1.

(41) In FIG. 6A, the first gain mode (G.sub.0 mode) is shown to result in a signal being routed and amplified as indicated by a path 150. In FIG. 6B, the second gain mode (G.sub.2 mode) is shown to result in a signal being routed and amplified as indicated by a path 152.

(42) FIG. 7 shows that in some embodiments, an LNA 100 having one or more features as described herein can include a switch between the input transistor (M.sub.1 or M.sub.2) and the cascode transistor (M.sub.CAS) for each of the first and second amplification paths. Other than such switches, the example LNA 100 of FIG. 7 can be similar to the example of FIG. 3.

(43) In the example of FIG. 7, a switch 160 is shown to be implemented between the first input transistor M.sub.1 and the cascode transistor M.sub.CAS. Similarly, a switch 162 is shown to be implemented between the second input transistor M.sub.2 and the cascode transistor M.sub.CAS. In some embodiments, each of such switches 160, 162 can be implemented when some levels of isolation and/or return loss are desired.

(44) FIG. 8A shows the LNA 100 of FIG. 7 being operated in the first gain mode (G.sub.0 mode) to provide a high gain. FIG. 8B shows the LNA 100 of FIG. 7 being operated in the second gain mode (G.sub.2 mode) to provide a low gain. Such gain modes can be achieved by operating the first input transistor M.sub.1, the second input transistor M.sub.2, the switch S.sub.2, and the switches 160, 162 as listed in Table 2.

(45) TABLE-US-00002 TABLE 2 Gain Gain Switch Switch mode achieved M1 state M2 state S2 state 160 state 162 state G0 High ON OFF OFF ON OFF G2 Low OFF ON ON OFF ON

(46) In FIG. 8A, the first gain mode (G.sub.0 mode) is shown to result in a signal being routed and amplified as indicated by a path 170. In FIG. 8B, the second gain mode (G.sub.2 mode) is shown to result in a signal being routed and amplified as indicated by a path 172.

(47) As described in reference to FIGS. 3 and 5, the first and second input transistors (M.sub.1 and M.sub.2) may or may not share a common degeneration inductance to ground. FIG. 9 shows an example LNA 100 in which each of the first and second input transistors (M.sub.1 and M.sub.2) has its own degeneration inductance coupling to ground. For example, the first input transistor M.sub.1 is shown to have its source coupled to ground through a first degeneration inductance L.sub.S1. Similarly, the second input transistor M.sub.2 is shown to have its source coupled to ground through a second degeneration inductance L.sub.S2. In some embodiments, the first and second input transistors (M.sub.1 and M.sub.2) can be different from each other, and their respective degeneration inductances can be configured accordingly.

(48) In the example of FIG. 9, operation of the LNA 100 to achieve first and second gain modes can be achieved similar to the examples of FIGS. 3, 4A and 4B.

(49) In the various examples described herein, LNAs are shown to have amplifying transistors and switches implemented as field-effect transistors (FETs). It will be understood that one or more features of the present disclosure can also be implemented utilizing other types of transistors. For example, amplifying transistors and switches can be implemented as bipolar-junction transistors (BJTs), FETs, or any combination thereof.

(50) In some embodiments, an LNA having one or more features as described herein can utilize a second amplification path (also referred to herein as an active gain bypass circuit) to achieve a second gain mode operation, also as described herein. Such a second gain mode of operation can provide, for example, a second gain (G.sub.2) having a third-order input intercept point (IIP3) that is greater than 10 dBm, with minimal or reduced impact to an optimal gain and noise figure combination of a first (e.g., primary) gain mode (G.sub.0).

(51) In some embodiments, and as described herein, the foregoing active gain bypass circuit can be implemented to allow the LNA to maintain a substantially same phase in both of the first and second gain modes. Such same-phase feature is typically important for, for example, receiver error vector magnitude (EVM) performance.

(52) FIG. 10 shows that in some embodiments, an LNA 100 and an active gain bypass circuit 104 having one or more features as described herein can be controlled by a controller 180. Such a controller can provide various control signals to, for example, operate the various amplification transistors and switches (e.g., switch transistors) to achieve various gain modes. In some embodiments, the controller 180 can be configured to include MIPI (Mobile Industry Processor Interface) functionality.

(53) FIG. 11 shows that in some embodiments, some or all of an LNA 100 having one or more features as described herein can be implemented on a semiconductor die 200. Such a die can include a substrate 202, and at least some of an active gain bypass circuit 104 can be implemented on the substrate 202.

(54) In some embodiments, the semiconductor die 100 of FIG. 11 can be a silicon-on-die (SOI) die, and at least the first and second input transistors (M.sub.1 and M.sub.2), the cascode transistor (M.sub.CAS), and the switch S.sub.2 of the second amplification path of the LNA 100 can be implemented on such an SOI die. Such transistors can be implemented as, for example, 0.13 m CMOS devices.

(55) FIGS. 12 and 13 show that in some embodiments, some or all of an LNA 100 having one or more features as described herein can be implemented on a packaged module 300. Such a module can include a packaging substrate 302 configured to receive a plurality of components such as one or more die and one or more passive components.

(56) FIG. 12 shows that in some embodiments, the packaged module 300 can include a semiconductor die 200 that is similar to the example of FIG. 11. Accordingly, such a die can include some or all of the LNA 100, with at least some of an active gain bypass circuit 104 being implemented on the die 200.

(57) FIG. 13 shows that in some embodiments, the packaged module 300 can include a first semiconductor die 210 having an LNA 100 implemented thereon. In the example of FIG. 13, some of an active gain bypass circuit 104 can be implemented on the first die 210, and the rest of the active gain bypass circuit 104 can be implemented on another die 212, outside of a die (e.g., on the packaging substrate 302), or any combination thereof.

(58) FIG. 14 shows that in some embodiments, a diversity receiver module 300 can be an example of the modules 300 of FIGS. 12 and 13. In some embodiments, such a DRx module can be coupled to an off-module filter 513. The DRx module 300 can include a packaging substrate 501 configured to receive a plurality of components and a receiving system implemented on the packaging substrate 501. The DRx module 300 can include one or more signal paths that are routed off the DRx module 300 and made available to a system integrator, designer, or manufacturer to support a filter for any desired band.

(59) The DRx module 300 includes a number of paths between the input and the output of the DRx module 300. The DRx module 300 includes a bypass path between the input and the output activated by a bypass switch 519 controlled by the DRx controller 502. Although FIG. 14 depicts a single bypass switch 519, in some implementations, the bypass switch 519 may include multiple switches (e.g., a first switch disposed physically close to the input and a second switch disposed physically close to the output. As shown in FIG. 14, the bypass path does not include a filter or an amplifier.

(60) The DRx module 300 includes a number of multiplexer paths including a first multiplexer 511 and a second multiplexer 512. The multiplexer paths include a number of on-module paths that include the first multiplexer 511, a bandpass filter 613a-613d implemented on the packaging substrate 501, an amplifier 100a-100d implemented on the packaging substrate 501, and the second multiplexer 512. The multiplexer paths include one or more off-module paths that include the first multiplexer 511, a bandpass filter 513 implemented off the packaging substrate 501, an amplifier 100e, and the second multiplexer 512. The amplifier 514 may be a wide-band amplifier implemented on the packaging substrate 501 or may also be implemented off the packaging substrate 501. In some embodiments, the amplifiers 100a-100d, 100e may be variable-gain amplifiers and/or variable-current amplifiers.

(61) A DRx controller 502 is configured to selectively activate one or more of the plurality of paths between the input and the output. In some implementations, the DRx controller 502 is configured to selectively activate one or more of the plurality of paths based on a band select signal received by the DRx controller 502 (e.g., from a communications controller). The DRx controller 502 may selectively activate the paths by, for example, opening or closing the bypass switch 519, enabling or disabling the amplifiers 100a-100d, 100e, controlling the multiplexers 511, 512, or through other mechanisms. For example, the DRx controller 502 may open or close switches along the paths (e.g., between the filters 613a-613d, 513 and the amplifiers 100a-100d, 100e) or by setting the gain of the amplifiers 100a-100d, 100e to substantially zero.

(62) In the example DRx module 300 of FIG. 14, some or all of the amplifiers 100a-100d, 100e can be provided with active gain bypass circuit 104 having one or more features as described herein. For example, each of such amplifiers (100) is shown to have associated with it an active gain bypass circuit 104.

(63) In some implementations, an architecture, device and/or circuit having one or more features described herein can be included in an RF device such as a wireless device. Such an architecture, device and/or circuit can be implemented directly in the wireless device, in one or more modular forms as described herein, or in some combination thereof. In some embodiments, such a wireless device can include, for example, a cellular phone, a smart-phone, a hand-held wireless device with or without phone functionality, a wireless tablet, a wireless router, a wireless access point, a wireless base station, etc. Although described in the context of wireless devices, it will be understood that one or more features of the present disclosure can also be implemented in other RF systems such as base stations.

(64) FIG. 15 depicts an example wireless device 700 having one or more advantageous features described herein. In some embodiments, an LNA having one or more features as described herein can be implemented in each of one or more places in such a wireless device. For example, in some embodiments, such advantageous features can be implemented in a module such as a diversity receive (DRx) module 300 having one or more low-noise amplifiers (LNAs).

(65) In the example of FIG. 15, power amplifiers (PAs) in a PA module 712 can receive their respective RF signals from a transceiver 710 that can be configured and operated to generate RF signals to be amplified and transmitted, and to process received signals. The transceiver 710 is shown to interact with a baseband sub-system 708 that is configured to provide conversion between data and/or voice signals suitable for a user and RF signals suitable for the transceiver 710. The transceiver 710 is also shown to be connected to a power management component 706 that is configured to manage power for the operation of the wireless device 700. Such power management can also control operations of the baseband sub-system 708 and other components of the wireless device 700.

(66) The baseband sub-system 708 is shown to be connected to a user interface 702 to facilitate various input and output of voice and/or data provided to and received from the user. The baseband sub-system 708 can also be connected to a memory 504 that is configured to store data and/or instructions to facilitate the operation of the wireless device, and/or to provide storage of information for the user.

(67) In the example of FIG. 15, the DRx module 300 can be implemented between one or more diversity antennas (e.g., diversity antenna 730) and the ASM 714. Such a configuration can allow an RF signal received through the diversity antenna 730 to be processed (in some embodiments, including amplification by an LNA) with little or no loss of and/or little or no addition of noise to the RF signal from the diversity antenna 730. Such processed signal from the DRx module 300 can then be routed to the ASM through one or more signal paths.

(68) In the example of FIG. 15, a main antenna 720 can be configured to, for example, facilitate transmission of RF signals from the PA module 512. In some embodiments, receive operations can also be achieved through the main antenna.

(69) A number of other wireless device configurations can utilize one or more features described herein. For example, a wireless device does not need to be a multi-band device. In another example, a wireless device can include additional antennas such as diversity antenna, and additional connectivity features such as Wi-Fi, Bluetooth, and GPS.

(70) Unless the context clearly requires otherwise, throughout the description and the claims, the words comprise, comprising, and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of including, but not limited to. The word coupled, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Additionally, the words herein, above, below, and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word or in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.

(71) The above detailed description of embodiments of the invention is not intended to be exhaustive or to limit the invention to the precise form disclosed above. While specific embodiments of, and examples for, the invention are described above for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. For example, while processes or blocks are presented in a given order, alternative embodiments may perform routines having steps, or employ systems having blocks, in a different order, and some processes or blocks may be deleted, moved, added, subdivided, combined, and/or modified. Each of these processes or blocks may be implemented in a variety of different ways. Also, while processes or blocks are at times shown as being performed in series, these processes or blocks may instead be performed in parallel, or may be performed at different times.

(72) The teachings of the invention provided herein can be applied to other systems, not necessarily the system described above. The elements and acts of the various embodiments described above can be combined to provide further embodiments.

(73) While some embodiments of the inventions have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.