APPLICATION METHOD OF DEMURA DATA HAVING UNIFORM FORMAT

Abstract

An application method of demura data having a uniform format includes: in step S12, it is determined whether demura data having a first format is stored in a first memory; if yes, step S13 is performed; if no, step S16 is performed; in step S13, it is checked whether the demura data having the first format is consistent with demura data having a second format and stored in a second memory; if yes, step S14 is performed; if no, step S16 is performed; in step S14, the demura data having the first format in the first memory is read; in step S15, a demura data compensation is activated; and in step S16, demura data having the first format is generated, according to the demura data having the second format and stored in the second memory, and stored; step S15 is performed.

Claims

1. An application method of demura data having a uniform format, comprising: in step S11, a system chip is initialized; in step S12, it is determined whether demura data having a first format is stored in a first memory; if yes, step S13 is performed; if no, step S16 is performed; in step S13, it is checked whether the demura data having the first format is consistent with demura data having a second format and stored in a second memory; if the demura data having the first format is consistent with the demura data having the second format, step S14 is performed; if the demura data having the first format is not consistent with the demura data having the second format, step S16 is performed; in step S14, the demura data having the first format in the first memory is read; in step S15, a demura data compensation is activated; and in step S16, demura data having the first format is generated, according to the demura data having the second format and stored in the second memory, and stored; step S15 is performed.

2. The application method of the demura data having the uniform format of claim 1, wherein step S13 comprises: in step S131, a cyclic redundancy check code of the demura data having the first format and stored in the first memory is read; in step S132, a cyclic redundancy check code of the demura data having the second format and stored in the second memory is read; and in step S133, a cyclic redundancy check is performed on the cyclic redundancy check codes read in steps S131 and S132; if the cyclic redundancy check code of the demura data having the first format is consistent with the cyclic redundancy check code of the demura data having the second format, step S14 is performed; if the cyclic redundancy check code of the demura data having the first format is not consistent with the cyclic redundancy check code of the demura data having the second format, step S16 is performed.

3. The application method of the demura data having the uniform format of claim 1, wherein step S16 comprises: in step S161, the demura data having the second format and stored in the second memory is read; in step S162, demura information is extracted from the demura data having the second format; in step S163, the demura information is written, in the first format, into the first memory, and the demura information is loaded into a register of the system chip; and in step S164, the cyclic redundancy check code of the demura data having the second format is written into the first memory, and step S15 is performed.

4. The application method of the demura data having the uniform format of claim 1, wherein the system chip is a timing controller chip.

5. The application method of the demura data having the uniform format of claim 2, wherein the system chip is a timing controller chip.

6. The application method of the demura data having the uniform format of claim 3, wherein the system chip is a timing controller chip.

7. The application method of the demura data having the uniform format of claim 4, wherein the first memory is a memory on a control board, and the second memory is a memory on an X-board.

8. The application method of the demura data having the uniform format of claim 7, wherein the memory on the control board is a flash memory, and the memory on the X-board is a flash memory.

9. The application method of the demura data having the uniform format of claim 1, wherein the system chip is a system on a chip (SoC).

10. The application method of the demura data having the uniform format of claim 2, wherein the system chip is a system on a chip (SoC).

11. The application method of the demura data having the uniform format of claim 3, wherein the system chip is a system on a chip (SoC).

12. The application method of the demura data having the uniform format of claim 9, wherein the first memory is a memory on the SoC, and the second memory is a memory on the X-board.

13. The application method of the demura data having the uniform format of claim 12, wherein the memory on the SoC is an embedded multimedia card (eMMC), and the memory on the X-board is a flash memory.

14. An application method of demura data having a uniform format, comprising: in step S301, the timing controller chip reads firmware in a memory of a control board; in step S302, demura data having a second format in a memory of an X-board is read; and in step S303, a demura data compensation is activated.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0069] The technical solution, as well as other beneficial advantages, of the present disclosure will become apparent from the following detailed description of embodiments of the present disclosure, with reference to the attached drawings.

[0070] FIG. 1 illustrates a structure diagram of a conventional TFT-LCD device.

[0071] FIG. 2 illustrates an architecture diagram of a conventional demura system.

[0072] FIG. 3 illustrates a flowchart of an application method of demura data having a uniform format in accordance with a preferred embodiment of the present disclosure.

[0073] FIG. 4 illustrates an architecture diagram of a demura system using the embodiment in FIG. 3.

[0074] FIG. 5 illustrates that the demura data in the embodiment of FIG. 3 is converted.

[0075] FIG. 6 illustrates an architecture diagram of a demura system using the embodiment in FIG. 7.

[0076] FIG. 7 illustrates a flowchart of an application method of demura data having a uniform format in accordance with another preferred embodiment of the present disclosure.

[0077] FIG. 8 illustrates an architecture diagram of a demura system using the embodiment in FIG. 9.

[0078] FIG. 9 illustrates a flowchart of an application method of demura data having a uniform format in accordance with yet another preferred embodiment of the present disclosure.

DETAILED DESCRIPTION OF EMBODIMENTS

[0079] An application method of demura data having a uniform format provided by the present disclosure mainly includes the following steps.

[0080] In step S11, a system chip is initialized.

[0081] In step S12, it is determined whether demura data having a first format is stored in a first memory. If yes, step S13 is performed. If no, step S16 is performed.

[0082] In step S13, it is checked whether the demura data having the first format is consistent with demura data having a second format and stored in a second memory. If the demura data having the first format is consistent with the demura data having the second format, step S14 is performed. If the demura data having the first format is not consistent with the demura data having the second format, step S16 is performed.

[0083] In step S14, the demura data having the first format in the first memory is read.

[0084] In step S15, a demura data compensation is activated.

[0085] In step S16, demura data having the first format is generated, according to the demura data having the second format and stored in the second memory, and stored. Step S15 is performed

[0086] Step S13 may include the following steps.

[0087] In step S131, a cyclic redundancy check code of the demura data having the first format and stored in the first memory is read.

[0088] In step S132, a cyclic redundancy check code of the demura data having the second format and stored in the second memory is read.

[0089] In step S133, a cyclic redundancy check is performed on the cyclic redundancy check codes read in steps S131 and S132. If the cyclic redundancy check code of the demura data having the first format is consistent with the cyclic redundancy check code of the demura data having the second format, step S14 is performed. If the cyclic redundancy check code of the demura data having the first format is not consistent with the cyclic redundancy check code of the demura data having the second format, step S16 is performed.

[0090] Step S16 may include the following steps.

[0091] In step S161, the demura data having the second format and stored in the second memory is read.

[0092] In step S162, demura information is extracted from the demura data having the second format.

[0093] In step S163, the demura information is written, in the first format, into the first memory, and the demura information is loaded into a register of the system chip.

[0094] In step S164, the cyclic redundancy check code of the demura data having the second format is written into the first memory. Step S15 is performed.

[0095] In the present disclosure, the first format and the second format respectively refer to a demura data format provided by a vendor and a uniform format provided by a panel manufacturer. The system chip is a timing controller chip. In one aspect, the system chip may be the timing controller chip. The first memory may be a memory on a control board. The second memory is a memory on an X-board. The memory on the control board is a flash memory. The memory on the X-board is a flash memory. In another aspect, the system chip may be a system on a chip (SoC). The first memory is a memory on the SoC. The second memory is a memory on the X-board. The memory on the SoC is an embedded multimedia card (eMMC). The memory on the X-board is a flash memory.

[0096] In the following description, China Star Optoelectronics Technology Co., Ltd (CSOT) serves as an example of the panel manufacturer to explain the application method of demura data having the uniform format provided by the present disclosure. In the following embodiments, demura data having a uniform format (hereinafter referred to as the demura data having the CSOT format) is targetedly designed in advance according to characteristics of a CSOT panel in combination with various timing controller chips and SoC s. For all types of CSOT panels, the demura data having the CSOT format is used and does not require being formulated according to the corresponding timing controller chip or SoC.

[0097] Please refer to FIG. 3 and FIG. 4. FIG. 3 illustrates a flowchart of an application method of demura data having a uniform format in accordance with a preferred embodiment of the present disclosure. FIG. 4 illustrates an architecture diagram of a demura system using the embodiment in FIG. 3. The present embodiment is compatible with the conventional timing controller chips and is a driving scheme aimed at the timing controller chips which are massively produced. The architecture of the demura system mainly includes: a system on a chip (SoC) having an embedded multimedia card (eMMC) disposed thereon and configured to control a timing controller chip to be powered up; a timing controller chip mainly including a flash memory for storage (the flash memory can be disposed on a control board), a demura module configured to implement a mura data compensation, and a mapping module configured to convert the format of the demura data (the mapping module can decode the demura data having the CSOT format and convert the same into demura data having a format which is provided by a vendor and can be directly read); and a flash memory on an X-board of an TFT-LCD panel configured to store the demura data having the uniform format provided by a panel manufacturer. The demura having the uniform format is the demura data having the CSOT format in the present embodiment.

[0098] It can be appreciated from FIG. 3 in combination with FIG. 4 that the timing controller chip performs the following steps after the SoC controls the timing controller chip to be powered up and activated. The memories of the control board and the X-board are flash memories in the present embodiment. The application method includes the following steps.

[0099] In step S101, the timing controller chip reads firmware in the memory of the control board.

[0100] In step S102, it is determined whether demura data having a first format is stored in the memory of the control board. If yes, step S103 is performed. If no, step S108 is performed.

[0101] In step S103, a cyclic redundancy check code of the demura data having the first format and stored in the memory is read.

[0102] In step S104, a cyclic redundancy check code of the demura data having a second format and stored in the memory of the X-board is read.

[0103] In step S105, a cyclic redundancy check is performed on the cyclic redundancy check codes read in steps S103 and S104. If the cyclic redundancy check code of the demura data having the first format is consistent with the cyclic redundancy check code of the demura data having the second format, step S106 is performed. If the cyclic redundancy check code of the demura data having the first format is not consistent with the cyclic redundancy check code of the demura data having the second format, step S108 is performed.

[0104] In step S106, the demura data having the first format in the memory of the control board is read.

[0105] In step S107, a demura data compensation is activated.

[0106] In step S108, the demura data having the second format and stored in the memory of the X-board is read.

[0107] In step S109, demura information is extracted from the demura data having the second format.

[0108] In step S110, the demura information is written, in the first format, into the memory of the control board, and the demura information is loaded into a register of the timing controller chip.

[0109] In step S111, the cyclic redundancy check code of the demura data having the second format is written into the memory of the control board. Step S107 is performed.

[0110] In step S102, time required for activating the panel for the first time is increased. A speed of activating the panel after the first time is the same as a speed in which the demura data having the format provided by the vendor is directly used.

[0111] Please refer to FIG. 5. FIG. 5 illustrates that the demura data in the embodiment of FIG. 3 is converted. The conventional timing controller chips cannot directly identify the demura data having the CSOT format. Accordingly, it is necessary to perform a specific process by the timing controller chip, so that the demura data having the CSOT format can be compatible. Content stored in the flash memory of the X-board and including the demura data having the CSOT format is shown in the left part in FIG. 5. The demura data having the CSOT format includes the cyclic redundancy check code, parameters, and a look-up table. Content stored in the flash memory of the control board and including the firmware, the cyclic redundancy check code, the demura data having the format provided by the vendor is shown in the right part in FIG. 5. The demura data having the format provided by the vendor includes parameters and a look-up table.

[0112] A core of the present scheme of the preferred embodiment is to use a micro control unit (MCU) embedded in the timing controller chip to decode the demura data having the CSOT format and convert the same into the demura data having the format which is provided by the vendor and can be directly read by the timing controller chip. It is determined whether the cyclic redundancy check code of the demura data having the CSOT format in the flash memory of the X-board is consistent with the cyclic redundancy check code of the demura data in the flash memory of the control board, before the timing controller chip is powered up. If the cyclic redundancy check code of the demura data having the CSOT format in the flash memory of the X-board is consistent with the cyclic redundancy check code of the demura data in the flash memory of the control board, the timing control chip reads the demura data having the format provided by the vendor form the flash memory of the control board. If the cyclic redundancy check code of the demura data having the CSOT format in the flash memory of the X-board is not consistent with the cyclic redundancy check code of the demura data in the flash memory of the control board, the converting process is performed again.

[0113] Please refer to FIG. 6 and FIG. 7. FIG. 7 illustrates a flowchart of an application method of demura data having a uniform format in accordance with another preferred embodiment of the present disclosure. FIG. 6 illustrates an architecture diagram of a demura system using the embodiment in FIG. 7. The present embodiment is a driving scheme aimed at an SoC without a timing controller chip. The architecture of the demura system mainly includes: a system on a chip (SoC) having an embedded multimedia card (eMMC) disposed thereon and configured to implement functions of a timing controller chip for controlling timing, a demura module for a mura data compensation, and a mapping module for converting the format of the demura data; and a flash memory on an X-board of an TFT-LCD panel configured to store the demura data having the uniform format provided by a panel manufacturer. The demura having the uniform format is the demura data having the CSOT format in the present embodiment.

[0114] It can be appreciated from FIG. 6 in combination with FIG. 7 that the SoC performs the following steps after the SoC is powered up and activated. In the present embodiment, the memory of the Soc is an embedded multimedia card (eMMC), and the memory of the X-board is a flash memory. The application method includes the following steps.

[0115] In step S201, the SoC is initialized.

[0116] In step S202, it is determined whether demura data having a first format is stored in the memory of the SoC. If yes, step S203 is performed. If no, step S208 is performed.

[0117] In step S203, a cyclic redundancy check code of the demura data having the first format and stored in the memory of the SoC is read.

[0118] In step S204, a cyclic redundancy check code of the demura data having a second format and stored in the memory of the X-board is read.

[0119] In step S205, a cyclic redundancy check is performed on the cyclic redundancy check codes read in steps S203 and S204. If the cyclic redundancy check code of the demura data having the first format is consistent with the cyclic redundancy check code of the demura data having the second format, step S206 is performed. If the cyclic redundancy check code of the demura data having the first format is not consistent with the cyclic redundancy check code of the demura data having the second format, step S208 is performed.

[0120] In step S206, the demura data having the first format and stored in the memory of the SoC is read.

[0121] In step S207, a demura data compensation is activated.

[0122] In step S208, the demura data having the second format and stored in the memory of the X-board is read.

[0123] In step S209, demura information is extracted from the demura data having the second format.

[0124] In step S210, the demura information is written, in the first format, into the memory of the SoC, and the demura information is loaded into a register of the SoC.

[0125] In step S211, the cyclic redundancy check code of the demura data having the second format is written into the memory of the SoC. Step S207 is performed.

[0126] In step S202, time required for activating the panel for the first time is increased. A speed of activating the panel after the first time is the same as a speed in which the demura data having the format provided by the vendor is directly used.

[0127] The SoC is designed by a system manufacturer. In all types of the CSOT panels (CSOT serves as a panel manufacturer), the demura data having the CSOT format is used. A driving scheme of the SoC of the system manufacturer is similar to that in FIG. 3. That is, a converting process is performed by a micro control unit (MCU) embedded in the chip. The conversion of the demura data can be referred to FIG. 5. However, the performance of the MCU integrated into the SoC is better than that of the MCU integrated into the timing controller chip, and thus the converting speed of the SoC is faster than that of the timing controller chip.

[0128] Please refer to FIG. 8 and FIG. 9. FIG. 9 illustrates a flowchart of an application method of demura data having a uniform format in accordance with yet another preferred embodiment of the present disclosure. FIG. 8 illustrates an architecture diagram of a demura system using the embodiment in FIG. 9. The present embodiment is a driving scheme aimed at a timing controller chip which will be newly developed in the future. When CSOT serving as the panel manufacturer and a vendor of a new timing controller chip cooperate to develop the new timing controller chip, the new timing controller chip requires reading the demura data having the CSOT format directly. As such, the new timing controller chip does not require performing the converting process. The architecture of the demura system mainly includes: a system on a chip (SoC) having an embedded multimedia card (eMMC) disposed thereon and configured to control a timing controller chip to be powered up; a timing controller chip mainly including a flash memory for storage (the flash memory can be disposed on a control board) and a demura module configured to implement a mura data compensation; and a flash memory on an X-board of an TFT-LCD configured to store the demura data having the uniform format provided by a panel manufacturer. The demura having the uniform format is the demura data having the CSOT format in the present embodiment.

[0129] It can be appreciated from FIG. 8 in combination with FIG. 9 that the timing controller chip performs the following steps after the SoC controls the timing controller chip to be powered up and activated. In the present embodiment, the memories of the control board and the X-board are flash memories. The application method includes the following steps.

[0130] In step S301, the timing controller chip reads firmware in a memory of a control board.

[0131] In step S302, demura data having a second format in a memory of a

[0132] X-board is read.

[0133] In step S303, a demura data compensation is activated.

[0134] In summary, in the application method of the demura data having the uniform format of the present disclosure, the demura data having various conventional formats can be unified by the above-mentioned three demura activation processes. As a result, the difficulty of management and control can be decreased significantly. Furthermore, the develop difficulty of the demura function can be decreased significantly when system manufacturer customers purchase the CSOT panel products without timing controller chips. All types of the CSOT panels can be compatible after only one time of the process of importing the demura data having the CSOT format is performed.

[0135] In summary, many other possible modifications and variations can be made by those skilled in the art without departing from the spirit and scope of the present disclosure as hereinafter claimed, and those modifications and variations are considered encompassed in the scope of protection defined by the claims of the present disclosure.