Method for calibrating capacitor voltage coefficient of high-precision successive approximation analog-to-digital converter

Abstract

The present disclosure relates to the field of semiconductor integrated circuits, and to a method for calibrating a capacitor voltage coefficient of a high-precision successive approximation analog-to-digital converter (SAR ADC). The method includes: calibrating a voltage coefficient; obtaining a sampled charged charge according to a capacitance model with the voltage coefficient; according to an INL value obtained by testing, first verifying whether a maximum value of INL occurs in the place shown in Equation 3, then obtaining two very close second-order capacitor voltage coefficients according to Equation 4, and taking an average value thereof as a second-order capacitor voltage coefficient; and then calibrating the second-order capacitor voltage coefficient in a digital domain. In the present disclosure, a capacitor voltage coefficient can be extracted based on INL and the capacitor voltage coefficient is calibrated at a digital backend without adding an analog calibration circuit, thereby improving conversion accuracy of the ADC.

Claims

1. A method for calibrating a capacitor voltage coefficient of a high-precision successive approximation analog-to-digital converter (SAR ADC), comprising: calibrating a voltage coefficient, a capacitance model with the voltage coefficient is shown in Equation 1:
C=C.sub.0*(1+1*V+2*V.sup.2+ . . . )(1) wherein C is an actual value of a capacitor, C.sub.0 is a nominal value of the capacitor when a voltage difference between two ends of the capacitor is 0, 1 is a first-order capacitor voltage coefficient, V is a voltage difference between the two ends of the capacitor, and 2 is a second-order capacitor voltage coefficient; sampling to obtain a charged charge:
Q=C.sub.0*(V+0.5*1*V.sup.2+*2*V.sup.3+ . . . )(2) wherein the ADC uses a differential structure, a related term 0.5*1*V.sup.2 of the first-order voltage coefficient is canceled during sampling; if a high-order capacitor voltage coefficient is omitted, a related term *2*V.sup.3 of the second-order capacitor voltage coefficient becomes a dominant factor of nonlinearity, and the second-order capacitor voltage coefficient is extracted and calibrated according to an integral nonlinearity (INL) curve of the ADC; and the shape of the INL curve is determined by the second-order voltage coefficient, and a digital code for generating maximum INL is shown in Equation 3:
Dout1=min(Dout)/{square root over (3)}
Dout2=max(Dout)/{square root over (3)}(3) wherein Dout is an output digital code of the ADC, a value at a minimum value of INL in a negative value range of Dout is set to Dout1, a value at a maximum value of INL in a positive value range of Dout is set to Dout2, min(Dout) represents a minimum value of Dout, and max(Dout) represents a maximum value of Dout; and a maximum INL value is shown in Equation 4:
max(INL)=2*21*(max(Dout)).sup.3/3.sup.2.5
min(INL)=2*22*(min(Dout)).sup.3/3.sup.2.5(4) wherein max(INL) represents the maximum value of INL, min(INL) represents the minimum value of INL, 21 represents a second-order voltage coefficient value derived from the maximum value of INL, and 22 represents a second-order voltage coefficient value derived from the minimum value of INL; according to an INL value obtained by testing, first verifying whether a maximum value of INL occurs in the place shown in Equation 3, then obtaining two very close second-order capacitor voltage coefficients according to Equation 4, and taking an average value thereof as a second-order capacitor voltage coefficient, as shown in Equation 5: $\begin{array}{cc}2=\frac{\mathrm{21}+\mathrm{22}}{2};& \left(5\right)\end{array}$ and then calibrating the second-order capacitor voltage coefficient in a digital domain, a calibration formula is shown in Equation 6:
Dout_cal=Dout*2*Dout.sup.3(6) wherein Dout_cal is a calibrated ADC digital output code.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) In order to make the object, the technical solution and the beneficial effects of the present disclosure clearer, the present disclosure provides the following drawings for description.

(2) FIG. 1 shows an N-bit SAR ADC.

(3) FIG. 2 shows input and output characteristics of the successive approximation ADC.

(4) FIG. 3 is an INL graph introduced by a capacitor voltage coefficient.

(5) FIG. 4 shows a calibration process of a capacitor voltage coefficient.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(6) The preferred embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

(7) FIG. 1 shows a circuit structure of a SAR ADC. An N-bit SAR ADC includes N binary weight capacitors. During phase sampling, a switch connected to input signals Vip and Vin in a switch S1 is turned on. A switch S2 is turned on, an upper pole plate of the capacitor is connected to the input signal, and a lower pole plate of the capacitor is connected to a common mode level. If the capacitor has a voltage coefficient, a sampled charge also has nonlinearity. After the sampling is completed, a conversion phase is entered, the switch connected to the input signals Vip and Vin in the switch S1 is disconnected, the switch S2 is disconnected, and the lower pole plate of the capacitor is unconnected.

(8) As shown in FIG. 1, a capacitor voltage coefficient affects the sampling accuracy of the signal, thereby constraining the linearity of the SAR ADC. In order to obtain a higher signal-to-noise ratio, the voltage coefficient needs to be calibrated. A capacitance model with the voltage coefficient is shown in Equation 1:
C=C.sub.0*(1+1*V+2*V.sup.2+ . . . )(1)

(9) A charged charge is sampled as:
Q=C.sub.0*(V+0.5*1*V.sup.2+*2*V.sup.3+ . . . )(2)

(10) Because the ADC uses a differential structure, a related term 0.5*1*V.sup.2 of a first-order voltage coefficient is canceled during sampling. If a high-order capacitor voltage coefficient is omitted, a related term *2*V.sup.3 of a second-order capacitor voltage coefficient becomes a dominant factor of nonlinearity. In the present disclosure, the second-order capacitor voltage coefficient is extracted and calibrated according to an INL curve of the ADC. FIG. 2 shows a graph of input and output characteristics of the ADC. If the ADC is an ideal device, transmission characteristics thereof are shown by a dotted line f1. However, if a capacitor in the ADC has a voltage coefficient, a very large error is introduced to a large input signal during sampling, and a transmission curve thereof is shown by a solid line f2, and nonlinearity appears. A dashed line f3 represents an ideal conversion curve after fitting of two ends, INL is obtained by the subtraction of f2 and f3, and the shape of INL is shown in FIG. 3. It can be learned that the shape of the INL curve is determined by a second-order voltage coefficient, and a digital code for generating the maximum INL is shown in Equation 3:
Dout1=min(Dout)/{square root over (3)}
Dout2=max(Dout)/{square root over (3)}(3)

(11) A maximum INL value is shown in Equation 4:
max(INL)=2*21*(max(Dout)).sup.3/3.sup.2.5
min(INL)=2*22*(min(Dout)).sup.3/3.sup.2.5(4)

(12) According to an INL value obtained by testing, whether a maximum value of INL occurs in the place shown in Equation 3 is first verified, then two very close second-order capacitor voltage coefficients can be obtained according to Equation 4, and an average value thereof is taken as a second-order capacitor voltage coefficient, as shown in Equation 5:

(13) $\begin{array}{cc}2=\frac{\mathrm{21}+\mathrm{22}}{2}& \left(5\right)\end{array}$

(14) Then the second-order capacitor voltage coefficient is calibrated in a digital domain, a calibration formula is shown in Equation 6:
Dout_cal=Dout*2*Dout.sup.3(6)

(15) In the present disclosure, the capacitor voltage coefficient is extracted according to the INL test curve. This requires the INL curve to fully represent information about the capacitor voltage coefficient. Therefore, before the voltage coefficient is calibrated, capacitor weight calibration needs to be performed to eliminate an error of a capacitor mismatch, and a calibration process is shown in FIG. 4. In a first step, original code information of the ADC is collected, in the second step, the calibration of the capacitor mismatch is completed according to the collected original code, in the third step, the INL curve after the mismatch is calibrated is tested, and in the final step, the second-order capacitor voltage coefficient is obtained according to the INL curve obtained by testing, and the second-order capacitor voltage coefficient is calibrated in the digital domain.

(16) Finally, it should be noted that the foregoing preferred embodiments are merely intended for illustrating rather than limiting the technical solution of the present disclosure. Although the present disclosure has been described in detail through the foregoing preferred embodiments, those skilled in the art should understand that various alterations may be performed to the form and details of the present disclosure without departing from the scope defined by the claims of the present disclosure.