Abstract
Systems and methods which provide low-loss dielectric microstrip line (DML) circuits for use with respect to signals in the terahertz frequency range are described. Low-loss DML integrated circuits of embodiments, such as may comprise DML transmission lines, DML couplers, DML crossovers, etc., may be based on silicon technology and are adapted for signal frequencies in the range of 750-925 GHz. A DML circuit implementation may be comprised of silicon on insulator based DML structure having a silicon dioxide (SiO.sub.2) insulation layer as the middle layer of the DML, wherein the device layer (HRSi) and the handle layer (HRSi) are the top and bottom layers of the DML. A high-precision fabrication process for the SOI wafer, wherein the height of the dielectric microstrip lines can be accurately controlled, may be utilized to fabricate DML circuits of embodiments. A non-contact measurement technology may be used to test the DML circuits of embodiments.
Claims
1. A silicon on insulator (SOI) based dielectric microstrip line (DML) circuit configured for operation with signals in a range of 750-925 GHz, the DML circuit comprising: a silicon dioxide (SiO.sub.2) insulation layer of the SOI providing a middle layer of the DML circuit, wherein the middle SiO2 layer of the DML circuit has a thickness t; a high-resistivity silicon (HRSi) layer providing a top layer of the DML circuit, wherein the top HRSi layer of the DML circuit has height h.sub.1, and wherein a DML structure formed in the top HRSi layer of the DML circuit has width w; and a HRSi layer providing a bottom layer of the DML, wherein the bottom HRSi layer of the DML circuit has height h.sub.2, and wherein values for parameters h.sub.1, h.sub.2, and w are selected for a particular value of parameter t and configure the DML circuit for the operation with the signals in the range of 750-925 GHz, wherein the DML circuit comprises a crossover circuit having two mutually perpendicular DML structures in a same plane.
2. The SOI based DML circuit of claim 1, wherein the values for parameters w, h.sub.1, and h.sub.2 are selected to achieve a smallest attenuation constant of DML for the particular value of parameter t.
3. The SOI based DML circuit of claim 1, wherein the particular value of parameter t is 2 m, the selected values for parameters w, h.sub.1, and h.sub.2 are 150 m, 65 m, and 65 m respectively.
4. The SOI based DML circuit of claim 1, wherein the top HRSi layer of the DML circuit comprises a device layer and the bottom HRSi layer of the DML circuit comprises a handle layer.
5. The SOI based DML circuit of claim 1, wherein each of the two mutually perpendicular DML structures comprise DMLs with dimensions w=150 m, h.sub.1=65 m, h.sub.2=65 m and t=2 m.
6. The SOI based DML circuit of claim 1, wherein the crossover circuit provides at least 24 dB isolation between inputs of the mutually perpendicular DML structures.
7. The SOI based DML circuit of claim 6, wherein the isolation between inputs of the mutually perpendicular DML structures is 25.455.54 dB.
8. A silicon on insulator (SOI) based dielectric microstrip line (DML) circuit configured for operation with signals in a range of 750-925 GHz, the DML circuit comprising: a silicon dioxide (SiO.sub.2) insulation layer of the SOI providing a middle layer of the DML circuit, wherein the middle SiO.sub.2 layer of the DML circuit has a thickness t; a high-resistivity silicon (HRSi) layer providing a top layer of the DML circuit, wherein the top HRSi layer of the DML circuit has height h.sub.l, and wherein a DML structure formed in the top HRSi layer of the DML circuit has width w; and an HRSi layer providing a bottom layer of the DML, wherein the bottom HRSi layer of the DML circuit has height h.sub.2, and wherein values for parameters h.sub.l, h.sub.2, and w are selected for a particular value of parameter t and configure the DML circuit for the operation with the signals in the range of 750-925 GHz, wherein the DML circuit comprises a coupler circuit having two DML structures having a 45 intersection angle in a same plane.
9. The SOI based DML circuit of claim 8, wherein each of the intersecting DML structures comprise DMLs with dimensions w=150 m, h.sub.1=65 m, h.sub.2=65 m and t=2 m.
10. The SOI based DML circuit of claim 8, wherein the coupler circuit provides a coupler factor of at least 10 dB.
11. The SOI based DML circuit of claim 10, wherein the coupler factor is 13.223.23 dB.
12. A silicon on insulator (SOI) based dielectric microstrip line (DML) circuit configured for operation with signals in a range of 750-925 GHz, the DML circuit comprising: a silicon dioxide (SiO.sub.2) insulation layer of the SOI providing a middle layer of the DML circuit, wherein the middle SiO.sub.2 layer of the DML circuit has a thickness t; a high-resistivity silicon (HRSi) layer providing a top layer of the DML circuit, wherein the top HRSi layer of the DML circuit has height h.sub.1, and wherein a DML structure formed in the top HRSi layer of the DML circuit has width w; and an HRSi layer providing a bottom layer of the DML, wherein the bottom HRSi layer of the DML circuit has height h.sub.2, and wherein values for parameters h.sub.1, h.sub.2, and w are selected for a particular value of parameter t and configure the DML circuit for the operation with the signals in the range of 750-925 GHz, wherein the DML circuit comprises a H-plane dielectric horn antenna.
13. The SOI based DML circuit of claim 12, wherein the H-plane dielectric horn antenna configures the DML circuit for operation with a non-contact measurement system.
14. The SOI based DML circuit of claim 12, wherein the H-plane dielectric horn antenna comprises a dielectric extension area of length g, wherein a value of parameter g is selected to match the H-plane dielectric horn antenna to free space.
15. A silicon on insulator (SOT) based dielectric microstrip line (DML) circuit configured for operation with signals in a range of 750-925 GHz, the SOT based DML circuit comprising: a first layer having height h.sub.1 and width w, wherein w is at least 150 m and h.sub.1, is 65 m or less; a second layer having thickness t, wherein t is at least 2 m; and a third layer having height h.sub.2, wherein t is at least 2 m, w is at least 150 m, h.sub.1, is 65 m or less, and h.sub.2 is 65 m or less and configure the DML circuit for the operation with the signals in the range of 750-925 GHz, wherein the DML circuit comprises a crossover circuit having two mutually perpendicular DML structures in a same plane or the DML circuit comprises a coupler circuit having two DML structures having a 45 intersection angle in a same plane.
16. The SOI based DML circuit of claim 15, wherein the first and third layers comprise a high-resistivity silicon (HRSi) layers and the second layer comprises a silicon dioxide (SiO.sub.2) insulation layer.
17. The SOI based DML circuit of claim 15, wherein the values for parameters w, h.sub.1, and h.sub.2 are selected to achieve a smallest attenuation constant of DML for the value of the thickness parameter t.
Description
BRIEF DESCRIPTION OF THE DRAWING
(1) For a more complete understanding of the present invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawing, in which:
(2) FIG. 1A shows a cross-sectional view of a DML structure as may be utilized according to embodiments of the invention.
(3) FIG. 1B shows the attenuation constant of the E.sup.y.sub.11 mode of a DML structure as may be utilized according to embodiments of the invention.
(4) FIG. 1C shows the simulated loss contributions of a DML fabricated according to embodiments of the invention.
(5) FIG. 1D shows the complex magnitude E-field distribution (E.sup.y.sub.11 mode) of a DML structure as may be utilized according to embodiments of the invention.
(6) FIG. 2A shows normalized phase constant data of a DML structure as may be utilized according to embodiments of the invention.
(7) FIG. 2B shows attenuation constant data of a DML structure as may be utilized according to embodiments of the invention.
(8) FIG. 3A shows a cross-sectional view of two DML structures disposed in proximity as may be utilized by DML circuits of embodiments of the invention.
(9) FIG. 3B shows the normalized dispersions of the E.sup.y.sub.11 mode of a single DML structure and the even and odd modes of two adjacent DML structures as may be utilized according to embodiments of the invention.
(10) FIG. 4A shows a top view of a crossover circuit implemented using DML structures of embodiments of the invention.
(11) FIG. 4B shows the H-field distribution in the SiO.sub.2 layer of a DML crossover circuit of embodiments of the invention.
(12) FIG. 4C shows the EM vector distribution in the SiO.sub.2 layer of a DML crossover circuit of embodiments of the invention.
(13) FIG. 4D shows the EM vector distribution of a rectangular metallic waveguide-based crossover structure.
(14) FIG. 4E shows simulated results of crossover operation of a DML crossover circuit of embodiments of the invention.
(15) FIG. 5A shows a top view of a coupler circuit implemented using DML structures of embodiments of the invention.
(16) FIG. 5B shows the Horfield distribution in the SiO.sub.2 layer of a DML coupler circuit of embodiments of the invention.
(17) FIG. 5C shows simulated results of coupling operation of a DML coupler circuit of embodiments of the invention.
(18) FIG. 6 shows an exemplary non-contact measurement system configured for use in testing DML circuits of embodiments of the present invention.
(19) FIG. 7A shows a top view of an implementation of H-plane dielectric horn antennas based on DML as may be utilized according to embodiments of the invention.
(20) FIG. 7B shows the simulated S.sub.11 of the antenna configuration of FIG. 7A.
(21) FIG. 8A shows a 3D DML bend structure, and its associated performance, as may be utilized according to embodiments of the invention.
(22) FIG. 8B shows the simulated S-parameter of the DML bend of FIG. 8A.
(23) FIGS. 9A-9E show integrated implementations of DML samples as may be fabricated according to embodiments of the invention.
(24) FIG. 10 shows a cross-section view of a DML structure fabricated according to embodiments of the invention.
(25) FIGS. 11A-11C show masks as may be utilized in a fabrication process of embodiments of the invention.
(26) FIGS. 12A and 12B illustrate a fabrication process to provide DML circuits according to embodiments of the invention.
(27) FIG. 13A shows a top view of small and large DML samples fabricated according to embodiments of the invention.
(28) FIG. 13B shows a scanning electron micrograph (SEM) displaying the cross-section of the fabricated DML samples of FIG. 13A.
(29) FIG. 13C shows a top view of a H-plane dielectric horn antenna based on the DML fabricated according to embodiments of the invention.
(30) FIG. 14 shows the complex magnitude E-field distribution (E).sup.y.sub.11 mode) in the cross-sectional view of DML circuits fabricated according to embodiments of the invention.
(31) FIG. 15A shows the measured and simulated results of small and large DML samples of embodiments of the invention.
(32) FIG. 15B shows the calculated attenuation constants of DML samples of embodiments of the invention.
(33) FIG. 15C shows the calculated phase constants of DML samples of embodiments of the invention.
(34) FIG. 15D shows the calculated insertion loss per wavelength of DML samples of embodiments of the invention.
(35) FIG. 16A shows the measured results of a DML crossover circuit fabricated in accordance with embodiments of the invention.
(36) FIG. 16B shows the measured results of a DML coupler circuit fabricated in accordance with embodiments of the invention.
(37) FIG. 16C shows the normalized results of a DML crossover circuit fabricated in accordance with embodiments of the invention.
(38) FIG. 16D shows the normalized results of a DML coupler circuit fabricated in accordance with embodiments of the invention.
DETAILED DESCRIPTION OF THE INVENTION
(39) Characterization of DML
(40) Low-loss dielectric microstrip line (DML) circuits based on silicon (Si) technology for use with respect to terahertz (THz) frequencies (e.g., operable with respect to frequencies in the 750-925 GHz range) are provided according to embodiments of the present invention. A DML circuit implementation of embodiments is comprised of a silicon on insulator (SOI) wafer configuration, such as may comprise a silicon dioxide (SiO.sub.2) insulation layer as the middle layer and high-resistivity silicon (HRSi) layers provide the top layer (e.g., comprised of the HRSi device layer) and the bottom layer (e.g., comprised of the HRSi handle layer).
(41) A cross-sectional view (not to scale) of a DML structure (DML structure 101) as may be utilized by DML circuits of embodiments of the invention is shown in FIG. 1A. Layers 111 and 113 of FIG. 1A may, for example, comprise HRSi (e.g., HRSi, such as may have a resistivity ()800 .Math.cm, wherein the relative dielectric constant is 11.9) and layer 112 may, for example, comprise SiO.sub.2 (e.g., SiO.sub.2 wherein the relative dielectric constant is 4), It should be appreciated that in the exemplary DML structure of FIG. 1A w represents the width of the DML microstrip, k represents the height of the DML circuit upper layer (layer 111), h.sub.2 represent the height of the DML circuit lower layer (layer 113), and t represents the thickness of the middle, dielectric layer (layer 112).
(42) In configuring a DML circuit adapted for use with respect to THz frequencies according to embodiments of the invention, the parameters w (DML structure width), h.sub.1 (DML structure top layer height), and h.sub.2 (DML structure bottom layer height) are selected to achieve the smallest attenuation constant of DML. The results, as simulated by HESS 14.0 with driven modal, provided by various values of the foregoing parameters for a DML structure having a dielectric layer thickness (t) of 2 m are shown in FIG. 1B. In particular, FIG. 1B shows the attenuation constant of the E.sup.y.sub.11 mode. As can be appreciated from the graph of FIG. 1B, the arithmetic average attenuation constant () is 0.16 dB/mm with w=150 m, h.sub.1=65 m and h.sub.2=65 m, which is the best result in the exemplary parameter study. With h.sub.1 or h.sub.2 increasing, a will decrease, however increasing these height parameters will generally make fabrication of the DML structure more difficult. Therefore, for DML circuits according to certain embodiments herein the parameters w, h.sub.1 and h.sub.2 are selected to be w=150 m, h.sub.1=65 m and h.sub.2=65 m as the optimized parameters. FIG. 1C shows the simulated loss contributions of the DML fabricated using the foregoing parameter values, wherein the SiO.sub.2 and Si contribute 30% and 67%, respectively. It should be appreciated that the finite resistivity of the HRSi introduces the conductor loss and that the radiation loss can be ignored for the contribution of 3%. The complex magnitude E-field distribution (F.sup.y.sub.11 mode) of the DML in the x-y plane at 850 GHz is shown in FIG. 1D. It can be appreciated from the illustration of FIG. 1D that the EM energy mainly distributes in the SiO.sub.2 layer (layer 112 of FIG. 1A).
(43) FIGS. 2A and 2B illustrate propagation constant data of the DML, wherein FIG. 2A shows normalized phase constant data and FIG. 2B shows attenuation constant data. In particular, FIG. 2A shows the normalized phase constant (/k0) for the first two E.sup.x.sub.mn modes (E.sup.x.sub.11 and E.sup.x.sub.21) and two E.sup.x.sub.mn modes (E.sup.y.sub.11 and E.sup.y.sub.21) of the DML with dimensions w=150 m, h.sub.1=65 m, h.sub.2=65 m and t=2 m. It should be appreciated that, because y-direction polarization is used to excite the DML, the E.sup.x.sub.mn modes are not propagated in the DML and with an even symmetry excitation source, the odd symmetry higher-order E.sup.y.sub.21 mode is difficult to excite. FIG. 2B shows the attenuation constant () for the E.sup.y.sub.11 and E.sup.y.sub.21 modes. It can be seen in the graph of FIG. 2B that the of the E.sup.y.sub.21 mode, which is larger than that of the E.sup.y.sub.11 mode, decreases as the frequency increases. In the range of 925-950 GHz, the values of the E.sup.y.sub.11 and E.sup.y.sub.21 modes are comparable, and the high-order E.sup.y.sub.21 mode may appear. Therefore, the operational frequency bandwidth of DML circuits according to certain embodiments herein is 750-925 GHz (e.g., the DML of embodiments is not designed for single-mode operation over 750-950 GHz).
(44) Embodiments of the present invention utilize DML structures, such as the foregoing DML structures optimized for 750-925 GHz operational frequency bandwidth, in implementing various circuits. For example, DML structures configured according to the concepts herein may be utilized in the design of a plurality of passive components, such as crossovers, couplers, etc. It should be appreciated, however, that various circuit implementations using DML circuits of embodiments of the present invention may comprise a plurality of DML structures in proximity, potentially resulting in coupling therebetween, FIG. 3A illustrates a scenario in which two DML structures (DML structures 301 and 302) are disposed with a distance of d (not to scale) between. FIG. 3B provides data useful in comparing such adjacent DML structures (e.g., DML structures 301 and 302 of FIG. 3A) with a single DML structure (e.g., DML structure 101 of FIG. 1A). In particular, FIG. 3B shows the normalized dispersions of the E.sup.y.sub.11 mode of a single DML structure and the even and odd modes of two adjacent DML structures at distances from 40 m to 80 m for DML structures configured with dimensions w=150 m, h.sub.1=65 m and h.sub.2=65 m and t=2 m. It can be appreciated from the data of FIG. 3B that as d increases, the normalized dispersions of the three modes become closer, and when d80 m, they become the same line and the differences are negligible.
(45) A crossover circuit (top view) implemented using DML structures of embodiments of the invention is shown in FIG. 4A. DML crossover circuit 400 of FIG. 4A comprises two mutually perpendicular DML structures (DML structures 401 and 402), such as may each comprise DMLs with dimensions w=150 m, h.sub.1=65 m, h.sub.2=65 m and t=2 m as described above, in the same plane. Taking advantage of the E.sup.y.sub.11 mode propagated in the DML, EM energy excited in port 1 of DML structure 401 cannot easily be transmitted to port 3 or port 4 of DML structure 402. Similarly, EM energy excited in port 3 of DML structure 402 cannot easily be transmitted to port 1 or port 2 of DML structure 401. Accordingly, the exemplary circuit configuration is well suited for providing a crossover circuit implementation having good isolation (e.g., on the order of 25.455.54 dB) between the crossing signal paths.
(46) FIGS. 4B and 4C show the signal energy distribution of DML crossover circuit 400, wherein FIG. 4B shows the H-field distribution and FIG. 4C shows the EM vector distribution of the DML based crossover circuit illustrated in FIG. 4A. In particular, FIG. 4B shows the H-field distribution in the SiO.sub.2 layer of DML crossover circuit 400 resulting from two signals with the same phase and magnitude excited at port 1 of DML structure 401 and port 3 of DML structure 402. FIG. 4C shows the EM vector distribution of DML crossover circuit 400 when excited in port 1 of DML structure 401. As can be appreciated from the illustration of FIG. 4C, the DML has an E.sub.z component when excited in port 1 of DML structure 401 which is difficult to excite the E.sup.y.sub.11 mode in port 3 or port 4 of DML structure 402 for the format matching. FIG. 4D shows the EM vector distribution of a rectangular metallic waveguide-based crossover structure for comparison. As can be appreciated from FIG. 4D, different from the EM vector distribution of the DML-based crossover of FIG. 4C, the E.sub.z component does not exist, which is easy to excite the TE.sub.10 mode in port 3 and port 4 of DML structure 402, as shown in FIG. 4D.
(47) Simulated results of crossover operation of DML crossover circuit 400 are shown in FIG. 4E. In particular, the simulated S-parameters of the crossover provided by DML crossover circuit 400 (w=150 m and l.sub.1=425 m) are shown in FIG. 4E. As can be appreciated from FIG. 4E, the average insertion loss between the input port and the through port is 0.95 dB and, except for some special frequency points, the return loss and isolation are both larger than 20 dB.
(48) A coupler circuit (top view) implemented using DML structures of embodiments of the invention is shown in FIG. 5A. DML coupler circuit 500 of FIG. 5A comprises two DML structures (DML structures 501 and 502), such as may each comprise DMLs with dimensions w=150 m, h.sub.1=65 m, h.sub.2=65 m and t=2 m as described above, with a 45 intersection in the same plane. The relatively simple structure of DML coupler circuit 500 realizes a weak coupling between DML structure 501 and DML structure 502. In operation, for an E.sup.y.sub.11 mode excited at port 1 of DML structure 501, the main part of the EM energy is transmitted to port 2 of DML structure 501, although a weak coupling can be extracted from port 3 of DML structure 502. FIG. 5B shows the H-field distribution in the SiO.sub.2 layer of DML coupler circuit 500 resulting from the E.sup.y.sub.11 mode excited at port 1 of DML structure 501.
(49) Simulated results of coupling operation of DML coupler 500 are shown in FIG. 5C. In particular, the simulated S-parameter and phase difference between the through port and the coupler port provided by DML coupler circuit 500 (w=150 m and l.sub.2=1167 m) are shown in FIG. 5C. As can be appreciated from FIG. 5C, the insertion loss between the input port and the through port is smaller than 1.42 dB, the coupling factor is approximately 14.40 dB, the return loss of port 1 of DML structure 501 is larger than 22.88 dB, the isolation between port 1 of DML structure 401 and port 4 of DML structure 502 is larger than 24.79 dB, and the phase difference of DML coupler 500 is 9012.
(50) It should be appreciated that measurement of signals excited in DML circuits of embodiments herein (e.g., optimized for 750-925 GHz operational frequency bandwidth) presents a challenge, and thus measurement of the performance of such DML circuits (e.g., to collect data such as shown in FIGS. 1B, 1C, 2A, 2B, 3B, 4E, and 5C above) may be difficult without suitable measurement technology. For example, the THz frequency band represents a region in the electromagnetic spectrum where the frequency of electromagnetic radiation becomes too high to be measured digitally via electronic counters, and thus measurements may be made by proxy using the properties of wavelength and energy. Further, it is extremely difficult to insert DML circuits operable in 750-925 (Hz frequencies into the interface of a waveguide used in testing such DML circuits. For example, the test waveguide may comprise a very small rectangular waveguide, such as a WR01 waveguide configuration having inside dimensions of 254 m127 m. Accordingly, embodiments of the invention provide a non-contact measurement technology used to test DML circuits fabricated in accordance with the concepts herein.
(51) FIG. 6 shows an exemplary non-contact measurement system configured for use in testing DML circuits of embodiments of the present invention. In non-contact measurement system 600 of FIG. 6 DML structures 601 and 602 (e.g., comprising straight DMLs with length l.sub.DML in the illustrated embodiment) are under test. Non-contact measurement system 600 of the illustrated embodiment includes measurement interfaces 610 and 620 configured to place DML structures 601 and 602 under test in communication with signal analyzer 640, such as via appropriate waveguides, frequency extenders, cables, etc. To facilitate non-contact measurement according to the illustrated embodiment of FIG. 6, measurement interfaces 610 and 620 provide two transitions comprising a plurality of horn antennas having a space (e.g., 0.4 mm) between. In particular, measurement interface 610 comprises horn antennas 611 and 612 (e.g., a H-plane dielectric horn antenna and a WR01 diagonal horn antenna, respectively) and measurement interface 620 comprises horn antennas 621 and 622 (e.g., a H-plane dielectric horn antenna and a WR01 diagonal horn antenna configuration, respectively). Bend 630 (e.g., a 60 bend based on the DML) of non-contact measurement system 600 of embodiments is provided for avoiding direct transmission between the horn antennas 612 and 622.
(52) An implementation of horn antennas 611 and 621 configured as H-plane dielectric horn antennas based on DML are shown in FIG. 7A. An embodiment of horn antennas 611 and 621 implemented as shown in FIG. 7A may, for example, be configured with dimensions w=150 m, w.sub.2=300 m, w.sub.3=819 m, l.sub.3=850 m, and l.sub.4=1846 m for use with DMLs under test configured in accordance with the concepts herein (e.g., optimized for 750-925 GHz operational frequency bandwidth, such as with dimensions w=150 m, h.sub.1=65 m, h.sub.2=65 m and t=2 m). It should be appreciated that the return loss of the exemplary H-plane dielectric horn antenna configuration of FIG. 7A is sensitive to the length (g) of the dielectric extension area. Accordingly, embodiments of horn antennas implemented as shown in FIG. 7A configure the length of the dielectric extension area (e.g., select g) to match the dielectric horn antenna and the free space. Data showing the relationship between g and S.sub.11 is shown in FIG. 7B. In particular, FIG. 7B shows the simulated S.sub.11 of the antenna configuration of FIG. 7A at various g (swept from 0 to 50 m). As can be appreciated from FIG. 7B, when g equals 40 m the return loss is larger than 12.64 dB. Considering a 5 m undercut width caused by DRIE, embodiments set g as 45.6 m in the mask design used to fabricate the H-plane dielectric horn antenna, wherein the added 5.6 m is a margin for the fabrication.
(53) An implementation of bend 630 configured as a 60 DML bend is shown in FIG. 8A. In particular, FIG. 8A shows the 3D structure of a 60 DML bend and the performance of the 60 DML bend at 850 GHz for different turning radiuses of R. It can be appreciated from FIG. 8A that, if the radius R of the bend is too small (e.g., R=0.5 mm), the radiation of the bend will be very large and the bend does not function satisfactory for use in non-contact measurement system 600 of embodiments. However, if the radius R of the bend is too large (e.g., R=4 mm), the added arc length increases the insertion loss of the bend. Accordingly, a reasonable range for the radius R of the bend is 1.5-3.5 mm. Embodiments of non-contact measurement system 600 utilize a sufficiently large radius R of bend 630 (e.g., R=3.1 mm) facilitate easy handling, transfer, and testing. FIG. 8B shows the simulated S-parameter of the 60 DML bend configuration of FIG. 8A (R=3.1 mm). As shown in FIG. 8B, the return loss of the bend is larger than 15 dB and the insertion loss of the bend decreases as the frequency increases because R of the bend is not optimally large for the low-frequency band 750-780 GHz).
(54) Various DML circuits and their components may be synthesized for measurement and analysis using non-contact measurement systems in accordance with the concepts herein. For example, an embodiment of the test configuration illustrated in FIG. 6 may be fabricated by integrating the H-plane dielectric horn antennas (e.g., horn antennas 611 and 621), the DML circuit transmission line components (e.g., DML structures 601 and 602), and the 60 DML bend (e.g., bend 630), wherein the H-plane dielectric horn antennas may be placed in proximity to respective WR01 diagonal horn antennas (e.g., horn antennas 612 and 622) of the non-contact measurement system (e.g., non-contact measurement system 600) for operation of the measurement system. FIG. 9A shows an integrated implementation of a small DML sample (e.g., length l.sub.DML of each arm of the small samples is 2.639 mm) corresponding to the exemplary DML structure under test of FIG. 6 and FIG. 9B shows an integrated implementation of a large DML sample (e.g., length l.sub.DML of each arm of the large DML samples is 33.483 mm) corresponding to the exemplary DML structure under test of FIG. 6. FIG. 9C shows a reference DML sample having a straight DML (2.5 mm) inserted into the middle of the 60 DML bend of the small DML sample of FIG. 9A. FIG. 9D shows an integrated implementation of a DML crossover circuit, such as that of FIG. 4A, comprising two mutually perpendicular DML samples, wherein the H-plane dielectric horn antennas thereof may be placed in proximity to respective diagonal horn antennas of the non-contact measurement system for operation of the measurement system. Similarly, FIG. 9E shows an integrated implementation of a DML coupler circuit, such as that of FIG. 5A, comprising two DML samples with a 45 angle, wherein the H-plane dielectric horn antennas thereof may be placed in proximity to respective diagonal horn antennas of the non-contact measurement system for operation of the measurement system.
(55) Processes used to fabricate DML circuits of embodiments of the invention, such as the DML crossover circuit of FIG. 4A, the DML coupler circuit of FIG. 5A, and the DML sample circuits of FIGS. 9A-9E, may utilize photo lithographic and chemical processing steps in which the height of the dielectric microstrip lines can be accurately controlled according to embodiments. In particular, the SiO.sub.2 layer can stop the DRIE process, used in fabricating a dielectric ribbon of the DML circuits, due to the etch selectivity between Si and SiO.sub.2, in operation of the fabrication process implemented according to embodiments.
(56) A 100-mm-diameter double-side polished SOI wafer may, for example, be used as a substrate for fabrication of embodiments of a DML circuit. FIG. 10 shows cross-section view of DML structure 1001 (not to scale) fabricated using such a substrate in a fabrication process of embodiments herein. DML structure 1001 fabricated according to the concepts herein comprises layers 111 and 113, wherein layer 113 comprises a handle layer (e.g., HRSi having thickness=350 m), layer 111 comprises a device layer (e.g., HRSi having thickness=65 m), and layer 112 comprises an insulation layer (e.g., SiO.sub.2 having thickness=2 m). In accordance with embodiments of the invention, the device and handle layers (layers 111 and 113) comprise Si layers having a <1, 0, 0> crystal orientation and a high resistivity (p800 .Math.cm).
(57) It should be appreciated that the exemplary DML structure illustrated in FIG. 10 comprises membrane area 1011 forming the bottom layer of the DML structure and connecting handling structures 1012 and 1013. In accordance with embodiments of the invention, handling structures 1012 and 1013 are relatively thick (e.g., 285 m) and are configured to enhance the mechanical strength of the DML circuit.
(58) A plurality of photolithography masks may be utilized in a process to fabricate DML structures such as that of FIG. 10. The masks utilized in a fabrication process of embodiments may, for example, include masks for both frontside etching (e.g., to fabricate DML structures) and backside etching (e.g., to fabricate handling structures) of a SOI wafer.
(59) Three masks as may be utilized in a fabrication process of embodiments herein are shown in FIGS. 11A-11C. The exemplary masks of FIGS. 11A-11C include mask 1101 (FIG. 11A) and mask 1103 (FIG. 11B) configured for frontside etching and mask 1102 (FIG. 11B) configured for backside etching. The exemplary masks of FIGS. 11A-11C provide for fabrication of (include) four small DML samples (e.g., corresponding to the example of FIG. 9A), one large DML sample (e.g., corresponding to the example of FIG. 9B), one reference sample (e.g., corresponding to the example of FIG. 9C), one crossover circuit (e.g., corresponding to the example of FIG. 9D), and two coupler circuits (e.g., corresponding to the example of FIG. 9E) using the masks.
(60) Embodiments of masks utilized in fabrication of DML circuits herein are preferably configured to make the SOI wafer more flat and/or stable when etched. For example, the exemplary mask of FIG. 11A includes pillars 1111-1113 disposed at positions configured to make the wafer more flat and stable when the SOI wafer is etched from the backside. Moreover, the exemplary masks of FIGS. 11A-11C each include a beam (e.g., a Y-shaped beam configuration) disposed and shaped to provide mechanical support to prevent the membrane from cracking during the last backside etching step. The use of such pillars and beams of embodiments, although not forming part of the DML circuits being fabricated, improve the yield of the DML samples.
(61) FIGS. 12A and 12B illustrate a fabrication process to provide DML circuits according to embodiments herein. In particular, FIG. 12A shows flow 1200 comprising process steps for fabricating DML circuits according to embodiments. Correspondingly, FIG. 12B shows cross-sections of a portion of a SOI wafer at each process step of flow 1200. As will be appreciated from the discussion that follows, the exemplary fabrication process of FIGS. 12A and 12B facilitates fabrication of handling structure, such as handling; structures 1012 and 1013 of FIG. 10, in association with the fabricated DML circuits.
(62) In operation according to the embodiment of flow 1200 illustrated in FIG. 12A, the SOI wafer from which the DML circuits are to be fabricated is cleaned at block 1201. For example, the SOI wafer may be cleaned with H.sub.2SO.sub.4: H.sub.2O.sub.2=10:1 and HF:H.sub.2O=1:50 to provide clean SOI wafer 1211 of FIG. 12B.
(63) At block 1202 of the illustrated embodiment, a mask is applied to the top (frontside) of the SOI wafer to define a layer of DML structures. For example, photoresist (PR) may be spin-coated (e.g., AZ4620 with a thickness of 5.7 m) on the top surface of the SOI wafer. A first mask (e.g., mask 1101 of FIG. 11A) may be applied and the open areas of the PR coating photo-exposed (e.g., using UV radiation). The PR may then be developed to define the first DML structure (e.g., DML transmission lines) layer to provide PR mask patterned SOI wafer 1212 of FIG. 12B.
(64) The developed PR is used at block 1203 of the illustrated embodiment to etch the frontside of the SOI wafer. For example, the top device layer may be etched by DRIE in Si (e.g., to a depth of 65 m) to form the strip line structure. In operation according to embodiments of flow 1200, the SiO.sub.2 acts as an etch stop. The remaining PR may be removed, such as by using an oxygen plasma, once the etching is complete to provide PR removed and etched SOI wafer 1213 of FIG. 12B.
(65) At block 1204 of the embodiment illustrated in FIG. 12A a SiO.sub.2 layer is formed on the SOI wafer (e.g., formed on the liontside, backside, and side walls of the etched wafer from block 1203) to protect the etched structure during further processing. For example, low-pressure chemical vapor deposition (LPCVD) may be used to form a SiO.sub.2 layer (e.g., SiO.sub.2 with a thickness of 5.8 m) on all sides of the SOI wafer to provide SiO.sub.2 encapsulated SOI wafer 1214 of FIG. 12B.
(66) A mask is applied to the bottom (backside) of the SOI wafer to define backside support structure at block 1205 of flow 1200 illustrated in FIG. 12A. For example, PR may be spin-coated (e.g., AZ4620 with a thickness of 3 m) on the bottom surface of the SOI wafer. A second mask (e.g., mask 1102 of FIG. 11B) may be applied and the open areas of the PR coating photo-exposed (e.g., using UV radiation). The PR may then be developed to define the support structure (e.g., handling structure) layer to provide PR mask patterned SOI wafer 1215 of FIG. 12B.
(67) At block 1206 of the illustrated embodiment, the backside support layer of the SOI wafer is etched. For example, the SiO.sub.2 on the backside of the SOI wafer may be etched by reactive ion etching (RIE). The remaining PR may be removed, such as by using an oxygen plasma, once the etching is complete to provide PR removed and etched SOI wafer 1216 of FIG. 12B.
(68) A mask, registered with the defined first layer of DML structures, is applied to the top (frontside) of the SOI wafer at block 1207 of the illustrated embodiment of flow 1200. For example, the frontside of the SOI wafer may be spray-coated with PR (e.g., AZ9260: MEK: PGMEA=1:8:1 by weight, with a thickness of 20 m). A third mask (e.g., mask 1103 of FIG. 11C) may be aligned using alignment marks on the backside and applied to the frontside of the SOI wafer. The open areas of the PR may be photo-exposed (e.g., using UV radiation) and the PR developed to provide PR mask patterned SOI wafer 1217 of FIG. 12B.
(69) At block 1208 of the embodiment illustrated in FIG. 12A, the DML structure layer is etched. For example, the SiO2 on the frontside of the SOI wafer may be etched by RIE. The remaining PR may be stripped, such as by using an oxygen plasma, once the etching is complete to provide PR removed and etched SIM wafer 1218 of FIG. 12B.
(70) The handle layer is etched to complete the fabrication of the fabricated DML circuits and to release the fabricated DML circuits from the SOI wafer at blocks 1209 and 1210 of the illustrated embodiment. For example, with the SOI wafer mounted on a support wafer, the handle layer may be etched by DRIE in the Si (e.g., to a depth of 65 m) from the frontside (block 1209, providing frontside handle layer etched SOI wafer 1219 of FIG. 12B). The etch depth may, for example, be monitored using a Tencor P-10 surface profilometer. With the SOI wafer mounted on a carrier wafer, the handle layer may be etched using DRIE in the Si from the backside to create the bottom layer of the DML (block 1210). After etching through the 285-m-thick handle wafer, the DML circuits are released from the carrier wafer providing released DML circuit 1220 of FIG. 12B. It should be appreciated that, because the sample is very thin and the remaining SiO.sub.2 around the strip of the DML will not affect the performance of the DML, the remaining SiO.sub.2 may not be removed according to embodiments.
(71) FIG. 13A shows a top view of small and large DML samples (e.g., corresponding to the configurations of FIGS. 9A and 9B) fabricated using a process in accordance with flow 1200 of FIG. 12A. FIG. 13B shows a scanning electron micrograph (SEM) displaying the cross-section of the fabricated DML samples of FIG. 13A, From the SEM of FIG. 13E it can be appreciated that the remaining SiO.sub.2 thickness of the exemplary sample is 4.7 m, the strip height of the exemplary sample fabricated device is 64.9 m, and the thickness of the exemplary sample fabricated device bottom layer is 59.8 m.
(72) FIG. 13C shows a top view of a H-plane dielectric horn antenna based on the DML (e.g., corresponding to the configuration of FIG. 7) fabricated using a process in accordance with flow 1200 of FIG. 12A. It can be appreciated from the illustration of FIG. 13C that the edge extension area (g) of the middle and bottom layers of the exemplary sample fabricated horn antenna is 43 m and the undercut width caused by the DRIE is 2.6 m.
(73) FIG. 14 shows the complex magnitude E-field distribution (E.sup.y.sub.11 mode) in the cross-sectional view of the fabricated DML circuits of FIG. 13B in the x-y plane at 850 GHz. In comparing the complex magnitude E-field distributions of FIG. 1D (for the structure as shown in FIG. 1A) and FIG. 14 (for the fabricated structure as shown by 1220 of FIG. 12B) it can be appreciated that the complex magnitude E-field distribution for these structures are very similar. Therefore, the thickness variation in the handle layer of embodiments of the invention is expected to have little effect on the DML performance.
(74) Measured results for the attenuation constant and normalized dispersion of DML circuits fabricated according to embodiments of flow 1200 of FIG. 12A may be obtained using a non-contact measurement system configuration consistent with that of FIG. 6 described above. The measured and simulated results of the small and large DML samples (e.g., the small DML sample configuration of FIG. 9A and the large DML sample of FIG. 9B) are shown in FIG. 15A, The isolation between the diagonal horns of the measurement system is also measured, as shown in FIG. 15A. It can be appreciated from the measured results in FIG. 15A that, except for a very small part at low end of the band (e.g., 750-758 GHz), the isolation of the entire operation frequency band is much larger than the insertion loss of the DML samples.
(75) The attenuation constant and the phase constant of the DML circuits can be calculated from the measured results using the following equations:
(76)
(77) The calculated attenuation and phase constants of the DML samples are shown in FIGS. 15B and 15C, respectively. It should be appreciated that the post-simulated and measured results match well over 750-925 GHz. As discussed above, a high-order E.sup.y.sub.21 mode may appear in 925-950 GHz, in which case the post-simulated and measured attenuation and phase constant do not match.
(78) The insertion loss per wavelength (IL/) can be calculated from the measured results using the following equation:
(79)
(80) The calculated insertion loss per wavelength of the DML samples is shown in FIG. 15D. As can be appreciated from the data of FIG. 15D, the measured loss per wavelength of the DML ranges from 0.0082 to 0.042 dB/ over 750-925 GHz, which is much smaller than that of the standard WR01 waveguide (0.079 dB/, average value) from the VDI Company over 750-925 GHz.
(81) Measured results for the DML crossover and DML coupler circuits (e.g., the DML crossover circuit of FIG. 9C and the DML coupler circuit of FIG. 9D) may likewise be obtained using a non-contact measurement system configuration consistent with that of FIG. 6 described above. It should be appreciated that, because the return loss of the H-plane DML horn antenna utilized according to embodiments is larger than 12.64 dB, the antenna matches well with the air. When measurement of the multi-port components is conducted using a non-contact measurement system of embodiments herein, the ports that do not point to the diagonal horns match well with the air, Thus n.on-contact measurement systems of embodiments do not need any additional matching loads.
(82) The measured results of the DIVIL crossover and DML coupler fabricated in accordance with the process of flow 1200 of embodiments are shown in FIGS. 16A and 16B, respectively. As can be appreciated from the results shown in FIGS. 16A and 16B, the S.sub.21 of both the DML crossover circuit and the DML coupler circuit are very similar to that of the reference sample, which supports a conclusion that the insertion loss between the input port and the through port of the crossover and coupler are very small.
(83) FIGS. 16C and 16D show the normalized results of the foregoing DML crossover and the DML coupler circuits, respectively. The normalized results of the crossover and coupler can be derived by the following equation:
Normalized S.sub.11 (dB)=S.sub.11 (dB)S.sub.21,k(dB)
where the S.sub.11 is the measured result of the crossover or coupler (i=2, 3, 4), and S.sub.21,R is the S.sub.21 of the reference sample. As shown in FIGS. 16C and 16D, the normalized results and the simulated results essentially match. The normalized results show that the exemplary fabricated DML crossover and DML coupler circuits can perform satisfactorily at least over the frequency range 758-925 GHz.
(84) Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
(85) Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification.
