MEMRISTOR WITH TWO-DIMENSIONAL (2D) MATERIAL HETEROJUNCTION AND PREPARATION METHOD THEREOF

Abstract

A memristor with a two-dimensional (2D) material heterojunction and a preparation method thereof is provided. The memristor includes a substrate, a bottom electrode layer, a 2D material heterojunction layer and a top electrode layer from bottom to top. The 2D material heterojunction layer serves as an intermediate dielectric layer, and has a two-layer laminate structure composed of two different transitional metal dichalcogenides (TMDCs), with one layer in the laminate structure corresponding to one of the TMDCs. The present invention constructs a novel memristor totally based on 2D materials by improving the materials used for key functional layers in the device and the design for the overall structure of the device. Compared with the prior art, the present invention completely different from the conventional metal/insulator/metal (MIM) structure, and has advantages, such as lower operating voltage, excellent retention and switching stability.

Claims

1. A memristor with a two-dimensional (2D) material heterojunction, comprising: a substrate; a bottom electrode layer; a 2D material heterojunction layer; and a top electrode layer from bottom to top; wherein the 2D material heterojunction layer serves as an intermediate dielectric layer with a thickness of 1 nm to 50 nm, and has a two-layer laminate structure composed of two different transitional metal dichalcogenides (TMDCs), with one layer in the laminate structure corresponding to one of the TMDCs.

2. The memristor with a 2D material heterojunction according to claim 1, wherein: the 2D material heterojunction layer is formed by directly sulfurating a metal laminate structure in high purity sulfur vapor; the metal laminate structure comprises two layers of elemental metal structures; and the two layers comprise metal elements different from each other.

3. The memristor with a 2D material heterojunction according to claim 2, wherein: the direct sulfuration is conducted at 500 C. to 1,000 C. for 1 min to 30 min; and the 2D material heterojunction layer has a thickness of about 10 nm, and the direct sulfuration is conducted at about 550 C. for 10 min.

4. The memristor with a 2D material heterojunction according to claim 1, wherein: the two different TMDCs are specifically two different transition metal disulfides; and the transition metal sulfides are any two of zinc sulfide, silver sulfide, titanium sulfide, cadmium sulfide, cuprous sulfide, germanium sulfide, tungsten sulfide and molybdenum sulfide.

5. The memristor with a 2D material heterojunction according to claim 2, wherein: the substrate is a rigid substrate or a flexible substrate and can withstand a high temperature of at least 500 C., and will not react with the sulfur vapor; and the rigid substrate is a SiO.sub.2/Si substrate with an oxide layer formed from oxidation of the monocrystalline silicon surface, or a sapphire substrate.

6. The memristor with a 2D material heterojunction according to claim 1, wherein: the top electrode layer is Au, Ti, Pt, Al, W, Ag, Cu, ITO, TiN or graphene, with a thickness of about 80 nm to 200 nm; the top electrode layer is Al, with a thickness of about 100 nm; the material used for the bottom electrode layer is any one of metal, conductive oxide, conductive nitride and conductive carbon material, with a thickness of about 1 nm to 500 nm; and preferably, the material used for the bottom electrode layer is a conductive oxide, preferably ITO with a thickness of 10 nm to 1,000 nm, and more preferably ITO with a thickness of 200 nm.

7. A method for preparing a memristor with a 2D material heterojunction, the method comprising: (1) preparing a substrate provided with a bottom electrode layer on the surface thereof; (2) depositing a metal laminate structure on the bottom electrode layer by a thin film deposition process with a shadow mask, wherein, the thin film deposition process is thermal evaporation, magnetron sputtering, electron beam evaporation, sol-gel, chemical vapor deposition or coating; (3) treating, using a direct vacuum sulfuration method, the substrate deposited with the metal laminate structure, so that the metal laminate structure is sulfurated to form a TMDCs heterojunction structure; and (4) spin-coating a photoresist on the heterojunction structure, and defining a top electrode pattern on the photoresist by lithography; then depositing electrode materials for forming a top electrode layer, and then stripping the photoresist to form the top electrode layer, thereby achieving the memristor with a 2D material heterojunction.

8. The method according to claim 7, wherein: the 2D material heterojunction layer is formed by directly sulfurating a metal laminate structure in high purity sulfur vapor; the metal laminate structure comprises two layers of elemental metal structures; and the two layers comprise metal elements different from each other.

9. The method according to claim 8, wherein: the direct sulfuration is conducted at about 500 C. to 1,000 C. for 1 min to 30 min; and the 2D material heterojunction layer has a thickness of about 10 nm, and the direct sulfuration is conducted at about 550 C. for 10 min.

10. The method according to claim 7, wherein: the two different TMDCs are specifically two different transition metal disulfides; and the transition metal sulfides are any two of zinc sulfide, silver sulfide, titanium sulfide, cadmium sulfide, cuprous sulfide, germanium sulfide, tungsten sulfide and molybdenum sulfide.

11. The method according to claim 8, wherein: the substrate is a rigid substrate or a flexible substrate and can withstand a high temperature of at least 500 C., and will not react with the sulfur vapor; and the rigid substrate is a SiO.sub.2/Si substrate with an oxide layer formed from oxidation of the monocrystalline silicon surface, or a sapphire substrate.

12. The method according to claim 7, wherein: the top electrode layer is Au, Ti, Pt, Al, W, Ag, Cu, ITO, TiN or graphene, with a thickness of about 80 nm to 200 nm; the top electrode layer is Al, with a thickness of about 100 nm; the material used for the bottom electrode layer is any one of metal, conductive oxide, conductive nitride and conductive carbon material, with a thickness of about 1 nm to 500 nm; and preferably, the material used for the bottom electrode layer is a conductive oxide, preferably ITO with a thickness of 10 nm to 1,000 nm, and more preferably ITO with a thickness of 200 nm.

13. The method according to claim 7, wherein: in step (2), the metal laminate structure is specifically deposited on the bottom electrode layer by magnetron sputtering or electron beam evaporation; in step (2), the metal laminate structure is a two-layer metal structure composed of a Mo atom layer and a W atom layer; and correspondingly, the TMDCs heterojunction structure formed in step (3) is specifically a MoS.sub.2/WS.sub.2 heterojunction structure composed of a MoS.sub.2 layer and a WS.sub.2 layer.

14. The method according to claim 8, wherein: in step (2), the metal laminate structure is specifically deposited on the bottom electrode layer by magnetron sputtering or electron beam evaporation; in step (2), the metal laminate structure is a two-layer metal structure composed of a Mo atom layer and a W atom layer; and correspondingly, the TMDCs heterojunction structure formed in step (3) is specifically a MoS.sub.2/WS.sub.2 heterojunction structure composed of a MoS.sub.2 layer and a WS.sub.2 layer.

15. The method according to claim 9, wherein: in step (2), the metal laminate structure is specifically deposited on the bottom electrode layer by magnetron sputtering or electron beam evaporation; in step (2), the metal laminate structure is a two-layer metal structure composed of a Mo atom layer and a W atom layer; and correspondingly, the TMDCs heterojunction structure formed in step (3) is specifically a MoS.sub.2/WS.sub.2 heterojunction structure composed of a MoS.sub.2 layer and a WS.sub.2 layer.

16. The method according to claim 10, wherein: in step (2), the metal laminate structure is specifically deposited on the bottom electrode layer by magnetron sputtering or electron beam evaporation; in step (2), the metal laminate structure is a two-layer metal structure composed of a Mo atom layer and a W atom layer; and correspondingly, the TMDCs heterojunction structure formed in step (3) is specifically a MoS.sub.2/WS.sub.2 heterojunction structure composed of a MoS.sub.2 layer and a WS.sub.2 layer.

17. The method according to claim 11, wherein: in step (2), the metal laminate structure is specifically deposited on the bottom electrode layer by magnetron sputtering or electron beam evaporation; in step (2), the metal laminate structure is a two-layer metal structure composed of a Mo atom layer and a W atom layer; and correspondingly, the TMDCs heterojunction structure formed in step (3) is specifically a MoS.sub.2/WS.sub.2 heterojunction structure composed of a MoS.sub.2 layer and a WS.sub.2 layer.

18. The method according to claim 12, wherein: in step (2), the metal laminate structure is specifically deposited on the bottom electrode layer by magnetron sputtering or electron beam evaporation; in step (2), the metal laminate structure is a two-layer metal structure composed of a Mo atom layer and a W atom layer; and correspondingly, the TMDCs heterojunction structure formed in step (3) is specifically a MoS.sub.2/WS.sub.2 heterojunction structure composed of a MoS.sub.2 layer and a WS.sub.2 layer.

19. The method according to claim 7, wherein: in step (1), the bottom electrode layer is specifically provided on the substrate by a thin film deposition process; preferably, in step (1), specifically, an ITO film layer is deposited as the bottom electrode layer on the substrate by magnetron sputtering under an oxygen atmosphere; and more preferably, the ITO film layer has a thickness of 10 nm to 1,000 nm, and more preferably of 200 nm.

20. The method according to claim 7, wherein: in step (4), the depositing electrode materials for forming the top electrode layer is specifically conducted by depositing electrode metal materials with magnetron sputtering or electron beam evaporation to form the top electrode layer.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0026] FIG. 1 is a structural diagram for the memristor unit prepared in the present invention.

[0027] FIG. 2 is a schematic diagram for specific steps of the preparation method in an example of the present invention.

[0028] FIG. 3 is a current-voltage (I-V) characteristic curve for the memristor unit prepared in Example 1 of the present invention.

[0029] FIG. 4 shows the switching performance (>100 times) of the memristor unit prepared in Example 1 of the present invention.

[0030] FIGS. 5A and 5B show the switching stability of the memristor unit prepared in Example 1 of the present invention, where FIG. 5A shows the stability of HRS and LRS during the switching, and FIG. 5B shows the stability of voltage during the set process and reset process of the switching.

[0031] FIGS. 6A and 6B are comparisons of the working process of the memristor unit prepared in Example 1 of the present invention with the process of information transmission by synapses, where, FIG. 6A is a schematic diagram for the working process of the memristor unit prepared in Example 1 of the present invention, and FIG. 6B is a schematic diagram for the process of information transmission by synapses.

[0032] FIG. 7 is an I-V characteristic curve for the memristor unit prepared in Example 2 of the present invention.

[0033] FIGS. 8A and 8B are I-V characteristic curves for the memristor unit prepared in Example 3 of the present invention, where, FIG. 8A shows the switching performance (>100 times), and FIG. 8B shows the reset process and the set process for the memristor.

[0034] FIG. 9 is an I-V characteristic curve for the memristor unit prepared in Example 4 of the present invention.

[0035] Among the numerical symbols 1 to 6 in the I-V characteristic curve, 1 to 3 represent the set process, and 4 to 6 represent the reset process.

DETAILED DESCRIPTION

[0036] To make the objectives, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below with reference to the accompanying drawings and examples. It should be understood that the specific examples described herein are merely intended to explain the present invention, rather than to limit the present invention. Further, the technical features involved in the various examples of the present invention described below may be combined with each other to the extent that they do not constitute a conflict with each other.

EXAMPLE 1

[0037] The following example adopts different electrode materials and different intermediate dielectric layers (i.e., different 2D material heterojunction layers) to realize the preparation of novel memristors.

[0038] Example 1 is described as follows in conjunction with FIG. 2:

[0039] The memristor with a 2D material heterojunction in Example 1 included a bottom electrode layer and a memristive dielectric layer formed on a substrate in sequence, and a top electrode layer formed on the memristive dielectric layer. The memristive dielectric layer was a 2D material heterojunction. In Example 1, the bottom electrode layer was ITO conductive glass; the intermediate memristive dielectric layer was a WS2/MoS2 heterojunction prepared by solid-phase sulfuration, with a thickness of 5 nm; and the top electrode layer was an aluminum film, with a thickness of 100 nm.

[0040] The memristor with a 2D material heterojunction of this example was prepared as follows:

[0041] 1) ITO conductive glasses, as a substrate and bottom electrode for the device, were ultrasonically cleaned with acetone, ethanol and deionized water in sequence, and then blow-dried;

[0042] 2) an elemental tungsten film was deposited on the bottom electrode film by magnetron sputtering, where the sputtering was conducted with the following parameters: sputtering target: tungsten, sputtering atmosphere: argon, sputtering pressure: 0.6 Pa, substrate temperature: room temperature, sputtering power: 100 W, and sputtering time: 1 min;

[0043] 3) an elemental molybdenum film was deposited on the elemental tungsten film by magnetron sputtering, where the sputtering was conducted with the following parameters: sputtering target: molybdenum, sputtering atmosphere: argon, sputtering pressure: 0.5 Pa, substrate temperature: room temperature, sputtering power: 100 W, and sputtering time: 1 min;

[0044] 4) the tungsten and molybdenum films grown by magnetron sputtering in step 2) and step 3) were simultaneously sulfurated and annealed by rapid thermal annealing (RTA), where, the specific parameters could be as follows: heating rate for RTA: 1 to 20 C./s, annealing atmosphere: argon and sulfur vapor, annealing temperature: 500 C. to 600 C. (preferably 550 C.), holding time: 1 min to 30 min, and cooling method: natural cooling to room temperature by water-cooling; and a WS2/MoS2 heterojunction film with a thickness of 5 nm was prepared;

[0045] 5) a top electrode pattern was formed on the WS2/MoS2 heterojunction film obtained from the annealing in step 4) by UV photolithography, where, a photoresist, which could be AZ5214 photoresist, was applied, then exposed and blow-dried; a top electrode layer of aluminum was deposited by magnetron sputtering, with a thickness of 100 nm; and finally the excessive photoresist was cleaned away to obtain the top electrode layer pattern.

[0046] FIG. 1 shows the structural diagram for the memristor prepared in this example, and as shown, the memristor includes a substrate, a bottom electrode layer, a memristive dielectric layer and a top electrode layer in sequence from bottom to top. The substrate and the bottom electrode layer directly adopt ITO conductive glass; the memristive dielectric layer is a 2D material (WS2/MoS2) heterojunction film, with a thickness of 5 nm; and the top electrode is an aluminum film, with a thickness of 100 nm.

[0047] Further, in this example, a semiconductor parameter analyzer B1500A was used to conduct the electrical testing for the memristor with a WS2/MoS2 heterojunction prepared by the above steps. The I-V characteristic curves are shown in FIG. 3, FIG. 4 and FIGS. 5A and 5B.

[0048] FIG. 3 shows the I-V characteristic curve for the memristor of this example at initial state under the action of a DC sweeping voltage, and the device exhibits a typical bipolar resistive switching feature. During the testing, the ITO bottom electrode was grounded, and a voltage was applied to the Al top electrode. As the forward voltage applied to the Al electrode increased, at about 1.3 V, the current suddenly increased and the device rapidly changed from HRS to LRS, which was a set process; and as the reverse voltage was further applied, the device returned from LRS to HRS at about 1.1 V, achieving the transition between HRS and LRS, which reveals the resistive switching feature of the memristor with a WS2/MoS2 heterojunction.

[0049] FIG. 4 shows the I-V switching performance for the memristor in this example, where the device has 100 cycles.

[0050] FIGS. 5A and 5B show the stability characteristics of HRS and LRS and the transition voltage during the cycle of the memristor in this example. It can be concluded from the figure that the on-off ratio (HRS/LRS) of the memristor in this example is greater than 104, and the transition voltage basically remains unchanged during the reset and the set processes of the device.

[0051] Due to the presence of a TMDCs heterojunction, the memristor in this example has a different resistive mechanism from a conventional MIM-type memristor. FIGS. 6A and 6B show the comparison of the switching mechanism of the memristor with a 2D material heterojunction of the present invention with the process of information transmission by synapses. As the entire intermediate dielectric layer is a heterojunction composed of two TMDCs, the free ions in the layer cannot move across the grain boundary from one material into another material, but the electron movement is suddenly changed due to the change in the ion concentration. This is similar to the information transmission by neurons, and will definitely play an extremely-important role in the research of brain-like computers in the future.

EXAMPLE 2

[0052] In this example, the specific implementation was the same as that for Example 1, except that the intermediate dielectric layer of WS2/MoS2 heterojunction had a thickness of 20 nm, in which tungsten sulfide and molybdenum sulfide both had a thickness of 10 nm.

[0053] Further, in this example, a semiconductor parameter analyzer was used to conduct the electrical testing for the memristor with a WS2/MoS2 heterojunction. FIG. 7 shows the I-V characteristic curve for the memristor of this example at initial state in responsive to a DC sweeping voltage.

EXAMPLE 3

[0054] In this example, the specific implementation was the same as that for Example 1, except that the top electrode layer was Ag with a thickness of 100 nm.

[0055] Further, in this example, a semiconductor parameter analyzer was used to conduct the electrical testing for the memristor with a WS2/MoS2 heterojunction. FIGS. 8A and 8B show I-V characteristic curves for the memristor of this example at initial state in responsive to a DC sweeping voltage.

EXAMPLE 4

[0056] In this example, the specific implementation was the same as that for Example 1, except that the top electrode layer was Au/Ni with a thickness of 80 nm/20 nm, and the bottom electrode layer was graphene.

[0057] Further, in this example, a semiconductor parameter analyzer was used to conduct the electrical testing for the memristor with a WS2/MoS2 heterojunction. FIG. 9 shows the I-V characteristic curve for the memristor of this example at initial state in responsive to a DC sweeping voltage.

[0058] In addition to what is described in the above examples, the bottom electrode layer and the intermediate dielectric layer can be formed on the substrate using a thin film deposition process. The thin film deposition process includes thermal evaporation, magnetron sputtering, electron beam evaporation, sol-gel, chemical vapor deposition or coating. The thin film deposition process can be flexibly adjusted according to the materials used for the bottom electrode layer and the intermediate dielectric layer. In addition, the substrate may be an insulating substrate, a semiconductor substrate or a conductive substrate. The insulating substrate may include, for example, thermal oxide silicon wafer, glass, ceramic or plastic; the semiconductor substrate may include, for example, silicon, oxide semiconductor, nitride semiconductor or other semiconductor materials; and the conductive substrate may include, for example, metal or graphene. The present invention preferably adopts the SiO2/Si material with an oxide layer formed from oxidation of the monocrystalline silicon surface (i.e., thermal oxide silicon wafer) as a substrate, which mainly considers the compatibility with existing CMOS processes and the applications in the field of integrated electronics. The substrate may also be another silicon-based substrate.

[0059] It is easy for those skilled in the art to understand that the above-mentioned contents are merely the preferred examples of the present invention, and are not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should fall within the protection scope of the present invention.