Slew-limited output driver circuit

Abstract

A slew-limited output driver circuit facilitates finding a circuitry that allows a flexible setting of the slew-rate of an integrated circuit, with only a small footprint and latency, and which allows realizing different driver modes without additional components integrated protection against ESD. A short circuit will be solved by a slew-limited output driver circuit comprising a switchable current mirror providing an output current equal to an input current, wherein the current mirror is controlled by an additional switch, which is switched in response to control signals and/or an output current level of the output driver circuit, wherein adjustable operating modes of the slew-limited output driver circuit are realized by the control signals.

Claims

1. Slew-limited output driver circuit comprising two switchable current mirrors providing an output current equal to an input current, wherein the current mirrors are controlled by additional switches, which are switched by a first set of control signals in response to a second set of control signals and to an output voltage level of the output of the output driver circuit, wherein different operating modes as a voltage source mode, a current source mode, or an automatic mode of the slew-limited output driver are realized by the control signals, wherein the second set of control signals are inputted to the output driver circuit at gate nodes of additional pass transistors connected also to the first set of control signals and the output, wherein the first set of control signals are input to the output driver circuit at source or drain nodes of said pass transistors.

2. The slew-limited output driver circuit according to claim 1, wherein when the lead transistor of the first and/or second current mirror is switched as a diode by means of a switch transistor that is controlled either by means of a pass transistor connecting to an output of the slew-limited output driver circuit or by directly controlling a control node of the switch transistor, the output functions as a current driver with high internal resistance.

3. The slew-limited output driver circuit according to claim 2, wherein no transistor gates of the current mirror transistors, the additional switch and the control circuitry thereof are directly connected to the output.

4. The slew-limited output driver circuit according to claim 3, wherein input signals to the current mirrors are connected as additional inputs of the slew-limited output driver circuit, providing a switchable pre-emphasis by optionally pre-charging or, respectively, discharging the control signals controlling the switchable current mirrors.

5. The Slew-limited output driver circuit according to claim 1, wherein when the additional switch at the lead transistor of the first and/or second current mirror is open, controlled to be open either by means of a pass transistor connecting to an output of the slew-limited output driver circuit or by directly controlling a control node of the switch transistor, the output functions as a voltage source with low internal resistance.

6. The slew-limited output driver circuit according to claim 1, wherein the first and second set of control signals control a pull-up driver comprising said current mirror and a said switch as well as a pull-down driver comprising a further current mirror and a further said switch by means of pass transistors and the said current mirror switches.

7. The slew-limited output driver circuit according to claim 6, wherein the control signals are inputted to the output driver circuit separately from each other.

8. The slew-limited output driver circuit according to claim 6, wherein no transistor gates of the current mirror transistors, the additional switch and the control circuitry thereof are directly connected to the output.

9. The slew-limited output driver circuit according to claim 8, wherein input signals to the current mirrors are connected as additional inputs of the slew-limited output driver circuit, providing a switchable pre-emphasis by optionally pre-charging or, respectively, discharging the control signals controlling the switchable current mirrors.

10. The slew-limited output driver circuit according to claim 1, wherein when said control signals p_prectl and p_fbe are high and n_prectl and n_fbe are low the operating mode of the output driver is a voltage source mode, wherein a slew-rate of the slew-limited driver is not limited.

11. The slew-limited output driver circuit according to claim 1, wherein when said control signals p_prectl and n_fbe are low and n_prectl and p_fbe are high the operating mode of the output driver is a current source mode, wherein the slew-rate of the slew-limited driver is limited.

12. The slew-limited output driver circuit according to claim 1, wherein when said control signals p_prectl and n_prectl are in a tri-state Z, p_fbe is low and n_fbe is high the operating mode of the output driver is automatically switched into a voltage source mode or into a current source mode if a change in the output current level is performed.

13. The slew-limited output driver circuit according to claim 1, wherein no transistor gates of the current mirror transistors, the additional switch and the control circuitry thereof are directly connected to the output.

14. The slew-limited output driver circuit according to claim 1, wherein input signals to the current mirrors are connected as additional inputs of the slew-limited output driver circuit, providing a switchable pre-emphasis by optionally pre-charging or, respectively, discharging the control signals controlling the switchable current mirrors.

Description

BRIEF DESCRIPTION OF THE DRAWING FIGURES

(1) The appended drawing shows

(2) FIG. 1 Inventive slew-limited output driver circuit.

DETAILED DESCRIPTION

(3) The FIGURE shows the inventive slew-limited output driver circuit. The inventive circuit uses in its core a current mirror (P1, P2 or N1, N2), by means of an additional switch (P3 or N3) in response to control signals (prectl, fbe) and/or the current level at the output (PAD) is switched. The control signals exist respectively for the pull-up driver (p_prectl, p_fbe) and the pull-down driver (n_prectl, n_fbe). They can be switched separately in a general embodiment.

(4) If the lead transistor (P2 or N2) is switched as a diode, a constant gate voltage at the corresponding output transistor (P1 or N1) and thus a constant output current is generated, whereby a linear increase of the output voltage is achieved at a capacitive load. The output thus functions as a current driver with high internal resistance.

(5) If the switch (P3 or N3) on the lead transistor (P2 or N2) is turned off, hence it is open, the gate-source voltage at the output transistor (P1 or N1) increases so that it opens completely and the output operates as a voltage source with low internal resistance.

(6) By the control signals (prectl, fbe), the operating mode, for example the voltage source mode or the current source mode is set as shown in the following tables:

(7) TABLE-US-00001 p_prectl p_fbe function logic 1 logic 1 voltage source mode (low resistive, (low resistive, slew-rate supply voltage) supply voltage) not limited logic 0 logic 1 current source mode (low resistive, (low resistive, slew-rate ground) supply voltage) limited Tri-state Z (high logic 0 voltage source mode, resistive) (low resistive, current source mode/ ground) slew-rate limitation will be automatically activated, if there is a level change at the output else Not allowed n_prectl n_fbe function logic 0 logic 0 voltage source mode (low resistive, (low resistive, slew-rate ground) ground) not limited logic 1 logic 0 current source mode (low resistive, (low resistive, slew-rate limited supply voltage) ground) Tri-state Z (high logic 1 voltage source mode, resistive) (low resistive, current source mode/ supply voltage) slew-rate limitation will be automatically activated, if there is a level change at the output else Not allowed

(8) In the so-called automatic mode, the turn-off of the conducting transistor (P1 or N1) is controlled by the output voltage via a pass transistor (P4 or N4). If the output level has not yet reached the target voltage, the circuit operates as a current driver with limited output current and high internal resistance, however, if the target voltage level is reached, the circuit is automatically switched to voltage source mode with low internal resistance.

(9) If there is a short circuit at the output and the output level does not change, the driver remains in current source mode and provides only the limited set output current.

(10) Since no transistor gates are connected directly to the output for the realization, there is no danger due to ESD events.

(11) In addition, it is possible to pre-emphasize the output signal (pre-emphasis) by pre-charging or discharging the nodes p_predrv or n_predrv before the switching operation in order to improve the signal properties on lines with low-pass behavior. For this purpose, the current mirror is constructed as a high-swing cascode, which is switched at the cascode voltage. If the gate has been discharged before switching on, the output current starting from 0 will slowly increase to the set current limit (soft start); however, when the gate is charged, the output current rises rapidly to a value greater than the set current limit and then drops to the limit (this is called pre-emphasis).

(12) The essential advantage of the claimed invention is the usage of a switchable current mirror, the control of the current mirror by direct feedback of the output, and the implementation of adjustable operating modes, such as current source mode/voltage source mode/automatically switchable mode.

LIST OF REFERENCE SIGNS

(13) 1 Slew-limited output driver circuit 2 switchable current mirror P1+P2 first current mirror N1+N2 second current mirror P1, N1 output transistor P2, N2 lead transistor P3, N3 additional switch P4 pull-up driver N4 pull-down driver x_prectl, x_fbe control signal, with x=p, n PAD output with output signal