PASSIVATION METHOD FOR A PASSAGE OPENING OF A WAFER

Abstract

A passivation method for a passage opening of a wafer, at least having the steps of: providing a wafer having a top, a bottom and comprising a plurality of solar cell stacks, wherein each solar cell stack has a Ge substrate that forms the bottom of the wafer, a Ge sub-cell, at least two III-V sub-cells, in the named order, and at least one passage opening extending from the top to the bottom of the wafer, with a contiguous side wall and a circumference that is oval in cross section, and applying a dielectric insulating layer by means of chemical vapor deposition to the top of the wafer, the bottom of the wafer and the side wall of the passage opening.

Claims

1. A passivation method comprising: providing a wafer having a top, a bottom and at least two solar cell stacks, each of the at least two solar cell stacks has a Ge substrate that forms the bottom of the wafer, a Ge sub-cell, at least two III-V sub-cells and at least one passage opening extending from the top to the bottom of the wafer with a contiguous side wall and a circumference that is oval in cross section; and applying a dielectric insulating layer via chemical vapor deposition to the top of the wafer, the bottom of the wafer and the side wall of the passage opening.

2. The method according to claim 1, wherein the dielectric insulating layer is applied via a plasma-assisted vapor deposition.

3. The method according to claim 1, wherein the applied dielectric insulating layer on the side wall of the passage opening has a layer thickness of at least 10 nm.

4. The method according to claim 1, wherein the dielectric insulating layer contains SiO.sub.x and/or SiN.sub.x.

5. The method according to claim 1, wherein the dielectric insulating layer is first applied to the top of the wafer, then the wafer is rotated and then the dielectric insulating layer is applied to the bottom.

6. The method according to claim 1, wherein the passage opening of the wafer has a first diameter of at most 1 mm and at least 50 m on an edge bordering the top of the wafer, and has a second diameter of at most 1 mm and of at least 50 m on an edge bordering the bottom of the wafer, and wherein the wafer that is provided has an overall thickness of at most 300 m and of at least 90 m.

7. The method according to claim 1, wherein, after applying the dielectric insulating layer, the dielectric insulating layer is first structured on the top and then on the bottom or first on the bottom and then on the top or the bottom and the top are structured at the same time.

8. The method according to claim 7, wherein the dielectric insulating layer is wet-chemically etched, wherein in each case a first lacquer layer is applied, cured, exposed and developed and/or an organic material that differs from the first lacquer layer is applied in a structured manner by means of a screen printing process or by an inkjet printing process.

9. The method according to claim 1, wherein the insulating layer is formed as a layer system comprising a first layer and at least one second layer, and wherein the first layer is applied prior to the second layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus, are not limitive of the present invention, and wherein:

[0036] FIG. 1 is a view of an exemplary according to the invention of a passivation method for a passage opening of a wafer,

[0037] FIG. 2 is a plan view of a passage opening of a wafer which is passivated according to the passivation method, and

[0038] FIG. 3 shows a wafer.

DETAILED DESCRIPTION

[0039] The illustration in FIG. 1 shows an exemplary embodiment of a passivation method for a passage opening of a wafer.

[0040] A stacked wafer 10 has a top 10.1, a bottom 10.2 and a passage opening 22 that extends from the top 10.1 to the bottom 10.2, with a contiguous side wall 22.1 and a circumference that is oval, for example circular, in cross section.

[0041] The bottom 10.2 is formed by a Ge substrate 14, followed by a Ge sub-cell 16 and two III-V sub-cells.

[0042] At the top 10.1 of the wafer 10, the passage opening 22 has a first diameter B1 and at the bottom 10.2 it has a second diameter B2, wherein said second diameter B2 is smaller than the first diameter B1.

[0043] In addition, the passage opening has two step-shaped circumferential shoulders, wherein the shoulders are each formed by a sudden decrease in the diameter of the passage opening, as seen from the top 10.1. The first shoulder has a circumferential shoulder surface that is formed by a top of the Ge sub-cell.

[0044] The second shoulder is located in the area of the Ge sub-cell, below a p/n junction of the Ge sub-cell.

[0045] The top 10.1 of the wafer 10 and a part of the side surface 22.1 of the passage opening 22 that adjoins the top 10.1 are coated with a dielectric insulating layer 24 by means of chemical vapor deposition.

[0046] The wafer 10.1 is then rotated and the bottom 10.2 and a part of the side surface 22.1 of the passage opening 22 that adjoins the bottom 10.2 are coated with the dielectric insulating layer 24 by means of chemical vapor deposition.

[0047] A layer thickness D1 of the dielectric insulating layer 24 within the passage opening is at least 10 nm.

[0048] A further example is shown in the illustration in FIG. 2. Only what is different from the illustration in FIG. 1 will be explained below.

[0049] In the plan view of the wafer top 10.1 including the passage opening 22, the two shoulders or shoulder surfaces can be seen. The shoulder surface of the first step-shaped shoulder has a tread depth S1. The second shoulder has a tread surface S2.

[0050] In the illustration in FIG. 3, a further embodiment is shown. Only what is different from the illustration in FIG. 1 or FIG. 2 will be explained below.

[0051] The passivation method is carried out on the wafer level, i.e. the wafer comprises a plurality of solar cell stacks 12, which can be seen in the plan view of the wafer top 10.1 in FIG. 3.

[0052] The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are to be included within the scope of the following claims.