Sequential circuit with timing event detection and a method of detecting timing events

Abstract

A sequential circuit with timing event detection is disclosed. The sequential circuit has an input that is asserted to the output during the second clock phase of a two phase clock signal. A timing event detector is coupled to the sequential element input to assert a timing event signal if a transition occurs at the sequential element input during the second clock phase but not to assert during the first clock phase.

Claims

1. A sequential circuit comprising: a sequential element having an input signal that is asserted to an output during a second clock phase of a two-phase clock signal; and a timing event detector coupled to the input signal of the sequential element, the timing event detector configured to assert an event signal in response to a transition occurring at the input signal of the sequential element during the second clock phase of the two-phase clock signal and further configured to refrain from asserting the event signal during a first clock phase of the two-phase clock signal, wherein the timing event detector comprises a clocked comparator configured to set its output based on a differential of the value of the input signal and the inverse value of the input signal at a clock edge, and wherein the timing event detector further comprises a digital logic block, and the clocked comparator is further configured to make the output available to the digital logic block in order to allow timing event detection.

2. The sequential circuit according to claim 1, comprising a feedback path from the digital logic block so the clocked comparator for using feedback from the digital logic block to maintain the state of the clocked comparator for the duration of the second clock phase.

3. A method of detecting timing events, the method comprising: making an output of a clocked comparator available to a digital logic block in order to allow timing event detection, in response to a clock signal transitioning from a first clock phase to a second clock phase: setting the output of said clocked comparator based on a differential signal consisting of the value of input data and the in-verse value of the input data; determining whether the input data is transitioning from a first state to a second state or from the second state to the first state while the clock signal is in its second clock phase; and in response to the input data transitioning from the first state to the second state or from the second state to the first state while the clock signal is in its second clock phase: flagging a timing event.

4. The method according to claim 3, comprising using feedback from said digital logic block to maintain the state of the clocked comparator for the duration of said second clock phase.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying drawings, which are included to provide a further understanding of the invention and constitute a part of this specification, illustrate embodiments of the invention and together with the description help to explain the principles of the invention. In the drawings:

(2) FIG. 1A is a diagram illustrating a prior art logic stage between two TED circuits;

(3) FIG. 1B is a timing diagram illustrating the concept of timing event detection;

(4) FIG. 2 is a schematic diagram of a prior art timing error detection circuit;

(5) FIG. 3 is a schematic diagram of a sequential logic element with timing event detection in accordance with an example embodiment;

(6) FIG. 4 is an example flow diagram of the sequential logic element with timing event detection of FIG. 3A;

(7) FIG. 5A is a schematic diagram of a sequential logic element with timing event detection in accordance with an example embodiment; and

(8) FIG. 5B is a timing diagram of the sequential logic element with timing event detection of FIG. 5a.

(9) Like reference numerals are used to designate like parts in the accompanying drawings.

DETAILED DESCRIPTION OF THE INVENTION

(10) Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings. The detailed description provided below in connection with the appended drawings is intended as a description of the present examples and is not intended to represent the only forms in which the present examples may be constructed or utilized. The description sets forth the functions of the examples and the sequence of steps for constructing and operating the examples. However, the same or equivalent functions and sequences may be accomplished by different examples.

(11) FIG. 3A illustrates a sequential logic element 300 with timing event detection in accordance with an example embodiment. This circuit 300 can be used e.g. to replace traditional master-slave flip-flop and/or latch-based circuits in critical paths of pipelined logic. The sequential logic element 300 of FIG. 3 comprises a data latch 301 and a timing event detector 302. The timing event detector 302 may be used e.g. to improve performance, improve yield, and reduce power consumption.

(12) The timing event detector 302 comprises a clocked comparator 303 and logic gates 304. The differential state of the clocked comparator 303 is set based on the value of the input data D when CLK transitions from low-to-high (LH). Logic gates 304 monitor the differential state of the clocked comparator 303. After CLK rises from LH, and the differential state of the clocked comparator has reached steady-state, the logic gates 304 apply a logic high on the feedback path 305 in order to maintain the differential state of the clocked comparator 303 until the CLK transitions high-to-low (HL). When CLK is high, any transitions of D from LH or HL trigger a timing event (TE).

(13) The timing event detector 302 removes the prior art need for a pulse generator, delay chains, or dynamic logic gates. Thus, the timing event detector 302 is advantageous e.g. in modern deep sub-micron CMOS circuits and at low supply voltages.

(14) FIG. 4 is an example flow diagram of a method 400 of detecting timing events. In the method 400 illustrated in FIG. 4, timing events are only detected when the clock signal CLK is high. Although it is not shown, the system can be designed to generate timing events only when CLK is low by adding an inverter to the CLK inputs of the latch 301 and the timing event detector 302 of FIG. 3.

(15) At operation 401, it is determined whether the clock signal CLK transitions from low-to-high. If yes, the method proceeds to operation 402. Otherwise, the method stays at operation 401.

(16) At operation 402, the differential state of the clocked comparator is set using the data signal D, an inverted version of D, and the clock signal CLK.

(17) At operation 403, feedback from a block of digital logic gates to the clocked comparator is set in order to ensure that further changes in the input data D do not change the differential state of the clocked comparator.

(18) At operation 404, it is determined whether the clock signal CLK is high. If yes, the method proceeds to operation 405. Otherwise, the method returns to operation 401.

(19) At operation 405, it is determined whether the data signal D transitions from LH or HL when CLK is high. If yes, the method proceeds to operation 406. Otherwise, the method returns to operation 404.

(20) At operation 406, a timing event is flagged in response to determining that D transitioned from LH or HL during the time CLK was high, i.e. in response to determining that D switched to a state which differs from the state recorded at operation 406. Finally, the method may return to operation 401.

(21) FIG. 5A is another schematic diagram of a sequential logic element 500 with timing event detection in accordance with an example embodiment. The sequential logic element 500 of FIG. 5A comprises a timing event detector 502 and a sequential element 501. The timing event detector 502 comprises a clocked comparator 503 and a digital logic block 504. The digital logic block 504 monitors the differential state of the clocked comparator 503 and the input data D, and when necessary, triggers a timing event TE. A timing event is triggered (i.e. TE transitions from low-to-high) when D transitions from LH or HL when CLK is high.

(22) The differential state of the clocked comparator 503 is determined from the value of the input data D when CLK transitions from LH. When CLK is low, the clocked comparator 503 is inactive and unable to change its differential state since NMOS transistors M3 and M4 are OFF and PMOS transistors M5 and M6 drive both outputs V.sub.C1 and V.sub.C2 of the clocked comparator 503 to a logic high. An inverted version of the input data signal D (here designated with Dn) assists the operation of the differential structure within the clocked comparator 503. When CLK transitions from LH, inputs D and Dn determine the outputs V.sub.C1 and V.sub.C2. If, for example, D is high and thus Dn is low, as CLK rises from LH V.sub.C2 is driven to a logic low (0 V) and V.sub.C1 is driven to a logic high (positive supply voltage, V.sub.DD). The pull-down network formed by NMOS transistors MX, MY, and MZ within the clocked comparator 503 is not active when CLK rises from LH. The pull-down network (MX, MY, and MZ) is active only after outputs V.sub.C1 and V.sub.C2 reach steady-state.

(23) The logic gate XOR1 within the digital logic gate block 504 monitors V.sub.C1 and V.sub.C2 within the clocked comparator 503. After CLK rises from LH and the differential outputs V.sub.C1 and V.sub.C2 of the clocked comparator reach steady-state, XOR1 triggers a logic high on node COMPs. A logic high on node COMPs is applied as feedback 505 in order to activate the pull-down network (MX, MY, and MZ) within the clocked comparator 503. The activation of the pull-down network due to COMPs transitioning from low-to-high ensures that the states of V.sub.C1 and V.sub.C2 are independent of the value of D during the time CLK is high. The pull-down strengths of MX, MY, and MZ are larger than those of transistors M2 and M1 to guarantee that the states of V.sub.C1 and V.sub.C2 are not affected by the transitions of D during the time CLK is high.

(24) Once node COMPs is high, the clocked comparator 503 is unable to change the state of V.sub.C1 and V.sub.C2 during the time CLK is high. V.sub.C2 is the logical complement of the value of D at the rising CLK edge. Thus, if D transitions from LH or HL during the time CLK is high, logic gate XNOR1 transitions from LH. Since COMPs is high, logic gate AND1 outputs a logic high and a timing event is flagged, i.e. the timing event TE node goes from low-to-high. In all other conditions, TE is low.

(25) Alternative implementations of the clocked comparator 503 and the digital logic 504 provide the same functionality. For example, the clocked comparator 503 may use one less transistor to be activated at the rising clock edge. In an embodiment, transistors M3 and M4 could be removed and replaced with a single transistor (with a CLK input signal). The single transistor with the CLK input signal could be added between ground and a new node which connects the source of transistors M1 and M2.

(26) The digital logic 504 may also be altered and still produce the same functionality. For example, logic gate XNOR1 may be replaced by a two-input multiplexer (MUX). The output of the MUX may be fed to the two-input logic gate AND1. The control signal to the MUX may be V.sub.C1, the zero-input to the MUX may be D, and the one-input may be Dn. V.sub.C1 is logically equivalent to D after the output of the clocked comparator 503 has settled (i.e. COMPs triggered high) following a transition of CLK from low-to-high. If, for example, D is high when CLK transitions from low-to-high, V.sub.C1 is high while CLK is high. Thus, V.sub.C1 passes the one-input of the MUX, or Dn. If during the time CLK is high, D does not transition, Dn remains low and the output of the MUX is low. If during the time CLK is high, D transitions from high-to-low, Dn transitions from low-to-high, and the MUX outputs a high. Consequently, logic gate AND1 triggers a timing event (TE) since both of its inputs are high.

(27) FIG. 5B is a timing diagram further detailing the operation of the circuit of FIG. 5A according to an example embodiment. As shown in diagram 550, at the rising edge (highlighted portion) of the clock signal CLK, either V.sub.C1 or V.sub.C2 is driven low depending on the value of the input data signal D. Consequently, the node COMPs is driven high once V.sub.C1 and V.sub.C2 settle. As shown in diagram 560, when the clock signal CLK is high (highlighted portion), any transitions of the input data signal D cause logic gate XNOR1 to transition from low-to-high. Since the node COMPs is already set high (i.e. after rising CLK edge), the logic gate AND1 has two high signals. Thus, the timing event node TE node transitions from low-to-high. Herein, this is referred to as timing event detection. As shown in diagram 570, when the clock signal CLK is low (highlighted portion), V.sub.C1 and V.sub.C2 are both high, and thus COMPs low. Thus, transitions of the input data signal D from low-to-high or high-to-low do not cause logic gate AND1 to transition from low-to-high (i.e. no timing-events are flagged).

(28) It is to be understood that although the latches 301, 501 of the above discussed embodiments are positive edge triggered latches, any type of latch (for example negative edge triggered) can be used without any loss of generality.

(29) The functionality described herein can be performed, at least in part, by one or more hardware logic components.

(30) Any range or device value given herein may be extended or altered without losing the effect sought. Also any embodiment may be combined with another embodiment unless explicitly disallowed.

(31) Although the subject matter has been described in language specific to structural features and/or acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as examples of implementing the claims and other equivalent features and acts are intended to be within the scope of the claims.

(32) It will be understood that the benefits and advantages described above may relate to one embodiment or may relate to several embodiments. The embodiments are not limited to those that solve any or all of the stated problems or those that have any or all of the stated benefits and advantages. It will further be understood that reference to an item may refer to one or more of those items.

(33) The steps of the methods described herein may be carried out in any suitable order, or simultaneously where appropriate. Additionally, individual blocks may be deleted from any of the methods without departing from the spirit and scope of the subject matter described herein. Aspects of any of the embodiments described above may be combined with aspects of any of the other embodiments described to form further embodiments without losing the effect sought.

(34) The term comprising is used herein to mean including the method, blocks or elements identified, but that such blocks or elements do not comprise an exclusive list and a method or apparatus may contain additional blocks or elements.

(35) While the present inventions have been described in connection with a number of exemplary embodiments, and implementations, the present inventions are not so limited, but rather cover various modifications, and equivalent arrangements, which fall within the purview of prospective claims.