METHOD OF CALIBRATING CAPACITIVE ARRAY OF SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER

Abstract

A method of calibrating capacitive array of a resistor-capacitor hybrid successive approximation register analog-to-digital converter (RC-hybrid SAR ADC) that includes a high M-bit capacitor DAC and a low N-bit resistor DAC. The method includes: disposing n unit capacitors in each capacitive array of the RC-hybrid SAR ADC, wherein n=2.sup.M1; sorting the capacitors in an ascending order according to their capacitances to form a sorted array, and selecting two capacitors C.sub.u(n/2)*, C.sub.u(n/2+1)* in the middle positions as a least significant bit (LSB) capacitor and a dummy capacitor, respectively; 4) obtaining a new array by forming each capacitor through adding two capacitors which have symmetrical positions with respect to the middle position(s) in the sorted array; and sorting the new array in an ascending order, and selecting the capacitor in the middle position as a higher bit capacitor. The method improves the static and dynamic performance of the SAR. ADC

Claims

1. A method for calibrating capacitive array of a resistor-capacitor hybrid successive approximation register analog-to-digital converter (RC-hybrid SAR ADC), wherein the RC-hybrid SAR ADC comprising a high M-bit capacitor DAC and a low N-bit resistor DAC, M represents the bit number of the high M-bit capacitor DAC, and N represents the bit number of the low N-bit capacitor DAC; the method comprising: 1) disposing n unit capacitors in a positive capacitive array and a negative capacitive array of the RC-hybrid SAR ADC, respectively, and labeling the n unit capacitors as: C.sub.u1, C.sub.u2, C.sub.u3, C.sub.u4, . . . , C.sub.u(n1), C.sub.un, wherein n=2.sup.M1; 2) sorting the n unit capacitors in an ascending order according to their capacitances, and recording them as: C.sub.u1*, C.sub.u2*, C.sub.u3*, C.sub.u4*, . . . , C.sub.u(n1)*, C.sub.un; 3) selecting the capacitor C.sub.u(n/2)* in a middle (2.sup.M1/2.sup.(0+1)=2.sup.M(0+2)).sup.th position of the capacitances as a least significant bit (LSB) capacitor in each of the positive capacitive array and the negative capacitive array of the RC-hybrid SAR ADC, wherein the LSB capacitor has a bit position number of 0; and selecting the capacitor C.sub.u(n/2+1)* in (2.sup.M2+1).sup.th position of the capacitances as a dummy capacitor in each of the positive capacitive array and the negative capacitive array of the RC-hybrid SAR ADC; 4) combining C.sub.u1* and C.sub.un* into A.sub.1, and combining C.sub.u2* and C.sub.u(n1)* into A.sub.2, . . . , and combining C.sub.u(n/21)* and C.sub.u(n/2+2)* into A.sub.(n/21), to yield a first array A.sub.i; 5) sorting the first array A.sub.i in an ascending order to obtain a second array A.sub.i* comprising A.sub.1*, A.sub.2*, A.sub.3*, A.sub.4*, . . . , A.sub.(n/2-1)*; selecting A.sub.(n/4)*, which is in a (2.sup.M1/2.sup.(1+1)=2.sup.M(1+2)).sup.th position of the second array A.sub.i*, as a second least significant bit (LSB+1) capacitor in each of the positive capacitive array and the negative capacitive array of the RC-hybrid SAR ADC, wherein the (LSB+1) capacitor has a bit position number of 1; 6) combining A.sub.1* and A.sub.(n/21)* into B.sub.1, combining A.sub.2* and A.sub.(n/22)* into B.sub.2, . . . , A.sub.(n/41)* and combining A.sub.(n/4+1)* into B.sub.(n/41), to yield a third array B.sub.i; 7) sorting the third array B.sub.i in an ascending order to obtain a fourth array B.sub.i* comprising B.sub.1*, B.sub.2*, B.sub.3*, B.sub.4*, . . . , B.sub.(n/41)*, and selecting B.sub.(n/8)*, which is in a (2.sup.M1/2.sup.(2+1)=2.sup.M(2+2)).sup.th position of the fourth array B.sub.i*, as a third least significant bit (LSB+2) capacitor in each of the positive capacitive array and the negative capacitive array of the RC-hybrid SAR ADC, wherein the (LSB+2) capacitor has a bit position number of 2; 8) repeating 6) and 7) to get other higher bit capacitors in each of the positive capacitive array and the negative capacitive array of the RC-hybrid SAR ADC; and 9) sorting the second to final array E.sub.i comprising E.sub.1, E.sub.2, E.sub.3 in an ascending order to obtain the final array E.sub.i* comprising E.sub.1*, E.sub.2*, E.sub.3*, and selecting E.sub.2*, which is in a (2.sup.M1/2.sup.(m1+1)=2.sup.M(m1+2)=2).sup.th position of the final array E.sub.i*, as a (LSB+m1) capacitor in each of the positive capacitive array and the negative capacitive array of the RC-hybrid SAR ADC, wherein the (LSB+m1) capacitor has a bit position number of m1, m is an integer and larger than 3, and M=m+2; and combining E.sub.1* and E.sub.3* to obtain a (LSB+m) capacitor that is a most significant bit (MSB) capacitor and has a bit position number of m.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] FIG. 1 is a schematic diagram of a RC-hybrid SAR ADC in the prior art.

[0017] FIGS. 2A-2B show the comparison of the unit capacitors C.sub.u1 and C.sub.u2 in two steps in the prior art. FIG. 2A shows the top plates of all the unit capacitors are switched to VCM. The bottom plate of C.sub.u1 in the positive capacitive array is switched to V.sub.REFP and the other bottom plates are switched to V.sub.REFN. The bottom plate of C.sub.u1 in the negative capacitive array is switched to VREFN and the other bottom plates are switched to VREFP. FIG. 2B shows the top plates of all the unit capacitors disconnects with V.sub.REFP; the bottom plate of C.sub.u2 in the positive capacitive array is switched to VREFP and the other bottom plates are switched to VREFN. The bottom plate of C.sub.u2 in the negative capacitive array is switched to VREFN and the other bottom plates are switched to VREFP.

[0018] FIGS. 3A-3G show the combination, sorting and median selection of capacitors according to one embodiment of the disclosure.

[0019] FIGS. 4A-4D are static simulation results of 14-bit SAR ADC according to one embodiment of the disclosure.

[0020] FIGS. 5A-5D are static simulation results of 16-bit SAR ADC according to one embodiment of the disclosure.

[0021] FIGS. 6A-6D are static simulation results of 18-bit SAR ADC according to one embodiment of the disclosure.

[0022] FIGS. 7A-7D are dynamic simulation results of 14-bit SAR ADC according to one embodiment of the disclosure.

[0023] FIGS. 8A-8D are dynamic simulation results of 16-bit SAR ADC according to one embodiment of the disclosure.

[0024] FIGS. 9A-9D are dynamic simulation results of 18-bit SAR ADC according to one embodiment of the disclosure.

DETAILED DESCRIPTION

[0025] The disclosure provides a capacitor mismatch calibration method, which also known as median selection. A 14-bit RC-hybrid SAR ADC comprising a high 8-bit capacitor DAC and a low 6-bit resistor DAC is taken as an example for detailed description. The structure of the M+N-bit RC-hybrid SAR ADC with high M-bit capacitor DAC and low N-bit resistor DAC is shown in FIG. 1.

[0026] If M=8, N=6, it means a 14-bit SAR ADC composed of a high 8-bit capacitor DAC and a low 6-bit resistor DAC. There are 128 unit capacitors in the positive capacitive array and the negative capacitive array respectively: C.sub.u1, C.sub.u2, C.sub.u3, C.sub.u4, . . . , C.sub.u127, C.sub.u128. 128 unit capacitors should be equal in value, but in fact, they are not completely equal after manufacture. In general, the mismatch errors of the capacitors are supposed to be a standard Gaussian distribution.

[0027] 128 unit capacitors are sorted in the ascending order according to their value for the first time and labeled as C.sub.u1*, C.sub.u2*, C.sub.u3*, C.sub.u4*, C.sub.u127*, C.sub.u128*. A method similar to FIGS. 2A-2B can be used to complete the comparison between every two capacitors. And FIGS. 2A-2B show the schematic diagram of the comparison between C.sub.u1 and C.sub.u2 in two steps.

[0028] As shown in FIG. 3B, the median selection is used for the first time of selecting: the two capacitors in the middle position (C.sub.u64* and C.sub.u65*) are selected as the least significant bit (LSB) and dummy capacitor of the converter respectively. The remaining capacitors are then combined for the first time: C.sub.u1*and C.sub.u128* are combined into A.sub.1, C.sub.u2* and C.sub.u127* are combined into A.sub.2, . . . , C.sub.u63* and C.sub.u66* are combined into A.sub.63.

[0029] As shown in FIG. 3C, Ai is sorted in the ascending order again to obtain a new array of A.sub.i*: A.sub.1*, A.sub.2*, A.sub.3*, A.sub.4*, . . . , A.sub.63*. And A.sub.32*, which is in the median position of A.sub.i*, is selected as the second least significant bit (LSB+1). And the same process above is repeat, the remaining capacitors are then selected and combined as shown in FIGS. 3D-3G to get the other higher bits of the converter: LSB+2, LSB+3, MSB (the most significant bit).

[0030] For 16-bit RC-hybrid SAR ADC composed of a high 8-bit capacitor DAC and a low 8-bit resistor DAC (M=8 and N=8 in FIG. 1), 18-bit RC-hybrid SAR ADC composed of a high-order 8-bit capacitor DAC and a low 10-bit resistor DAC (M=8 and N=10 in FIG. 1), these capacitors are sorted and reconstructed using the provided median selection method. The method is identical to the 14-bit RC-hybrid SAR ADC consisting of a high 8-bit capacitor DAC and a low 6-bit resistor DAC.

[0031] To evaluate the performance improvement of the provided median selection, 14-bit, 16-bit, and 18-bit RC-hybrid SAR ADC are simulated in Matlab to run extensive Monte Carlo simulations with the mismatch of capacitors (.sub.u=.sub.0/C.sub.0) of 0.2%, 0.15% and 0.1% separately. For the static simulation (differential nonlinearity (DNL) and integral nonlinearity (INL)), the Monte Carlo simulation time is set at 100. And for the dynamic simulation (spurious free dynamic range (SFDR) and signal-to-noise-and-distortion ratio (SNDR)), the Monte Carlo simulation time is set at 500.

[0032] The static simulation results of RC-hybrid SAR ADC are shown in FIGS. 4A-6D and summarized in Table 1. It can be found that for the maximum root-mean-square (RMS) of DNL, the 14-bit, 16-bit, 18-bit RC-hybrid SAR ADC are improved by 87.3%, 93.9%, and 94.9% to 0.16 LSB, 0.20 LSB and 0.37 LSB respectively, while the maximum RMS of INL are improved by 89.7%, 96.5%, 97.3% to 0.15LSB, 0.16 LSB and 0.36 LSB with the median selection.

[0033] The dynamic simulation results of RC-hybrid SAR ADC are shown in FIGS. 7A-9D and summarized in Table 2. For 14-bit SAR ADC, the worst-case of SFDR is improved from 72.61 dB to 98.81 dB and the worst-case of SNDR is improved from 68.31 dB to 85.67 dB by the provided median selection. Compared with the conventional SAR ADC, the mean of SFDR and SNDR is improved by 26.26 dB and 9.80 dB respectively. For 16-bit SAR ADC after calibration, the worst-case of SFDR is improved from 73.14 dB to 102.77 dB and the worst-case of SNDR is improved from 69.06 dB to 95.79 dB. And the provided median selection improves the mean of SFDR and SNDR by 32.73 dB and 18.34 dB respectively. For 18-bit SAR ADC, the median selection improves the worst-case of SFDR from 77.64 dB to 106.79 dB and improves the worst-case of SNDR from 72.94 dB to 102.70 dB. The mean of SFDR is enhanced by 36.75 dB, while the mean of SNDR is 26.40 dB higher than the median selection.

[0034] The capacitor calibration method based on median selection is applicable for any kind of data converters. Compared with the conventional calibration method, the median selection method improves the static and dynamic performance of the SAR ADC.

TABLE-US-00001 TABLE 1 Summary of 100 Monte Carlo simulation results of maximum RMS of DNL and INL Conventional Provided Improvement 14-bit DNL(LSB) 1.26 0.16 1.10 (.sub.u = 0.2%) INL(LSB) 1.45 0.15 1.30 16-bit DNL(LSB) 3.27 0.20 3.07 (.sub.u = 0.15%) INL(LSB) 4.63 0.16 4.47 18-bit DNL(LSB) 7.20 0.37 6.83 (.sub.u = 0.1%) INL(LSB) 13.30 0.36 12.94

TABLE-US-00002 TABLE 2 Summary of 500 Monte Carlo simulation results of SFDR and SNDR Conventional Provided Improvement 14-bit SFDR Min 72.61 98.81 26.20 (.sub.u = 0.2%) (dB) Mean 82.55 108.81 26.26 SNDR Min 68.31 85.67 17.36 (dB) Mean 76.20 86.00 9.80 16-bit SFDR Min 73.14 102.77 29.63 (.sub.u = 0.15%) (dB) Mean 85.55 118.28 32.73 SNDR Min 69.06 95.79 26.73 (dB) Mean 79.57 97.91 18.34 18-bit SFDR Min 77.64 106.79 29.15 (.sub.u = 0.1%) (dB) Mean 88.47 125.22 36.75 SNDR Min 72.94 102.70 29.76 (dB) Mean 82.70 109.10 26.40

[0035] It will be obvious to those skilled in the art that changes and modifications may be made, and therefore, the aim in the appended claims is to cover all such changes and modifications.