Voltage detector

Abstract

A voltage detector includes a voltage division circuit which outputs a divided voltage based on an input voltage, a comparison circuit which compares the divided voltage and a reference voltage to output a detection signal and a release signal, and a voltage limiting circuit which limits the divided voltage to a preset voltage.

Claims

1. A voltage detector, comprising: a voltage division circuit configured to output a divided voltage based on an input voltage; a comparison circuit configured to compare the divided voltage and a reference voltage to output one of a detection signal and a release signal; and a voltage limiting circuit configured to limit the divided voltage to a preset voltage, wherein the voltage division circuit comprises: an NMOS transistor having a source to which an output terminal of the voltage division circuit is connected, and a gate to which a constant voltage is applied, a first resistor connected between a first terminal to which the input voltage is applied, and a drain of the NMOS transistor, and a second resistor connected between the output terminal of the voltage division circuit and a second terminal to which a reference potential is applied.

2. The voltage detector according to claim 1, wherein the NMOS transistor is a depletion type, and wherein the constant voltage is the reference voltage.

3. The voltage detector according to claim 1, wherein the constant voltage is supplied from a voltage adjustment circuit to which the reference voltage is entered.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a circuit diagram illustrating an example of a voltage detector according to an embodiment of the present invention;

(2) FIG. 2 is a circuit diagram illustrating another example of the voltage detector according to the embodiment of the present invention;

(3) FIG. 3 is a circuit diagram illustrating a further example of the voltage detector according to the embodiment of the present invention; and

(4) FIG. 4 is a circuit diagram illustrating a voltage detector in Related Art.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(5) Embodiments of the present invention will hereinafter be described with reference to the accompanying drawings.

(6) FIG. 1 is a circuit diagram illustrating an example of a voltage detector according to an embodiment of the present invention.

(7) The voltage detector 100 according to the embodiment includes a voltage division circuit 10, a comparator 11, an output transistor 12, a reference voltage circuit 13, an NMOS transistor 14, and a constant voltage circuit 15. The voltage division circuit 10 has a resistor 101, an NMOS transistor 104, a resistor 102, and a resistor 103 connected in series between a monitoring terminal 2 and a ground terminal 3.

(8) The comparator 11 has an inversion input terminal to which a source of the NMOS transistor 104 is connected, a non-inversion input terminal to which the reference voltage circuit 13 is connected, and an output terminal connected to a gate of the output transistor 12 and a gate of the NMOS transistor 14. The NMOS transistor 14 has a drain and source connected across the resistor 103. The NMOS transistor 104 has a gate to which the constant voltage circuit 15 is connected.

(9) A description will next be made as to the operation of the voltage detector 100 according to the embodiment.

(10) Since the output of the comparator 11 is Lo in a release state in which a divided voltage provided from the voltage division circuit 10 is higher than a reference voltage of the reference voltage circuit 13, the NMOS transistor 14 turns off. The output of the voltage division circuit 10 is a voltage divided by the resistor 101 and the resistors 102 and 103 connected in series. The divided voltage increases with a rise in a voltage applied to the monitoring terminal 2.

(11) Here, since an NMOS transistor can't feed a current at a gate-source voltage lower than the threshold voltage of the NMOS transistor, the gate-source voltage of the NMOS transistor 104 is limited to a voltage which becomes equal to the threshold voltage of the NMOS transistor 104. Assuming that the threshold voltage of the NMOS transistor 104 is VTN, and the voltage provided from the constant voltage circuit 15 is VFIX, a source voltage of the NMOS transistor 104 is limited to a preset value expressed by VFIX-VTN. That is, the constant voltage circuit 15 and the NMOS transistor 104 operate as a voltage limiting circuit to limit the divided voltage. The divided voltage provided from the voltage division circuit 10 is therefore limited to the preset value expressed by VFIX-VTN even if a high voltage is applied to the monitoring terminal 2.

(12) For this reason, even if the voltage applied to the monitoring terminal 2 greatly exceeds the release voltage of the voltage detector, the divided voltage provided from the voltage division circuit 10 is limited by the NMOS transistor 104 and thus will not degrade the characteristic of the transistor which constitutes each input terminal of the comparator 11.

(13) Incidentally, in the limitation of the divided voltage, since the divided voltage is set higher than the reference voltage, no effect is given to the detection and release operations of the voltage detector.

(14) As described above, since the voltage detector 100 according to the embodiment includes the NMOS transistor 104 for limiting the divided voltage provided from the voltage division circuit 10, it is capable of maintaining the accuracy of the detection voltage and the release voltage.

(15) FIG. 2 is a circuit diagram illustrating another example of the voltage detector according to the embodiment.

(16) The voltage detector 200 has a configuration in which in terms of the voltage detector 100 illustrated in FIG. 1, the NMOS transistor 104 of the voltage division circuit 10 is replaced by a depletion type NMOS transistor 204 having a gate to which a reference voltage is applied. In other constituents, the same circuits as those in the voltage detector 100 are denoted by the same reference numerals, and their detailed description will be omitted.

(17) Assuming that a threshold voltage of the depletion type NMOS transistor 204 is VTND, and a reference voltage of a reference voltage circuit 13 is VREF, a divided voltage of a voltage division circuit 10 is limited to a value represented by VREFVTND. Since the threshold voltage of the depletion type NMOS transistor is a negative value, the voltage VREFVTND always becomes larger than the reference voltage VREF. The voltage detector 200 is therefore capable of limiting the divided voltage to a desired voltage by appropriately setting the threshold voltage VTND without including the constant voltage circuit 15.

(18) FIG. 3 is a circuit diagram illustrating yet another example of the voltage detector according to the embodiment.

(19) The voltage detector 300 has a configuration in which in terms of the voltage detector 100 illustrated in FIG. 1, the constant voltage circuit 15 is replaced by a voltage adjustment circuit 30 including a current source 301 and a PMOS transistor 302. In other constituents, the same circuits as those in the voltage detector 100 are denoted by the same reference numerals, and their detailed description will be omitted.

(20) The current source 301 has one terminal connected to a power supply terminal 1 and the other terminal connected to a source of the PMOS transistor 302. The PMOS transistor 302 has a source connected to a gate of an NMOS transistor 104, a gate to which a reference voltage circuit 13 is connected, and a drain connected to a ground terminal 3.

(21) The current source 301 and the PMOS transistor 302 form a source follower. A divided voltage is therefore limited to VREF+VTPVTN assuming that a threshold voltage of the NMOS transistor 104 is VTN, a threshold voltage of the PMOS transistor 302 is VTP, and a reference voltage is VREF.

(22) The voltage detector 300 according to the yet another example of the embodiment is therefore capable of limiting the divided voltage to a desired voltage and easily adjusting the same by the threshold voltage VTP of the PMOS transistor 302.

(23) Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments. It is needless to say that various changes can be made thereto within the scope not departing from the gist of the present invention.

(24) For example, a voltage detector which has a monitoring terminal 2 in common with a power supply terminal 1 is also capable of obtaining a similar effect. Also, for example, a voltage detector in which a voltage dividing ratio of a voltage division circuit 10 is not switched by an NMOS transistor 14 is also capable of obtaining a similar effect.

(25) Incidentally, in the conventional voltage detector 400, upon the power supply voltage being supplied in the state in which the intermediate voltage between the detection voltage and the release voltage is applied to the monitoring terminal 41, the comparator 43 outputs the release signal because the divided voltage of the voltage division circuit 42 is applied to the inversion input terminal. In the voltage detectors 100 through 300 of the present invention, on the other hand, since the voltage division circuits 10 respectively include the NMOS transistor 104 or the NMOS transistor 204, the divided voltage is increased more gently than the reference voltage Vref, and hence the comparator 11 can output the detection signal, even in the above-described situation. That is, according to the voltage detectors 100 through 300 of the present invention, there is also an effect that no restriction is imposed on the order of applying the voltages to the power supply terminal 1 and the monitoring terminal 2.