CAPACITIVE APPARATUS AND METHOD FOR PRODUCING THE SAME

Abstract

Embodiments of the application provide a capacitive apparatus and a method for producing the same. The capacitive apparatus includes at least one capacitor; where the at least one capacitor includes at least one first dielectric layer and at least one second dielectric layer, the first dielectric layer has a positive voltage coefficient and the second dielectric layer has a negative voltage coefficient; and/or the first dielectric layer has a positive temperature coefficient and the second dielectric layer has a negative temperature coefficient. Using a principle of positive and negative cancellation, when the at least one capacitor is regarded as a whole, a voltage coefficient and/or a temperature coefficient thereof may be zero or close to zero. Thus, when a bias voltage or a temperature of the at least one capacitor changes, a capacitance value thereof does not change or changes slightly, thereby effectively ensuring the performance of the capacitive apparatus.

Claims

1. A capacitive apparatus, comprising: at least one capacitor; wherein the at least one capacitor comprises at least one first dielectric layer and at least one second dielectric layer, the first dielectric layer has a positive voltage coefficient and the second dielectric layer has a negative voltage coefficient; and/or the first dielectric layer has a positive temperature coefficient and the second dielectric layer has a negative temperature coefficient, wherein the positive voltage coefficient of the first dielectric layer and the negative voltage coefficient of the second dielectric layer enable a voltage coefficient of the at least one capacitor to be zero or close to zero, the positive temperature coefficient of the first dielectric layer and the negative temperature coefficient of the second dielectric layer enable a temperature coefficient of the at least one capacitor to be zero or close to zero.

2. The capacitive apparatus according to claim 1, wherein the at least one capacitor comprises: a first capacitor comprising the first dielectric layer; a second capacitor comprising the second dielectric layer, wherein the first capacitor and the second capacitor are connected in parallel.

3. The capacitive apparatus according to claim 2, wherein the first dielectric layer comprises a first hafnium oxide (HfO.sub.2) layer, and the second dielectric layer comprises an yttrium oxide (Y.sub.2O.sub.3) layer.

4. The capacitive apparatus according to claim 3, wherein the first dielectric layer further comprises a first silicon dioxide (SiO.sub.2) layer, and a second SiO.sub.2 layer, wherein the first HfO.sub.2 layer is disposed between the first SiO.sub.2 layer and the second SiO.sub.2 layer.

5. The capacitive apparatus according to claim 4, wherein the second dielectric layer further comprises a third SiO.sub.2 layer, a fourth SiO.sub.2 layer, wherein the Y.sub.2O.sub.3 layer is disposed between the third SiO.sub.2 layer and the fourth SiO.sub.2 layer.

6. The capacitive apparatus according to claim 1, wherein the at least one capacitor comprises: a single capacitor comprising the first dielectric layer and the second dielectric layer.

7. The capacitive apparatus according to claim 6, wherein the second dielectric layer comprises two SiO.sub.2 layers, and the first dielectric layer comprises a second HfO.sub.2 layer, wherein the second HfO.sub.2 layer is disposed between the two SiO.sub.2 layers.

8. The capacitive apparatus according to claim 1, wherein the at least on capacitor further comprises: a substrate comprising a first surface; and a plurality of conductive layers disposed on the substrate, the substrate and the plurality of conductive layers are separated by the first dielectric layer and the second dielectric layer.

9. The capacitive apparatus according to claim 8, wherein the substrate is a conductive substrate, or the first surface of the substrate is provided with a conductive region with a resistivity lower than a preset threshold value, and one of the first dielectric layer and the second dielectric layer is contact with the first surface of the substrate.

10. The capacitive apparatus according to claim 9, wherein the first surface of the substrate is provided with at least one groove, and at least a portion of the conductive layers, the first dielectric layer and the second dielectric layer are disposed in the at least one groove.

11. The capacitive apparatus according to claim 8, wherein the substrate is an insulating substrate, and one of the conductive layers is contact with the first surface of the substrate.

12. A method for producing a capacitive apparatus, comprising: producing at least one capacitor; wherein the at least one capacitor comprises at least one first dielectric layer and at least one second dielectric layer, the first dielectric layer has a positive voltage coefficient and the second dielectric layer has a negative voltage coefficient, the positive voltage coefficient of the first dielectric layer and the negative voltage coefficient of the second dielectric layer enable a voltage coefficient of the at least one capacitor to be zero or close to zero; and/or the first dielectric layer has a positive temperature coefficient and the second dielectric layer has a negative temperature coefficient, the positive temperature coefficient of the first dielectric layer and the negative temperature coefficient of the second dielectric layer enable a temperature coefficient of the at least one capacitor to be zero or close to zero.

13. The method according to claim 12, wherein the producing at least one capacitor comprises: producing at least two capacitors connected in parallel; wherein the at least two capacitors comprise at least one first capacitor and at least one second capacitor, wherein the first capacitor comprises the first dielectric layer and the second capacitor comprises the second dielectric layer.

14. The method according to claim 13, wherein the first dielectric layer comprises a first SiO.sub.2 layer, a second SiO.sub.2 layer and a first HfO.sub.2 layer, wherein the first HfO.sub.2 layer is disposed between the first SiO.sub.2 layer and the second SiO.sub.2 layer; and the second dielectric layer comprises a third SiO.sub.2 layer, a fourth SiO.sub.2 layer and a Y.sub.2O.sub.3 layer, wherein the Y.sub.2O.sub.3 layer is disposed between the third SiO.sub.2 layer and the fourth SiO.sub.2 layer.

15. The method according to claim 14, wherein the producing at least one capacitor further comprises: producing at least one conductive layer on a substrate, wherein the substrate and the at least one conductive layer are separated by the first dielectric layer and the second dielectric layer.

16. The method according to claim 15, wherein a surface of substrate is contact with one of the first dielectric layer and the second dielectric layer, and the substrate is a conductive substrate or the surface of the substrate is provided with a conductive region with a resistivity lower than a preset threshold value.

17. The method according to claim 15, wherein the substrate is an insulating substrate, and one of the at least one conductive layer is contact with the substrate.

18. The method according to claim 15, wherein a surface of the substrate is provided with at least one groove, and the at least one conductive layer, the first dielectric layer and the second dielectric layer are disposed in the at least one groove.

19. The method according to claim 12, wherein the producing at least one capacitor comprises: producing a single capacitor, wherein the single capacitor comprises the first dielectric layer and the second dielectric layer.

20. The method according to claim 19, wherein the second dielectric layer comprises a fifth SiO.sub.2 layer and a sixth SiO.sub.2 layer, and the first dielectric layer comprises a second HfO.sub.2 layer, wherein the second HfO.sub.2 layer is disposed between the fifth SiO.sub.2 layer and the sixth SiO.sub.2 layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0065] FIG. 1 is a schematic block diagram of a capacitive apparatus according to an embodiment of the present disclosure.

[0066] FIG. 2 is an equivalent circuit diagram of two capacitors connected in parallel according to an embodiment of the present disclosure.

[0067] FIG. 3 is a schematic diagram of a curve of a capacitance value of a capacitor changing with a voltage value.

[0068] FIGS. 4 to 5 are schematic block diagrams of modified structures of the capacitive apparatus shown in FIG. 1.

[0069] FIGS. 6 to 11 are schematic flow charts of a method for producing the capacitive apparatus shown in FIG. 1 according to an embodiment of the present disclosure.

DESCRIPTION OF EMBODIMENTS

[0070] Technical solutions in embodiments of the present disclosure will be described hereinafter with reference to the accompanying drawings.

[0071] It should be understood that a capacitive apparatus of an embodiment of the present disclosure may play a role of bypassing, filtering, decoupling, or the like in a circuit.

[0072] The capacitive apparatus described in the embodiment of the present disclosure may be a 3D silicon capacitor, which may be a capacitor processed by semiconductor wafer processing technology.

[0073] Compared with a multilayer ceramic capacitor (Multilayer ceramic capacitor, MLCC), the 3D silicon capacitor has advantages of small size, high precision, strong stability, and long lifetime. In a processing flow of the 3D silicon capacitor, a 3D structure with a high depth-to-width ratio such as a via (Via), a trench (Trench), a pillar (Pillar) shape, a wall (Wall) shape, or the like is required to be first processed on a wafer or substrate, and then an insulating film and a low-resistivity conductive material are deposited on a surface of the 3D structure to produce a lower electrode, a dielectric layer and an upper electrode of the capacitor, sequentially.

[0074] Hereinafter, a capacitive apparatus and a method for producing the same according to the present disclosure will be introduced in detail with reference to FIGS. 1 to 11.

[0075] It should be noted that, for convenience of description, in the embodiments of the present disclosure, the same reference numeral represents the same component, and a detailed explanation for the same component is omitted in different embodiments for the sake of brevity. It should be understood that dimensions such as thicknesses, lengths and widths of various components in embodiments of the present disclosure shown in the drawings, as well as dimensions of the overall thickness, length and width of an integrated apparatus are merely illustrative, and should not constitute any limitation to the present disclosure.

[0076] In addition, to facilitate understanding, in the embodiments shown below, for structures shown in different embodiments, the same structure is denoted by the same reference number, and a detailed explanation for the same structure is omitted for the sake of brevity.

[0077] Embodiments of the present disclosure provide a capacitive apparatus and a method for producing the same, which could reduce a voltage coefficient and/or a temperature coefficient of the capacitor.

[0078] Optionally, the capacitive apparatus may include at least one capacitor.

[0079] The at least one capacitor includes at least one first dielectric layer and at least one second dielectric layer, the first dielectric layer has a positive voltage coefficient and the second dielectric layer has a negative voltage coefficient; and/or the first dielectric layer has a positive temperature coefficient and the second dielectric layer has a negative temperature coefficient.

[0080] That is, the voltage coefficient of the first dielectric layer of a first capacitor cancels out the voltage coefficient of the second dielectric layer of a second capacitor and/or the temperature coefficient of the first dielectric layer of the first capacitor cancels out the temperature coefficient of the second dielectric layer of the second capacitor, so that when the at least two capacitors connected in parallel are regarded as a whole, a voltage coefficient and/or a temperature coefficient thereof is zero or close to zero.

[0081] Thus, when a bias voltage or a temperature of the at least two capacitors changes, a capacitance value thereof does not change or changes slightly, thereby effectively ensuring the performance of the capacitive apparatus.

[0082] In other words, the positive voltage coefficient of the first dielectric layer and the negative voltage coefficient of the second dielectric layer enable a voltage coefficient of the at least one capacitor to be zero or close to zero; and/or the positive temperature coefficient of the first dielectric layer and the negative temperature coefficient of the second dielectric layer enable a temperature coefficient of the at least one capacitor to be zero or close to zero.

[0083] It should be understood that the coefficient close to zero may refer to that the coefficient is substantively zero, and at this time, when the bias voltage and/or temperature of the capacitor changes, the capacitance value thereof does not change or changes slightly.

[0084] In some embodiments of the present disclosure, the at least one capacitor may include:

[0085] at least two capacitors connected in parallel;

[0086] where the at least two capacitors include at least one first capacitor and at least one second capacitor, and the first capacitor has a positive voltage coefficient and the second capacitor has a negative voltage coefficient, so that a voltage coefficient of the at least two capacitors is zero or close to zero; and/or the first capacitor has a positive temperature coefficient and the second capacitor has a negative temperature coefficient, so that a temperature coefficient of the at least two capacitors is zero or close to zero.

[0087] FIG. 1 is a schematic block diagram of a capacitive apparatus 100 according to an embodiment of the present disclosure.

[0088] Referring to FIG. 1, the capacitive apparatus 100 may include a first capacitor and a second capacitor, where the first capacitor may be formed by a conductive region 131 formed on an upper surface of a substrate 130, a first dielectric layer 124 and a first conductive layer 123, and the second capacitor may be formed by the first conductive layer 123, a second dielectric layer 122 and a second conductive layer 121. Further, a first electrode 111 is electrically connected to the conductive region 131 and the second conductive layer 121 through a first via 151 in an insulating layer 140, and a second electrode 112 is electrically connected to the first conductive layer 123 through a second via 152 in the insulating layer 140, so that the first capacitor is connected in parallel with the second capacitor, thereby forming a large capacitor.

[0089] The first dielectric layer 124 may be formed of a material with a positive voltage coefficient, and the second dielectric layer 122 may be formed of a material with a negative voltage coefficient, so that a voltage coefficient of the capacitive apparatus 100 is zero or close to zero; and/or, the first dielectric layer 124 may be formed of a material with a positive temperature coefficient, and the second dielectric layer 122 may be formed of a material with a negative temperature coefficient, so that a temperature coefficient of the at least two capacitors is zero or close to zero. FIG. 2 is an equivalent circuit diagram of the capacitive apparatus 100 shown in FIG. 1.

[0090] Referring to FIG. 2, the capacitive apparatus 100 may include a first capacitor 210 and a second capacitor 220 connected in parallel.

[0091] FIG. 3 is a schematic diagram of a curve of a capacitance value of a capacitor changing with a voltage value.

[0092] Referring to FIG. 3, it is assumed that a capacitance value C.sub.1 of the first capacitor 210 increases with the increase of a bias voltage V across both ends thereof, and a capacitance value C.sub.2 of the second capacitor 220 decreases with the increase of a bias voltage V across both ends thereof, however when the capacitive apparatus 100 is regarded as a whole, a capacitance value thereof does not change with a bias voltage V across both ends thereof, thus effectively ensuring the performance of the capacitive apparatus.

[0093] FIG. 4 is a schematic structural diagram of a modified structure of the capacitive apparatus 100 shown in FIG. 1.

[0094] Referring to FIG. 4, the first dielectric layer 124 may include a first silicon dioxide SiO.sub.2 layer 1241, a second SiO.sub.2 layer 1243 and a first hafnium oxide HfO.sub.2 layer 1242, where the first HfO.sub.2 layer is disposed between the first SiO.sub.2 layer and the second SiO.sub.2 layer. Similarly, the second dielectric layer 122 may include a third SiO.sub.2 layer, a fourth SiO.sub.2 layer and an yttrium oxide Y.sub.2O.sub.3 layer, where the Y.sub.2O.sub.3 layer is disposed between the third SiO.sub.2 layer and the fourth SiO.sub.2 layer.

[0095] As a voltage coefficient of Y.sub.2O.sub.3 is negative and a voltage coefficient of HfO.sub.2 is positive, Y.sub.2O.sub.3 and HfO.sub.2 are respectively used as dielectric layers in two capacitors, so that when the two capacitors are regarded as a whole, a voltage coefficient thereof may be zero or close to zero.

[0096] Thus, when a bias voltage or a temperature of the two capacitors changes, a capacitance value thereof does not change or changes slightly, thereby effectively ensuring the performance of the capacitive apparatus.

[0097] In addition, Y.sub.2O.sub.3 and HfO.sub.2 belong to high dielectric constant (high-k) materials, and a band gap thereof is small, which easily causes leakage of the capacitor. Therefore, SiO.sub.2 with a wide band gap is placed on upper and lower surfaces of the high-k materials, which could reduce the leakage of the capacitor and ensure the comprehensive performance of the capacitor.

[0098] Further, the capacitive apparatus 100 may be formed by an even number of capacitors connected in parallel. For example, a number of the at least one first capacitor is equal to a number of the at least one second capacitor to ensure that the voltage coefficient and/or the temperature coefficient of the capacitive apparatus 100 is zero or close to zero. Of course, the capacitive apparatus 100 may also be formed by an odd number of capacitors connected in parallel, which is not specifically limited in the embodiment of the present disclosure.

[0099] In some other embodiments of the present disclosure, the at least one capacitor includes:

[0100] a third capacitor, where dielectric layers of the third capacitor include the first dielectric layer and the second dielectric layer, so that a voltage coefficient and/or a temperature coefficient of the third capacitor is zero or close to zero.

[0101] That is, the voltage coefficient of the first dielectric layer cancels out the voltage coefficient of the second dielectric layer, and/or the temperature coefficient of the first dielectric layer cancels out the temperature coefficient of the second dielectric layer, so that when the dielectric layers of the third capacitor are regarded as a whole, a voltage coefficient and/or a temperature coefficient thereof is zero or close to zero.

[0102] Thus, when a bias voltage or a temperature of the third capacitor changes, a capacitance value of the third capacitor does not change or changes slightly, thereby effectively ensuring the performance of the capacitive apparatus.

[0103] For example, the first dielectric layer includes a fifth SiO.sub.2 layer and a sixth SiO.sub.2 layer, and the second dielectric layer includes a second HfO.sub.2 layer, where the second HfO.sub.2 layer is disposed between the fifth SiO.sub.2 layer and the sixth SiO.sub.2 layer.

[0104] As a voltage coefficient of SiO.sub.2 is negative and a voltage coefficient of HfO.sub.2 is positive, a laminated layer formed by SiO.sub.2 and HfO.sub.2 is used as a dielectric layer of the third capacitor, so that a voltage coefficient of the third capacitor may be zero or close to zero.

[0105] In addition, HfO.sub.2 belongs to a high dielectric constant (high-k) material, and a band gap thereof is small, which easily causes excessive leakage of the capacitor. Therefore, SiO.sub.2 with a wide band gap is placed on upper and lower surfaces of the HfO.sub.2 layer, which could reduce the leakage of the capacitor and ensure the comprehensive performance of the capacitor.

[0106] Of course, in other alternative embodiments, the foregoing at least two capacitors and the foregoing third capacitor may be connected in parallel to form a capacitive apparatus with a large capacitance value, which is not specifically limited in the embodiment of the present disclosure.

[0107] In some embodiments of the present disclosure, the at least one capacitor is at least one capacitor formed by a laminated structure.

[0108] The laminated structure is provided with layers with different temperature coefficients and/or voltage coefficients, so that when the laminated structure is regarded as a whole, a voltage coefficient and/or a temperature coefficient thereof may be zero or close to zero, thereby ensuring the performance of the capacitive apparatus.

[0109] In some embodiments of the present disclosure, the laminated structure may include a plurality of dielectric layers and at least one conductive layer that are disposed over a substrate, where the plurality of dielectric layers and the at least one conductive layer form a structure that a dielectric layer and a conductive layer are adjacent to each other.

[0110] For example, the plurality of dielectric layers includes at least one first dielectric layer and at least one second dielectric layer, the first dielectric layer has a positive voltage coefficient and the second dielectric layer has a negative voltage coefficient; and/or the first dielectric layer has a positive temperature coefficient and the second dielectric layer has a negative temperature coefficient.

[0111] In some embodiments of the present disclosure, the substrate is a conductive substrate, or a surface of the substrate close to the laminated structure is provided with a conductive region with a resistivity lower than a preset threshold value, and a bottom layer of the laminated structure close to the substrate is a dielectric layer in the plurality of dielectric layers.

[0112] In some embodiments of the present disclosure, the substrate is an insulating substrate, and a bottom layer of the laminated structure close to the substrate is a conductive layer in the at least one conductive layer.

[0113] In some embodiments of the present disclosure, a surface of the substrate close to the laminated structure is provided with at least one groove, and at least a portion of the laminated structure is disposed in the at least one groove.

[0114] In some embodiments of the present disclosure, a bottom conductive layer of the at least one conductive layer close to the substrate or a bottom dielectric layer of the plurality of dielectric layers close to the substrate forms at least one of following structures:

[0115] a trench structure, a pillar structure, or a wall structure.

[0116] FIG. 5 is a schematic diagram of another modified structure of the capacitive apparatus 100 shown in FIG. 1.

[0117] Referring to FIG. 5, the capacitive apparatus 100 includes a conductive substrate 130, and an upper surface of the conductive substrate 130 extends downward to form at least one groove (for example, two grooves shown in FIG. 5). The capacitive apparatus 100 may include a first capacitor and a second capacitor, where the first capacitor may be formed by the conductive substrate 130, a first dielectric layer 124 and a first conductive layer 123, and the second capacitor may be formed by the first conductive layer 123, a second dielectric layer 122 and a second conductive layer 121. Further, a first electrode 111 is electrically connected to the conductive substrate 130 and the second conductive layer 121 through a first via 151 in an insulating layer 140, and a second electrode 112 is electrically connected to the first conductive layer 123 through a second via 152 in the insulating layer 140, so that the first capacitor is connected in parallel with the second capacitor, thereby forming a large capacitor.

[0118] The present disclosure also provides a method for producing a capacitive apparatus, which could reduce a voltage coefficient and/or a temperature coefficient of the capacitive apparatus.

[0119] In some embodiments of the present disclosure, the at least one capacitor is produced.

[0120] The at least one capacitor includes at least one first dielectric layer and at least one second dielectric layer, the first dielectric layer has a positive voltage coefficient and the second dielectric layer has a negative voltage coefficient; and/or the first dielectric layer has a positive temperature coefficient and the second dielectric layer has a negative temperature coefficient.

[0121] In some embodiments of the present disclosure, the positive voltage coefficient of the first dielectric layer and the negative voltage coefficient of the second dielectric layer enable a voltage coefficient of the at least one capacitor to be zero or close to zero; and/or the positive temperature coefficient of the first dielectric layer and the negative temperature coefficient of the second dielectric layer enable a temperature coefficient of the at least one capacitor to be zero or close to zero.

[0122] In some embodiments of the present disclosure, the producing at least one capacitor includes:

[0123] producing at least two capacitors connected in parallel;

[0124] where the at least two capacitors include at least one first capacitor and at least one second capacitor, and the first capacitor has a positive voltage coefficient and the second capacitor has a negative voltage coefficient, so that a voltage coefficient of the at least two capacitors is zero or close to zero; and/or the first capacitor has a positive temperature coefficient and the second capacitor has a negative temperature coefficient, so that a temperature coefficient of the at least two capacitors is zero or close to zero.

[0125] In some embodiments of the present disclosure, the first dielectric layer includes a first silicon dioxide SiO.sub.2 layer, a second SiO.sub.2 layer and a first hafnium oxide HfO.sub.2 layer, where the first HfO.sub.2 layer is disposed between the first SiO.sub.2 layer and the second SiO.sub.2 layer; and the second dielectric layer includes a third SiO.sub.2 layer, a fourth SiO.sub.2 layer and an yttrium oxide Y.sub.2O.sub.3 layer, where the Y.sub.2O.sub.3 layer is disposed between the third SiO.sub.2 layer and the fourth SiO.sub.2 layer.

[0126] In some embodiments of the present disclosure, a number of the at least one first capacitor is equal to a number of the at least one second capacitor.

[0127] In some embodiments of the present disclosure, the producing at least one capacitor includes:

[0128] producing a third capacitor, where dielectric layers of the third capacitor include the first dielectric layer and the second dielectric layer, so that a voltage coefficient and/or a temperature coefficient of the third capacitor is zero or close to zero.

[0129] In some embodiments of the present disclosure, the first dielectric layer includes a fifth silicon dioxide SiO.sub.2 layer and a sixth SiO.sub.2 layer, and the second dielectric layer includes a second hafnium dioxide HfO.sub.2 layer, where the second HfO.sub.2 layer is disposed between the fifth SiO.sub.2 layer and the sixth SiO.sub.2 layer.

[0130] In some embodiments of the present disclosure, the at least one capacitor is at least one capacitor formed by a laminated structure.

[0131] In some embodiments of the present disclosure, the producing at least one capacitor includes:

[0132] producing a plurality of dielectric layers and at least one conductive layer that are disposed above a substrate;

[0133] where the plurality of dielectric layers and the at least one conductive layer form a structure that a dielectric layer and a conductive layer are adjacent to each other.

[0134] In some embodiments of the present disclosure, the substrate is a conductive substrate, or a surface of the substrate close to the laminated structure is provided with a conductive region with a resistivity lower than a preset threshold value, and a bottom layer of the laminated structure close to the substrate is a dielectric layer in the plurality of dielectric layers.

[0135] In some embodiments of the present disclosure, the substrate is an insulating substrate, and a bottom layer of the laminated structure close to the substrate is a conductive layer in the at least one conductive layer.

[0136] In some embodiments of the present disclosure, a surface of the substrate close to the laminated structure is provided with at least one groove, and at least a portion of the laminated structure is disposed in the at least one groove.

[0137] In some embodiments of the present disclosure, a bottom conductive layer of the at least one conductive layer close to the substrate or a bottom dielectric layer of the plurality of dielectric layers close to the substrate forms at least one of following structures:

[0138] a trench structure, a pillar structure, or a wall structure.

[0139] FIG. 6 is a schematic flow chart of a method 300 for producing a capacitive apparatus 100 according to an embodiment of the present disclosure. FIGS. 7 to 11 are schematic block diagrams of respective structures formed in a process of producing the capacitive apparatus 100. A method for producing a capacitive apparatus according to an embodiment of the present disclosure will be exemplarily illustrated with reference to FIGS. 6 to 11.

[0140] Referring to FIG. 6, the method 300 may include:

[0141] S310, a conductive region is formed on an upper surface of a substrate.

[0142] For example, referring to FIG. 7, a silicon wafer may be selected as a substrate 130, and doping is performed on a local region of an upper surface of the substrate 130 to form a low-resistivity conductive region 131. Of course, in other alternative embodiments, a conductive substrate may also be directly used, or doping may also be performed on an entire upper surface of the substrate, which is not specifically limited in an embodiment of the present disclosure.

[0143] The substrate 130 may be a semiconductor substrate, a glass substrate, or an organic substrate whose surface is provided with a low-resistivity conductive layer. A material of the semiconductor substrate may be silicon, germanium, or III-V elements such as silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), or the like), or a combination of the foregoing different materials. The semiconductor substrate may also include an epitaxial layer structure of the substrate for insulating the substrate, such as a silicon-on-insulator (SOI) structure. The substrate 130 may be a whole piece of the wafer or a portion cut from the wafer.

[0144] S320, a first dielectric layer and a first conductive layer are deposited on the conductive region.

[0145] For example, referring to FIG. 8, a first dielectric layer 124 and a first conductive layer 123 are deposited on the conductive region 131, where the first dielectric layer 124 may have a negative voltage (temperature) coefficient or a positive voltage (temperature) coefficient.

[0146] A material of the first conductive layer 123 may be formed of a low-resistivity conductive material, which may be, for example, heavily doped polysilicon, a carbon material, or various metals such as aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), platinum (Pt), ruthenium (Ru), iridium (Ir), rhodium (Rh), or the like, or may be a low-resistivity compound such as titanium nitride and tantalum nitride, or a laminated layer or combination of the foregoing several conductive materials, which is not specifically limited in the embodiment of the present disclosure.

[0147] S330, a second dielectric layer and a second conductive layer are deposited on the first conductive layer.

[0148] For example, referring to FIG. 9, a second dielectric layer 122 and a second conductive layer 121 are deposited on the first conductive layer 123, and when the first dielectric layer 124 has a negative voltage (temperature) coefficient, the second dielectric layer 122 has a positive voltage (temperature) coefficient; and when the first dielectric layer 124 has a positive voltage (temperature) coefficient, the second dielectric layer 122 has a negative voltage (temperature) coefficient.

[0149] A material of the second conductive layer 121 and a material of the first conductive layer 123 may be the same or different, which is not specifically limited in the present disclosure.

[0150] S340, a step of the first conductive layer and a step of the second conductive layer are formed.

[0151] For example, referring to FIG. 10, the steps of the first conductive layer 123 and the second conductive layer 121 may be formed by a photolithography process, and the low-resistivity conductive region 131 of the substrate 130 is exposed.

[0152] S350, an insulating layer is deposited above the substrate, and a plurality of vias are formed in the insulating layer.

[0153] For example, referring to FIG. 11, an insulating layer 140 may be deposited above the substrate 130 as an interlayer dielectric layer for covering the substrate 130 and respective conductive layers. Further, a photolithography process may be combined with an etching process to form at least one first via 151 and at least one second via 152, where the first via 151 is configured to expose the conductive region 131 and the second conductive layer 121, and the second via 152 is configured to expose the first conductive layer 123.

[0154] A material of the first insulating layer 140 may be an organic polymer material, such as polyimide, parylene, benzocyclobutene (BCB), or the like, it may also be some inorganic materials, such as spin on glass (SOG), undoped silicon glass (USG), boro-silicate glass (BSG), phospho-silicate glass (PSG), boro-phospho-silicate glass (BPSG), silicon oxide synthesized by tetraethyl orthosilicate (TEOS), silicon oxide, silicon nitride and ceramic; and it may also be a laminated layer or combination of the foregoing materials.

[0155] S360, a conductive material is filled in the plurality of vias, and at least two electrodes are formed above the plurality of vias.

[0156] For example, referring to FIG. 1, a conductive material is filled in the first via 151 and the second via 152 to form conductive channels. Further, a first electrode 111 and a second electrode 112 are respectively produced above the first via 151 and the second via 152, where the first electrode 111 is connected to the low resistivity-conductive region 131 of the substrate 130 and the second conductive layer 121 through a conductive channel formed by the first via 151, and the second electrode 112 is electrically connected to the first conductive layer 123 through a conductive channel formed by the second via 152.

[0157] It should be understood that the etching process may include at least one of the following processes:

[0158] a dry etching process, a wet etching process or a laser etching process.

[0159] Further, the dry etching process may include at least one of the following etching processes: reactive ion etching, ion beam etching, or the like. A chemical raw material of the wet etching process may include, but is not limited to, an etching solution containing hydrofluoric acid. In some embodiments of the present disclosure, an etching method combining dry etching with wet etching is adopted, or an etching method combining laser etching with wet etching is adopted, which could effectively ensure the etched shape and the flatness of the bottom surface, or the like.

[0160] The deposition process includes, but is not limited to:

[0161] a physical vapor deposition (PVD) process and/or a chemical vapor deposition (CVD) process. For example, thermal oxidation, plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), electroplating, spin coating or spray coating, or the like.

[0162] It should also be understood that the method embodiment and the product embodiment may correspond to each other, and similar descriptions may refer to the product embodiment. For the sake of brevity, they will not be repeatedly described here.

[0163] It should also be understood that FIGS. 1 to 5 are only examples of the present disclosure, and should not be understood as limitation to the present disclosure.

[0164] For example, in other alternative embodiments, the process of producing the conductive region may be directly omitted. That is, the dielectric layer is directly produced on the conductive substrate.

[0165] It should also be understood that, each embodiment of the method 300 for producing the capacitive apparatus listed above may be executed by a robot or numerical control machine. The device software or process for executing the method 300 may execute the foregoing method 300 by executing the computer program code stored in the memory.

[0166] It shall be noted that each embodiment described in the present disclosure and/or the technical features in each embodiment can be combined with each other arbitrarily in the case of no conflict, and the technical solutions obtained after combination should also fall into the protection scope of the present disclosure.

[0167] It should be understood that sequence numbers of the foregoing processes do not mean execution sequences in various embodiments of the present disclosure. The execution sequences of the processes should be determined according to functions and internal logic of the processes, and should not be construed as any limitation on the implementation processes of the embodiments of the present disclosure.

[0168] An ordinary person skilled in the art may be aware that the preparation method described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware or a combination of computer software and electronic hardware. Whether these functions are implemented in the form of hardware or software depends upon a particular application of the technical solutions and constraint conditions of design. A person skilled in the art may use different methods to implement the described functions for each particular application, but it should not be considered that the implementation goes beyond the scope of the present disclosure.

[0169] In several embodiments provided by the present disclosure, it should be understood that the disclosed integrated apparatus, the components in the integrated apparatus and the method for producing the integrated apparatus may be realized in other manners. For example, the embodiments of the integrated apparatus described above are only exemplary. For example, the division of layers is just a division of logical functions, and there may be other division manners for practical implementations. For example, multiple layers or devices may be combined or integrated, and for example, the upper plate and the active material layer may be combined into one layer. Or some features (such as the active material layer) may be omitted or not produced.

[0170] The foregoing descriptions are merely specific embodiments of the present disclosure, however, the protection scope of the present disclosure is not limited thereto, persons skilled in the art who are familiar with the art could readily think of variations or substitutions within the technical scope disclosed by the present disclosure, and these variations or substitutions shall fall within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.