Abstract
A CMOS compatible heterogeneously integrated material platform for photonic integrated circuitry is invented. The material platform has SiO2 as cladding material, at least a bottom layer made of moderate refractive index (contrast) material(s), a bonded single crystal Si layer transfer from either a SOI wafer or a ion implanted single crystal Si wafer ready for ion cut split on top of the bottom layer, and some devices enabling light coupling between the devices made within these two layers. The invention provides a great material platform to offer a full set of photonic building blocks for all sorts of different applications such as photonic circuitry for optical neural network, quantum computing, telecommunication, data communication, optical switching, optical sensing, passive and/or active Si optical interposer with its size even bigger than lithography step field.
Claims
1. A material platform for a photonic integrated circuitry on a single wafer substrate comprises at least: A light circuit made of a set of optical building blocks in a layer of a moderate refractive index (contrast) material (named as a bottom layer) below a single crystal Si layer (named as a top Si layer); from a SOI substrate; A light coupling structure to allow light traveling between the optical build blocks in the bottom layer and the devices in the top Si layer.
2. The system of claim 1, wherein said single crystal layer is bonded on top of said set of optical building blocks in said bottom layer via a wafer-to-wafer bonding process.
3. The system of claim 1, wherein said set of optical building blocks is created in said bottom layer by a layer deposition and a layer patterning.
4. The system of claim 1, wherein said moderate refractive index (contrast) material has its refractive index value smaller than that of said single crystal Si layer with a minimal predetermined number in full optical spectrum.
5. The system of claim 1, wherein said wafer, from which said single crystal Si layer is obtained, is a silicon-on-insulator (SOI) wafer.
6. The system of claim 1, wherein said wafer, from which said single crystal Si layer is obtained, is a single crystal Si wafer with ion implantation ready for ion cut after said wafer-to-wafer bonding process.
7. The system of claim 1, wherein said set of optical building blocks in the bottom layer includes at least a device cross a lithography step field to extend the size of said photonic integrated circuitry beyond the size of a lithography step field(s) with minimal optical impact from any stitching error between the lithography step fields.
8. The system of claim 1, wherein said set of devices in said single crystal Si layer has at least a sacrificial dummy feature, which will be removed to leave a space for a bonded functional material chip, which is coupled with said light circuit in the bottom layer via an optical evanescence wave.
9. The system of claim 1, wherein said set of optical building blocks in the bottom layer has at least a sacrificial dummy feature, which will be removed to leave a undercut below a function device in the top Si layer to enhance its performance.
10. (canceled)
11. (canceled)
12. (canceled)
13. (canceled)
14. The system of the claim 1, wherein said set of devices in said single crystal Si layer has at least a sacrificial dummy feature above an optical building block in the bottom layer.
15. The system of the claim 14, wherein said sacrificial dummy feature is used as a RIE stop layer during a RIE process to remove all the dielectric materials above the dummy feature.
16. The system of the claim 14, wherein said sacrificial dummy feature is removed by isotropic RIE process, after all the dielectric materials above it have been removed, and leave only a thin layer of SiO2 over said optical building block in the bottom layer.
17. The system of the claim 16, wherein said thin layer of SiO2 allows the light passing through said optical building block in the bottom layer to leak out as an evanescence wave, which interacts with surrounding environment to allow an optical sensing.
18. The system of the claim 1, wherein said moderate refractive index (contrast) material is either Si3N4, or SiNO, or AlN, or diamond, LiNbO3, or SiC, or Ta2O5, or TiO2, or As2S3, or high index doped SiO2 hydex, or their stacked material combinations ie, one material layer on top of another material layer.
19. The system of the claim 1, wherein said moderate refractive index (contrast) material is made of trilayer material configured as A(t1)/SiO2(t2)/A(t2), where t1 is the thickness of a top layer made of material A, t2 is the thickness of a middle SiO2 layer thinner than half of the wavelength of a concerned optical wave in said light circuit in the bottom layer, t3 is the thickness of a bottom layer made of material A, in which A is either Si3N4, or SiNO, or AlN, or diamond, LiNbO3, or SiC, or Ta2O5, or TiO2, or As2S3, or high index doped SiO2 hydex.
20. The system of the claim 1, wherein said moderate refractive index (contrast) material is made of trilayer material configured as A(t1)/SiO2(t2)/B(t2), where t1 is the thickness of a top layer made of material A, t2 is the thickness of a middle SiO2 layer thinner than half of the wavelength of a concerned optical wave in said light circuit in the bottom layer, t3 is the thickness of a bottom layer made of material B (different from material A), in which A and B is either Si3N4, or SiNO, or AlN, or diamond, LiNbO3, or SiC, or Ta2O5, or TiO2, or As2S3, or high index doped SiO2 hydex.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0017] FIG. 1(a) an embodiment of existing SOI platform with SiN integrated; FIG. 1(b) an embodiment of the proposed moderate refractive index (contrast) material integrated below single crystalline Si layer with the photonic building blocks in it.
[0018] FIG. 2 (a)-(f) an embodiment of a step-by-step process flow for the proposed moderate refractive index (contrast) materials integrated with a single crystal Si layer from a SOI wafer bonded on top; FIG. 2(g) extra material chip bonded on top of patterned single crystal Si layer for a functional device; FIG. 2(h)-(j) an embodiment of a process flow to bond extra material directly on top of the device in the layer of moderate refractive index (contrast) material using sacrificial features built in the Si layer; FIG. 2(k)-(m) an embodiment of a process flow of making undercut structures below the passive or active devices in Si layer by introducing sacrificial features in the moderate refractive index material layer.
[0019] FIG. 3(a)-(f) an embodiment of a step-by-step process flow for the proposed moderate refractive index (contrast) materials integrated with a single crystal Si layer from an ion implanted Si wafer.
[0020] FIG. 4(a)-(l) an embodiment of a step-by-step process flow to generate photonic circuits in both single crystalline Si layer and the moderate refractive index material layer without patterning the moderate refractive index material layer before the single crystal Si layer bonded on.
[0021] FIG. 5(a) shows the projection view of the optical coupling structures between two layers for process flow shown in FIG. 4(d) during the pattern transfer from the top bonded single crystal Si layer to the bottom layer; FIG. 5(b)-(c) shows the cross section view along the A-A and B-B cuts respectively on FIG. 5(a); FIG. 5(d) shows the projection view of the optical coupling structures between two layers for process flow shown in FIG. 4(f); FIG. 5(e)-(f) shows the cross section view along the A-A and B-B cuts respectively on FIG. 5(b).
[0022] FIGS. 6(a) and (b) an embodiment of a process flow for the proposed material platform used for optical sensor applications with the removal of sacrificial features in Si layer to expose the waveguide structure in moderate refractive index (contrast) material layer.
DETAILED DESCRIPTION
[0023] The following numerous specific detail descriptions are set forth to provide a thorough understanding of various embodiments of the present disclosure. It will be apparent to one skilled in the art, however, these specific details need not be employed to practice various embodiments of the present disclosure. In other instances, well known components or methods have not been described.
[0024] FIG. 1(a) shows an embodiment of the existing silicon on insulator (SOI) platform 100 with SiN integrated on top of the patterned SOI layer. In details, the incoming SOI wafer has Si substrate 101 with buried oxide (BOX) layer 102. In the SOI layer, various photonic building blocks (devices), such as grating 103, different waveguide structures for the light routing, electrical to optical modulator 105, and Ge photodiode (Ge PD) 106. The active devices such as modulator 105 and Ge PD 106 is connected to vertical electrical connection paths 107. On top of the SOI layer, there is a layer of non stoichiometric silicon nitride (SiN) deposited by plasma enhanced chemical vapor deposition (PECVD) or physical vapor deposition (PVD). In the SiN layer, extra optical building blocks (or device) can be fabricated.
[0025] FIG. 1(b) shows the proposed wafer system 110 with moderate refractive index (contrast) material integrated below single crystalline Si layer. The system 110 starts with Si substrate 111, on which a layer of thermal oxide 112 with targeted thickness, which meets the requirement of optical designs, is grown. On top of oxide 112, a layer of moderate refractive index (contrast) material, in which various of photonic build blocks (or devices) are fabricated. They are photonic circuit 113, cross the lithography step field optical routing structure 114, coupling structure 115 for evanescence coupling and mode matching between the bottom photonic circuits in moderate refractive index (contrast) material and upper circuit in single crystal Si layer. Above the bottom layer of moderate refractive index (contrast) material, there is a bonded single crystal Si layer, in which various of photonic building blocks (devices) are built including but not limited to grating structure 116, modulator 117, Ge PD 118, various optical routing structures including those for between layer coupling 119, and vertical electrical connection paths 120 for active devices.
[0026] FIG. 2 shows an embodiment of a process flow for the proposed material platform to heterogeneously integrated moderate refractive index (contrast) material layer with device patterning, SiO2 backfill, then CMP before a bonded single crystal Si layer from a SOI wafer is introduced on top. The process starts with incoming Si wafer 201, on which a layer for thermal silicon oxide 202 is grown with predetermined thickness as shown in FIG. 2(a). A layer of moderate refractive index (contrast) material with predetermined thickness 203 is deposited on top as shown in FIG. 2(b). Since there is no thermal budget limitation and no concerns of plasma damage for the layer below, the higher temperature process for the best material properties can be used to deposit the layer 203. For example, the stoichiometric Si3N4 can be deposited via low pressure chemical vapor deposition (LPCVD) followed by high temperature (>1000 C) annealing to drive out NH and SiH bonds from the as-deposited layer 203. After the deposition, the photonic building blocks (or devices) is lithographically patterned, then pattern transfer into layer 203 by reactive ion etch (RIE) followed by backfill of SiO2 and CMP-ed to flatten the wafer surface with smooth surface quality ready for the incoming wafer-to-wafer bonding. During the layer 203's patterning, if needed, hard mask can be used and removed afterwards just like CMOS FEOL patterning.
[0027] FIG. 2(d) is a incoming SOI wafer from the SOI suppliers with a thin predetermined thermal oxide 204 grown on top. As shown in FIG. 2(e), the SOI wafer is then bonded on top of wafer already with the patterned moderate refractive index (contrast) layer 203 as shown in Fig.(c). The Si substrate (or carrier substrate) and BOX layer from the original SOI wafer are then removed. At the end, as shown in FIG. 2(f), a single crystal layer 205, which is the previous SOI layer, is left on wafer, whose carrier Si substrate is now 201. All the Silicon oxide below the layer 205 can be effectively treated as so-called BOX layer in a normal SOI wafer. Just as normal Si photonic process on virgin SOI wafer, all the photonic building blocks (or devices) can be made with in layer 205 as shown in FIG. 2(g). As such, there is no bonding alignment difficulty at all because the alignment assistant patterns in bottom layer 203 can be used during devices' (or build blocks') fabrication in layer 205. If needed, extra material chip 206 can be also bonded on top of layer 205 using collective chip-to-wafer bonding as shown in FIG. 2(g). The extra material can be III-V stack for light source, or detector, or modulator, or for semiconductor optical amplifier etc, while the coupling between devices in the layer 205 and devices in 206 is evanescence coupling while the bonding interface can be just simple SiO2-to-SiO2 or other dielectric to dielectric bonding interface.
[0028] FIG. 2(h) to FIG. 2(j) show a process flow to bond extra material directly on top of the device in the layer 203 of moderate refractive index (contrast) material. Comparing FIG. 2(g) and FIG. 2(h), apart from missing material die 206, FIG. 2(h) has extra patterned Si feature 207, which is a sacrificial structure. The surface of the wafer shown in FIG. 2(h) is planarized with all the building blocks (or devices) and features in layer 205 is covered by a thin SiO2. As shown in FIG. 2(i), the oxide above the sacrificial feature 207 is opened then followed by 207's removal, then a new material chip 208 can be bonded directly on top of the devices in layer 203 with evanescence coupling is needed. There are many choices of the materials and the devices made from different materials (or material stacks) by either collective chip-to-wafer bonding or transfer print. Device fabrication can be follow up if material 208 is only material or material stack rather than function device. The advantage of the doing device fabrication after bonding is that it mitigates the alignment challenge during collective die-to-wafer bonding.
[0029] FIG. 2(k) to FIG. 2(m) show a process flow of making some undercut structures below the passive or active devices to boost their performance. In this particular example, a modulator structure 209 in the single crystal Si layer 205 is used as an example. Compared with what has been shown in FIG. 2(h), in FIG. 2(k), below the device 209 in the single crystal Si layer, there is a sacrificial feature 210 in the bottom layer made with moderate refractive index (contrast) material. As shown in FIG. 2(l), in the SiO2 cladding layer, there are purposely created etch paths 211, from which the sacrificial feature of 212 can be removed either by RIE, vapour etch, or wet etch. This will leave a undercut structure as show in FIG. 2(mm) below the targeted device 209. The void can be sealed and flatten by subsequent SiO2 backfill and CMP.
[0030] FIG. 3 shows an embodiment of process flow for the proposed moderate refractive index (contrast) materials integrated with a single crystal Si layer from an ion implanted Si wafer. The preparation of the bottom part of the wafer with the fabricated building blocks (or devices) in the moderate refractive index (contrast) material layer is essentially the same as what have been shown from FIG. 2(a) to FIG. 2(c), which will not be repeated again. The description of the following process is very much similar to so-called wafer smart cut processes. For the incoming single crystal Si layer bonded on top of the moderate refractive index (contrast) material layer, as shown in FIG. 3(a), the incoming substrate is a single crystalline wafer 301, on which a thermal oxide SiO2 302 is grown shown in FIG. 3(b). As shown in FIG. 3(c), the wafer is then subject to ion implantation to created a highly stressed layer 304 with the densest implanted ion concentration. As shown in FIG. 3(d), the ion implanted wafer is then up-side-down bonded on top of the bottom portion of the wafer shown in FIG. 2(c). Under certain heat treatment or annealing, the substrate will be split from substrate as shown in FIG. 3(e). After a light polishing (CMP), the finished wafer will have the single crystal Si layer over the moderate refractive index (contrast) material layer as shown in FIG. 3(f), from which the subsequent processes can be carried out for device fabrication within the bonded layer.
[0031] FIG. 4 shows a schematic embodiment of process flow to generate photonic circuitry in both single crystalline Si layer and the moderate refractive index material layer without patterning the moderate refractive index material layer before the single crystal Si layer bonded on. One of the biggest advantage on the process side is to reduce the planarization (or CMP) process requirement if the patterned of the moderate refractive index material layer before bonding. Like the process flow shown from FIG. 2(a) to FIG. 2(b), the moderate refractive index (contrast) material layer is now on the wafer as shown in FIG. 4a, As shown in FIG. 4(b), a high quality SiO2 is then deposited cross the wafer. Without patterning the moderate refractive index (contrast) material, as shown in FIG. 4(c) a single crystal Si layer is bonded on top of the wafer as previously shown either from a SOI wafer (FIG. 2(d)-FIG. 2(f)) or from an ion implanted single crystal wafer (FIG. 3(a)-FIG. 3(f)). Without prepatterning of the moderate refractive index (contrast) material layer makes the single crystal Si bonding relatively easier. On the other hand, without the patterning, the moderate refractive index (contrast) material layer, which is left below some building blocks (device) and structures created in the Si layer, will act partially as bottom cladding materials. As such, it is undoubted that the detailed designs of the build blocks/devices in the Si layer need to be adjusted. Nevertheless, considering the well controlled deposition with stoichiometry is used for the moderate refractive index (contrast) material, its properties should also be well understood. Therefore it should be relatively easier to adjust various designs based on optical device modelling results.
[0032] The device patterning is carried out in the bonded single crystal layer as shown in FIG. 4(d) (note: for the simplicity of schematic drawing, the hard mask during the Si layer patterning is not shown here. Nevertheless, it should be there for the later wafer planarization purpose), Compared with FIG. 2(g), apart from absence of the feature 206, there are several extra features, such as 401, 402, 403, present in FIG. 4(d), which will be used as hard mask for the incoming pattern transfer into the moderate refractive index (contrast) material layer below. As shown in FIG. 4(e), photoresist protection 404, 405 is implemented on top of the building blocks (or devices), which would like to be preserved, while there is no photoresist protection layer on top for those features need to transfer to the moderate refractive index (contrast) material layer below. It is noticeable that the photoresist protection 405 on top of the layer-coupling structure is different from the rest of the building blocks (or devices). This is because that there is a transition happening along the direction perpendicular to the paper in this particularly drawing. We will discuss more in the following section in FIG. 5. As shown in FIG. 4(f), after RIE, the top pattern is successfully transfer into the bottom moderate refractive index (contrast) material layer. Then, as shown in FIG. 4(e), the remaining Si is removal in original place marked as 401, 402, 403. The protection photoresist 404, 405 is then removed as shown in FIG. 4(h). For some devices such as those shown as 406 in FIG. 4(h) in the moderate refractive index (contrast) material layer, extra patterning is needed. Considering devices in the moderate refractive index (contrast) material layer have much larger dimensions compared with those existing in Si layer, thicker photoresist can be used here as shown in FIG. 4(i), followed by pattern transfer into the moderate refractive index (contrast) material layer below as shown in FIG. 4(j). The resist can then be removed as shown in FIG. 4(k) followed by SiO2 backfill and CPM (as mentioned previously the hard mask used during the bonded Si patterning is very important here for CMP control).
[0033] FIG. 5(a) shows the projection view of the optical coupling structure, inside the paper for those shown as 405 in FIG. 4(ed), a optical device for light coupling between a building block in the bottom moderate refractive index (contrast) material layer and a device in the top bonded single crystal Si layer for the process steps described in FIG. 4(d) to FIG. 4(f). After process shown in FIG. 4(d) is done, ie. all the devices' patterns (or shapes) in top bonded single crystal Si layer has been created, the projection view of the bottom layer and the top layer transition area looks as what is being shown in FIG. 5(a). On top of the SiO2 layer 501, which separates the bottom layer from the top layer, the patterned structure 502 is created in the top Si layer. The cross section A-A cut and B-B cut are shown on the right hand side in FIG. 5(a) labeled as FIG. 5(b) and FIG. 5(c) respectively. Along the arrow 503 is the structure, which need to pattern transfer to the bottom layer as part of the coupling structure linking the bottom layer to the top layer, while the arrow 504 indicates the direction to the waveguide structure in the top Si layer, which is needed to be preserved in the subsequent process steps. FIG. 5(db) shows the top down view of the photoresist 505 protecting on the pattern structures in the top layer while leaving the structures on the left open during the pattern-transfer RIE process (as previously shown in FIG. 4(f)). Their cross sections patterns at both A-A and B-B cuts are also shown on the right hand side of FIG. 5(d) labeled as FIG. 5(e) and FIG. 5(f) respectively. After the top feature 506 in the top Si layer is removed and subsequent the process steps described from FIG. 4(g) to FIG. 4(l) are done, the light can travel from bottom layer to top layer and vice versa through such or similar structures via evanescence coupling, FIG. 6 shows an embodiment of the proposed material platform used for sensor applications via evanescence wave leaking from the waveguide built in the moderate refractive index (contrast) material layer, which has less light confinement. To enable sensor application, the thick dielectric above the bottom moderate refractive index (contrast) material layer need be mostly remove with only a thin SiO2 left over the the device designed to interact with either gas, or liquid, or both in the surround environment. In the proposed platform for sensor application 600, for the purpose of process illustration, it is assumed here that all the features shown in FIG. 6(a) are identical to those shown in FIG. 1(b). They are Si substrate 601, on which a layer of thermal oxide 602. On top of oxide 602, a layer of moderate refractive index (contrast) material, in which various of photonic build blocks (or devices) are fabricated. They includes photonic circuit 603, cross the lithography step field optical routing structure 604, coupling structure 605 for evanescence coupling and mode matching between the bottom circuit in moderate refractive index (contrast) material and upper circuit in single crystal Si layer. Above the bottom layer of moderate refractive index (contrast) material, there is a bonded single crystal Si layer, in which various of photonic building blocks (devices) are built including but not limited to grating structure 606, modulator 607, Ge PD 608, various optical routing structures including those for between layer coupling 609, and vertical electrical connection paths 610 for active devices. Nevertheless, in the bonded single crystal Si layer, there is one unique feature 611, which is a sacrificial dielectric RIE stop layer. As shown in FIG. 6(b), to remove most dielectric materials on top of the structure 603, a thick photoresist 612 is coated and pattern with the open 613 to allow RIE to etch away the most dielectric layer and stop within the feature 611, which can then be removed by isotropic RIE process. At the end, only a SiO2 layer thinner than the one separating the bottom moderate refractive index (contrast) material layer and top bonded Si layer is left on top of the structure 603, whose evanescence wave can interact with outside environment. After the photoresist 612 is removed, the chip can be used for sensing applications.
