Successive approximation analog-to-digital converter with nonlinearity compensation

Abstract

Successive-approximation-register (SAR) analog-to-digital conversion technique continues to be one of the most popular analog-to-digital conversion techniques, due to their versatility, which allows providing high resolution output or high conversion rates. In addition, SAR analog-to-digital converters (ADC) have a modest circuit complexity that results in low-power dissipation. A SAR ADC is, typically, composed of a single comparator, a bank of capacitors and switches, in addition to, a control digital logic. However, the comparator input capacitance is input-signal dependent, and hence introduces non-linearity to the transfer characteristics of the ADC. A simple technique is devised to significantly reduce this non-linearity, by pre-distorting the sampled-and-held input signal using the same comparator input capacitance.

Claims

1. A method of converting an analog signal to a digital signal using successive approximation, using circuitry comprising a sampling unit, a capacitor array, a sampling capacitor, a comparator, a successive approximation register and control logic, wherein, the method comprising: during a sampling phase that ends at a sampling edge, coupling the sampling capacitor to an input voltage and powering off the comparator; during a hold phase that begins at the sampling edge, de-coupling the sampling capacitor from the input voltage with the comparator powered off; during a pre-distortion phase subsequent to the hold phase and before a bit cycling phase, powering on the comparator with the sampling capacitor de-coupled from the input voltage, such that distortion caused by input capacitance variations of the comparator is reduced; and during the bit-cycling phase subsequent to the pre-distortion phase, coupling the sampling capacitor to a reference voltage with the comparator powered on.

2. An analog to digital converter for converting an analog signal to a digital signal using successive approximation, wherein the analog to digital converter is configured to provide a pre-distortion phase, following a sampling phase and prior to a bit-cycling phase, comprising: a sampling unit for sampling an analog input signal to produce a sampled signal; a capacitor array coupled to the sampling unit for producing an approximation signal; a comparator coupled to the capacitor array for comparing the approximation signal to the sampled signal; and a successive approximation register and control logic coupled to the comparator, the control logic: during a sampling phase, powering off the comparator and coupling the sampling capacitor to an input voltage; during a hold phase that begins subsequent to the sampling phase, de-coupling the sampling capacitor from the input voltage with the comparator powered off; during a pre-distortion phase subsequent to the hold phase and before a bit cycling phase, powering on the comparator with the sampling capacitor de-coupled from the input voltage, such that distortion caused by input capacitance variations of the comparator is reduced; and during the bit-cycling phase subsequent to the pre-distortion phase, coupling the sampling capacitor to a reference voltage with the comparator powered on.

3. A method of converting an analog signal to a digital signal using successive approximation, the method comprising: after a sampling phase and a hold phase, and before beginning a bit cycling phase, performing pre-distortion of a held signal by performing charge sharing between a sampling capacitor and a parasitic capacitance of a comparator, the held signal sampled during the sampling phase and held during the hold phase; whereby distortion caused by input capacitance variations of the comparator is reduced in the bit cycling phase in accordance with the pre-distortion.

4. An analog to digital converter for converting an analog signal to a digital signal using successive approximation, comprising: a sampling unit for sampling an analog input signal to produce a sampled signal; a capacitor array coupled to the sampling unit for producing an approximation signal; a comparator coupled to the capacitor array for comparing the approximation signal to the sampled signal; and a successive approximation register and control logic coupled to the comparator, the control logic: after a sampling phase and a hold phase, and before beginning a bit cycling phase, performing pre-distortion of a held signal by performing charge sharing between a sampling capacitor and a parasitic capacitance of the comparator, the held signal sampled during the sampling phase and held during the hold phase; whereby distortion caused by input capacitance variations of the comparator is reduced in the bit cycling phase in accordance with the pre-distortion.

5. A method of converting an analog signal to a digital signal using a main digital-to-analog converter (MDAC) comprising a sampling capacitor and a comparator, the method comprising: sampling an analog input signal to produce a sampled signal on the sampling capacitor by coupling the sampling capacitor with an input signal while a comparator is powered off; holding the sampled signal on the sampling capacitor subsequent to the sampling by de-coupling the sampling capacitor from an input signal while the comparator is powered off; pre-distorting the sampled signal subsequent to the holding by powering on the comparator while holding the sampled signal on the sampling capacitor; and generating an approximation signal by bit-cycling and in accordance with the pre-distorting.

6. A successive approximation analog-to-digital converter comprising: a main digital-to-analog converter (MDAC) comprising a sampling capacitor and a comparator; and control logic coupled with the MDAC to: sample an analog input signal to produce a sampled signal on the sampling capacitor by coupling the sampling capacitor with an input signal while the comparator is powered off; hold the sampled signal on the sampling capacitor subsequent to the sampling by de-coupling the sampling capacitor from an input signal while the comparator is powered off; pre-distort the sampled signal subsequent to the holding by powering on the comparator while holding the sampled signal on the sampling capacitor; and generating an approximation signal by bit-cycling and in accordance with the pre-distorting.

Description

BRIEF DESCRIPTION OF THE DRAWING FIGURES

(1) The invention may be further understood from the following detailed description in conjunction with the appended drawing figures. In the drawing:

(2) FIG. 1 is a block diagram of a SAR ADC.

(3) FIG. 2A is a plot of the simulation results showing the waveforms of the input signals to the comparator, V.sub.ipc, and V.sub.inc, during sample-and-hold and the subsequent bit-cycling, the corresponding differential signal (V.sub.ipcV.sub.inc), for a large input signal close to full-scale, in addition to the sample-and-hold signal.

(4) FIG. 2B is a plot of the simulation results showing the waveforms of the input signals to the comparator, V.sub.ipc, and V.sub.inc, during sample-and-hold and the subsequent bit-cycling, the corresponding differential signal (V.sub.ipcV.sub.inc), for a small input signal, in addition to the sample-and-hold signal.

(5) FIG. 3 is a plot of the comparator input transistor parasitic capacitance as a function in the input voltage.

(6) FIG. 4A is a diagram of a single ended version of the MDAC, in the sampling phase of operation.

(7) FIG. 4B is a diagram of a single ended version of the MDAC, in the hold phase of operation.

(8) FIG. 4C is a diagram of a single ended version of the MDAC, in the bit-cycling phase of operation.

(9) FIG. 5 is a timing diagram for the proposed pre-distortion technique.

(10) FIG. 6A is a diagram of a single ended version of the MDAC, in the sampling phase of operation in accordance with the predistortion technique of FIG. 5.

(11) FIG. 6B is a diagram of a single ended version of the MDAC, in the hold phase of operation in accordance with the predistortion technique of FIG. 5.

(12) FIG. 6C is a diagram of a single ended version of the MDAC, in the pre-distortion phase of operation in accordance with the predistortion technique of FIG. 5.

(13) FIG. 6D is a diagram of a single ended version of the MDAC, in the bit-cycling phase of operation in accordance with the predistortion technique of FIG. 5.

(14) FIG. 7A is a plot of the simulation results of the SAR ADC showing the differential input signal to the comparator (V.sub.ipcV.sub.inc), for a conventional SAR ADC (dotted line), and the described pre-distortion technique (solid line), for a large input signal showing the complete conversion cycle.

(15) FIG. 7B is a plot showing a zoom-in for a portion of the signal of FIG. 7A.

(16) FIG. 8A is a plot of the simulation results of the SAR ADC showing the differential input signal to the comparator (V.sub.ipcV.sub.inc), for a conventional SAR ADC (dotted line), and the described pre-distortion technique (solid line), for a small input signal showing the complete conversion cycle.

(17) FIG. 8B is a plot showing a zoom-in for a portion of the signal of FIG. 8A.

(18) FIG. 9 is a plot of a 128 point FFT of the ADC output at a sampling frequency of 4 MHz, and an input-signal frequency of 531.25 KHz, without the described technique.

(19) FIG. 10 is a plot of a 128 point FFT of the ADC output at a sampling frequency of 4 MHz, and an input-signal frequency of 531.25 KHz, with the described technique.

DETAILED DESCRIPTION

Summary

(20) Successive-approximation-register (SAR) analog-to-digital conversion technique continues to be one of the most popular analog-to-digital conversion techniques, due to their versatility, which allows providing high resolution output or high conversion rates. In addition, SAR analog-to-digital converters (ADC) have a modest circuit complexity that results in low-power dissipation. A SAR ADC is, typically, composed of a single comparator, a bank of capacitors and switches, in addition to, a control digital logic. However, the comparator input capacitance is input-signal dependent, and hence introduces non-linearity to the transfer characteristics of the ADC. A simple technique is devised to significantly reduce this non-linearity, by pre-distorting the sampled-and-held input signal using the same comparator input capacitance.

DESCRIPTION

(21) A 13-bit differential SAR ADC, implemented in 0.18 m technology, is shown in FIG. 1. The ADC DAC is realized by an M-bit capacitive main-DAC (MDAC) 101, and an N-bit resistive Sub-DAC (SDAC) 103, such that M+N is equal to 13-bits. M is equal to 9 and N is equal to 4 in this design. The capacitive MDAC is binary weighted with the smallest capacitance element equal to C.sub.u. The back-plate side of the capacitors can be connected to V.sub.REF, V.sub.REF/2, or ground (gnd). The resistive SDAC is a thermometer based DAC.

(22) The input differential signal, V.sub.id (V.sub.id=V.sub.ipV.sub.in) is sampled, by the bootstrapped switches, S.sub.1, of a sample-and-hold unit 105 on the MDAC capacitors. During sampling, all the capacitors back-plates are connected to V.sub.REF/2. The sampled input signal is held on the MDAC capacitance, thus the differential voltage, V.sub.idc(V.sub.idc=V.sub.ipcV.sub.inc), at the input of the comparator 107 is equal, initially, to a sampled version of the input differential signal V.sub.id, and in the first cycle of the bit-cycling process, the comparator compares the sampled V.sub.ip to V.sub.in, or in other words it compares V.sub.id to zero, which is the mid-scale value for the differential signal. Based on the comparator output, the SAR Logic 104 determines whether V.sub.id is positive or negative, sets the digital output MSB accordingly, and sends a control word to the DAC to generate the voltage value to be used in the second comparison cycle of the bit-cycling process. Note that since the signal is sampled on the top plate of the DAC capacitance, the MSB is resolved with no MDAC capacitor switching, and therefore the DAC capacitor array total capacitance (one-side) is 2.sup.M-1 C.sub.u, which is half that of the conventional approach [7].

(23) More specifically, if the comparator indicates that V.sub.id is positive (V.sub.ip>V.sub.in), the comparator outputs logic 1, and the control word to the DAC connects the back-plate of the C.sub.MSB (=2.sup.M-2C.sub.u), of the p-side to gnd, and the corresponding capacitor on the n-side to V.sub.REF. Hence, a voltage step of V.sub.REF/2 and V.sub.REF/2 are applied to the p-side and the n-side capacitor dividers formed by each DAC side, thus, ideally (ignoring the comparator parasitic capacitance) V.sub.idc becomes

(24) $\begin{array}{cc}{V}_{idc}=V_{id}+\frac{-V_{REF}}{2}\left[\frac{2^{M-2}{C}_u}{C_u+\underset{k=0}{\overset{M-2}{.Math.}}{2}^k{C}_u}\right]-\frac{+V_{REF}}{2}\left[\frac{2^{M-2}{C}_u}{C_u+\underset{k=0}{\overset{M-2}{.Math.}}{2}^k{C}_u}\right]& \left(1\right)\end{array}$

(25) where

(26) $C_u+\underset{k=0}{\overset{M-2}{.Math.}}{2}^k{C}_u=2^{M-1}{C}_u$

(27) Therefore,

(28) $\begin{array}{cc}{V}_{idc}=V_{id}-\frac{V_{REF}}{2}& \left(2\right)\end{array}$

(29) That is the comparator compares V.sub.id to V.sub.REF/2, and the output of the comparator indicates whether V.sub.id is greater than or smaller than V.sub.REF/2. Otherwise, if V.sub.id is negative, the p-side and n-side reverse their switching, comparing V.sub.id to V.sub.REF/2. The SAR logic sets the bit following the MSB of the digital output accordingly, and sends a control word to the DAC, switching the capacitors following the MSB capacitors to generate a new DAC voltage, and comparing V.sub.id to a value greater than or smaller than V.sub.REF/2, by V.sub.REF/4, in the third cycle of bit-cycling, hence

(30) $\begin{array}{cc}{V}_{idc}=V_{id}\frac{V_{REF}}{2}\frac{V_{REF}}{4}& \left(3\right)\end{array}$

(31) This process of conversion (bit-cycling) continues, switching the MDAC capacitors, in order, until M bits are resolved, and then the SDAC resolves the remaining N-bits. The resulting waveforms of V.sub.ipc and V.sub.inc, during sampling and bit-cycling, are shown in FIG. 2A and FIG. 2B. It is important to note that voltage levels of V.sub.ipc and V.sub.inc converge to the value of the input signal common-mode voltage, and that the large voltage steps are only experienced in the first few steps of bit-cycling. That is to say that, in the later bit-cycling cycles, the input signals to the comparator get close to the common-mode value of the of the input signal, and the comparator input capacitance is relatively constant. Thus, the largest capacitance variation is experienced in the first bit-cycling step.

(32) Accordingly, the comparator is basically comparing the sampled input V.sub.id to the DAC output voltage, V.sub.DAC, and (3) can be re-formulated as
V.sub.idc=V.sub.idV.sub.DAC(4)

(33) where V.sub.DAC is given by

(34) $\begin{array}{cc}{V}_{DAC}=V_{REF}(\frac{C_{\mathrm{MSB}}}{C_T}\frac{C_{\mathrm{MSB}-1}}{C_T}\frac{C_{\mathrm{MSB}-2}}{C_T}\mathrm{.Math.})& \left(5\right)\end{array}$

(35) where C.sub.T is equal to 2.sup.M-1C.sub.u and represents the total capacitance of one side of the MDAC. Eq. (1)-(5) represent the ideal operation. However, since the comparator has a parasitic input capacitance, this capacitance contributes to the capacitor divider formed by the MDAC. A plot of the comparator input-transistor capacitance, as a function of the input voltage to the transistor, is shown in FIG. 3. The transistor has an almost fixed capacitance value (C.sub.0) when it is OFF (input voltage to the transistor is low and less than the transistor threshold voltage), and an increasing capacitance value with the input voltage, when it turns on. Therefore, the capacitance can be assumed to be composed of a fixed part C.sub.0, and a variable input-dependent part C.sub.in.

(36) The comparator capacitance is considered in FIG. 4A-FIG. 4C, where different phases of operation are illustrated, and a single-ended version of the MDAC is considered for clarity. In FIG. 4C, C.sub.i can be any of the MDAC capacitors (C.sub.MSB, C.sub.MSB-1, . . . , etc.). The switching operation of each side of the MDAC can be described by referring to FIG. 4A-FIG. 4C. In FIG. 4A, illustrating a sampling phase of operation, a sampling switch is closed, and the capacitance of the comparator may be represented as shown. In FIG. 4B, illustrating a hold phase of operation, the sampling switch is open, and the capacitance of the comparator may be represented as shown. In FIG. 4C, illustrating bit-cycling, a switch (different than the sampling switch) associated with a capacitor C.sub.I may be open or closed, and the capacitance of the comparator may be represented as shown.

(37) Considering the comparator non-linear capacitance, the voltage added or subtracted to the sampled input differential signal, due to capacitor switching is

(38) $\begin{array}{cc}\begin{array}{c}{V}_{\mathrm{DAC}}^{}=V_{REF}(\frac{C_{\mathrm{MSB}}}{C_T+C_0+C_{in}}\frac{C_{\mathrm{MSB}-1}}{C_T+C_0+C_{in}}\\ \frac{C_{\mathrm{MSB}-2}}{C_T+C_0+C_{in}}+\mathrm{.Math.})\\ =V_{\mathrm{REF}}\frac{C_T}{C_T+C_0+C_{in}}(\frac{C_{\mathrm{MSB}}}{C_T}\frac{C_{\mathrm{MSB}-1}}{C_T}\frac{C_{\mathrm{MSB}-2}}{C_T}\mathrm{.Math.})\\ =V_{DAC}\frac{C_T}{C_T+C_0+C_{in}}\end{array}& \left(6\right)\end{array}$

(39) That is, the V.sub.DAC is a scaled version of the ideal case V.sub.DAC. A more accurate description is that V.sub.DAC is a distorted version of V.sub.DAC, since the term C.sub.T/(C.sub.T+C.sub.0+C.sub.in) is not of a constant value, and the value of C.sub.in is input-signal dependent.

(40) To compensate for the variation in the DAC steps values, an additional pre-distortion phase is introduced, after the sample-and-hold phase and before bit-cycling. For this pre-distortion to take effect, the comparator is powered-down during the sample-and-hold phase, and turned ON during the hold period only after occurrence of a sampling edge, before bit-cycling, as indicated in the timing diagram of FIG. 5. FIG. 6A-FIG. 6D illustrate the different phases of operation in this case. Compare FIG. 6A with FIG. 4A, FIG. 6B with FIG. 4B, and FIG. 6D with FIG. 4C. During the sampling and hold phases of FIG. 6A and FIG. 6B, the comparator is turned off, such that the input capacitance of the comparator is a constant C.sub.0. During a subsequent proposed pre-distortion phase (FIG. 6C), the comparator is turned on, before the start of the bit-cycling phase. During bit cycling (FIG. 6D), the effective capacitance is the same as in the conventional case (FIG. 4C).

(41) More particularly, referring to FIG. 6A-FIG. 6D, during sampling (comparator is OFF), the input-signal generates a charge on the MDAC capacitance, given by
Q=(C.sub.T+C.sub.0)V.sub.in(7)

(42) After the input signal is held on the capacitance C.sub.T+C.sub.0, that is in the pre-distortion phase, the comparator is powered-ON, and charge sharing results in
Q=V.sub.in(C.sub.T+C.sub.0+C.sub.in)(8)

(43) Therefore, the voltage held becomes

(44) $\begin{array}{cc}{V}_{in}^{}=\frac{\left(C_T+C_0\right)V_{in}}{\left(C_T+C_0+C_{in}\right)}& \left(9\right)\end{array}$

(45) Thus the held signal becomes a scaled (pre-distorted) value of the input signal in a similar manner to the DAC steps in (6). Therefore,

(46) $\begin{array}{cc}\frac{V_{in}^{}}{V_{DAC}^{}}=\frac{V_{in}}{V_{DAC}}\frac{C_T}{C_T+C_0}& \left(10\right)\end{array}$

(47) Hence, compared to the ideal case (V.sub.in/V.sub.DAC), the comparator causes only a gain error term (C.sub.T/(C.sub.T+C.sub.0)), and the input-signal dependent non-linear term that has C.sub.in is cancelled.

(48) According to (7)-(10), the described technique would result in perfect elimination of the comparator non-linear effect. However, in practice, the comparator capacitance C.sub.in changes during, bit-cycling. Nevertheless, since the largest change in the capacitance is in the first step of bit-cycling, compensating the comparator capacitance by its value at the beginning of bit-cycling results in a considerable improvement. The exact behavior of the SAR ADC bit-cycling, together with the non-linear comparator input capacitance that depends on the comparator input voltage, cannot be captured by a closed-form formula, and can be only fully captured by simulation, as is the case in [4]. The analysis presented is more intended to show that the improvement is achieved by pre-distorting V.sub.in, in the same direction of the DAC step error and by a factor that is a function of C.sub.in, resulting in partial compensation.

(49) The simulation results of the SAR ADC with and without the described pre-distortion technique are shown in FIG. 7A and FIG. 7B and in FIG. 8A and FIG. 8B, for a large-input signal and a small-input signal respectively. The ADC V.sub.REF=1V, and the ADC least-significant-bit (LSB)=0.244 mV. For the large input signal of value 894.226 mV (FIG. 7A), the pre-distortion phase pre-distorts the input signal by a step of 1.777 mV, which represents 7.28 LSB, and hence the held-signal is decreased to 892.449 mV. While, for the small input-signal, of 107.436 mV (FIG. 8A), which is about 8 times smaller than the large-signal, the step is 1.175 mV (4.8LSB). The pre-distortion step for the large input signal is about 0.2% of its value, whereas the pre-distortion step for the small input-signal is around 1.1% of the its value, which is greater percent than that for the large input-signal. This distorted step mechanism agrees with the simple expressions derived earlier, since the comparator capacitance (C.sub.in) seen by the differential signal applied to the comparator is greater for the case of the small input-signal. The pre-distortion steps compensate, considerably, the distorted DAC steps, due to the comparator input-capacitance non-linearity.

(50) 128-point FFT plots of the SAR ADC output without and with the proposed technique are shown in FIG. 9 and FIG. 10, respectively, for an input-signal frequency of 531.25 KHz, and a sampling frequency of 4 MHz. FIG. 9 shows that the ADC output experiences a considerable non-linearity with a third harmonic at 54.6 dB, and few other folded-back higher order harmonics. As stated earlier, the degradation in performance, due to the comparator non-linear capacitance of the comparator depends on the ratio of the comparator capacitance to the linear capacitance of the MDAC. The signal-to-noise-plus-distortion (SNDR) achieved without applying the proposed technique is 52.7 dB (FIG. 9). FIG. 10 shows a significant reduction in signal harmonics. An SNDR of 76 dB is achieved, when applying the pre-distortion technique (FIG. 10), which corresponds to more than 3.5 bits of improvement in performance.

(51) It will be appreciated by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential character thereof. The disclosed embodiments are therefore intended in all respects to be illustrative and not restrictive. The scope of the invention is indicated by the appended claims rather than the foregoing description, and all changes that come within the scope and range of equivalents thereof are intended to be embraced therein.