Broadband driver with extended linear output voltage

Abstract

Modern modulator drivers must be capable of delivering a large output voltage into a tens of ohms modulator, while minimizing the amount of distortion added by the driver. The driver should deliver the output voltage without exceeding a maximum distortion while minimizing the DC power consumption. Accordingly, a modulator driver includes a final stage amplifier with auxiliary transistors that turn on when the conventional differential pair of transistors approaches their maximum voltage of the linear region of their transfer function, thereby providing a more linear transfer function, in particular at large input voltages.

Claims

1. A transmitter driver: a first input and a second input for inputting a differential input voltage; an amplifier stage for receiving the differential input voltage, including: a first transistor and a second transistor forming a first differential pair; a first output connected to the first transistor, and a second output connected to the second transistor for outputting a differential output voltage; and a first auxiliary transistor connected to the first transistor, and a second auxiliary transistor connected to the second transistor, a first degeneration resistor extending between the first transistor and the second transistors configured to extend a linear voltage range of the amplifier stage; wherein the first auxiliary transistor and the second auxiliary transistor are configured to turn on in response to the differential input voltage exceeding a set value, for increasing the differential output voltage, thereby extending a linear region of a transfer function of the amplifier stage.

2. The transmitter driver according to claim 1, further comprising a first degeneration resistor extending between the first transistor and the second transistors configured to extend a linear voltage range of the amplifier stage.

3. The transmitter driver according to claim 1, further comprising a buffer stage; wherein the buffer stage comprises a first buffer transistor connected to the first transistor, and a second buffer transistor connected to the second transistor.

4. A transmitter driver comprising: a first input and a second input for inputting a differential input voltage; an amplifier stage for receiving the differential input voltage, including: a first transistor and a second transistor forming a first differential pair; a first output connected to the first transistor, and a second output connected to the second transistor for outputting a differential output voltage; and a first auxiliary transistor connected to the first transistor, and a second auxiliary transistors connected to the second transistor, wherein the first auxiliary transistor and the second auxiliary transistor are configured to turn on in response to the differential input voltage exceeding a set value, for increasing the differential output voltage, thereby extending a linear region of a transfer function of the amplifier stage; a buffer stage comprising a first buffer transistor connected to the first transistor, and a second buffer transistor connected to the second transistor; and wherein the buffer stage includes a third buffer transistor connected to the first buffer transistor and the first auxiliary transistor, and a fourth buffer transistor connected to the second buffer transistor and the second auxiliary transistor.

5. The transmitter driver according to claim 4, further comprising a first shift resistor connected to the third buffer transistor, and a second shift resistor connected to the fourth buffer transistor, for shifting the differential input voltage applied to the first auxiliary transistor and the second auxiliary transistor, wherein the first auxiliary transistor and the second auxiliary transistor are configured to turn on in response to the differential input voltage exceeding the set value, and output a current that is added in parallel to the differential output voltage, thereby extending the linear region of the transfer function of the amplifier stage.

6. The transmitter driver according to claim 5, further comprising a first capacitor and a second capacitor in parallel with the first shift resistor and the second shift resistor, respectively, configured to increase current from the third buffer transistor and the fourth buffer transistor at increased frequencies.

7. The transmitter driver according to claim 2, further comprising a second degeneration resistor connected to the first auxiliary transistor, and a third degeneration resistor connected to the second auxiliary transistor.

8. The transmitter driver according to claim 4, wherein the first buffer transistor and the second buffer transistor are configured to be respectively connected to a bias voltage.

9. The transmitter driver according to claim 4, further comprising a respective current source connected to each of the first buffer transistor, the second buffer transistor, the first transistor, and the second transistor.

10. The transmitter driver according to claim 9, wherein the respective current source connected to the first buffer transistor and the second buffer transistor, each comprise a variable current source for controlling a turn-on voltage of the first auxiliary transistor and the second auxiliary transistor.

11. The transmitter driver according to claim 10, further comprising a feedback loop configured to: sense a bias voltage of the first buffer transistor and the second buffer transistor respectively, compare the bias voltage to a reference voltage, and control the respective current sources connected to the first buffer transistor and the second buffer transistor to turn on the first buffer transistor and the second buffer transistor in response to the differential input voltage exceeding the set value.

12. The transmitter driver according to claim 1, further comprising a first cascode transistor and a second cascode transistor connected to the first transistor and the second transistor, respectively.

13. The transmitter driver according to claim 1, wherein the set value is about a maximum differential input voltage of the linear region of the transfer function of the amplifier stage.

14. A transmitter comprising: a transmitter driver comprising: a first input and a second input for inputting a differential input voltage; an amplifier stage for receiving the differential input voltage, including: a first transistor and a second transistor forming a first differential pair; and a first output connected to the first transistor, and a second output connected to the second transistor for outputting a differential output voltage; and a first auxiliary transistor connected to the first transistor, and a second auxiliary transistors connected to the second transistor, wherein the first auxiliary transistor and the second auxiliary transistor are configured to turn on in response to the differential input voltage exceeding a set value, for increasing the differential output voltage, thereby extending a linear region of a transfer function of the amplifier stage; a laser for generating an optical signal; and a modulator for modulating the optical signal in accordance with the differential output voltage.

15. The transmitter according to claim 14, further comprising a buffer stage; wherein the buffer stage comprises: a first buffer transistor including a first terminal connected to the first input, and a third terminal connected to a first terminal of the first transistor; and a second buffer transistor including a first terminal connected to the second input, and a third terminal connected to a first terminal of the second transistor.

16. The transmitter according to claim 15, wherein the buffer stage includes: a third buffer transistor including a first terminal connected to the first terminal of the first buffer transistor, and a third terminal connected to a first terminal of the first auxiliary transistor; and a fourth buffer transistor including a first terminal connected to the first terminal of the first buffer transistor, and a third terminal connected to a first terminal of the second auxiliary transistor.

17. The transmitter according to claim 16, further comprising a first shift resistor connected to the third terminal of the third buffer transistor, and a second shift resistor connected to the third terminal of the fourth buffer transistor for shifting the differential input voltage applied to the first terminals of the first auxiliary transistor and the second auxiliary transistors, whereby the first auxiliary transistor and the second auxiliary transistor are configured to turn on in response to the differential input voltage exceeding the set value, and output a current that is added in parallel to the differential output voltage, thereby extending the linear region of the transfer function of the amplifier stage.

18. The transmitter according to claim 14, wherein the set value is about a maximum differential input voltage of the linear region of the transfer function of the amplifier stage.

19. The transmitter driver according to claim 3, wherein the buffer stage includes a third buffer transistor connected to the first buffer transistor and the first auxiliary transistor, and a fourth buffer transistor connected to the second buffer transistor and the second auxiliary transistor.

20. The transmitter driver according to claim 4, wherein the set value is about a maximum differential input voltage of the linear region of the transfer function of the amplifier stage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The invention will be described in greater detail with reference to the accompanying drawings which represent preferred embodiments thereof, wherein:

(2) FIG. 1 is an schematic diagram of a transmitter in accordance with an embodiment of the present invention;

(3) FIG. 2 is a schematic diagram of a conventional final stage driver;

(4) FIG. 3 is a graph of a normalized transfer function of the driver of FIG. 2;

(5) FIG. 4 is a schematic diagram of a final stage driver with extended linear output voltage of FIG. 1;

(6) FIG. 5 is a graph of a normalized transfer function of the driver of FIG. 4;

(7) FIG. 6 is graph of THD vs normalized output voltage comparing conventional drivers with the driver of FIG. 4;

(8) FIG. 7 is a graph of normalized voltage gain vs normalized frequency comparing conventional drivers with the driver of FIG. 4;

(9) FIG. 8 is a schematic diagram of a final stage driver with cascode output stage and extended linear output voltage of FIG. 1; and

(10) FIG. 9 is a graph of THD vs normalized frequency comparing conventional drivers with the driver of FIG. 4.

DETAILED DESCRIPTION

(11) While the present teachings are described in conjunction with various embodiments and examples, it is not intended that the present teachings be limited to such embodiments. On the contrary, the present teachings encompass various alternatives and equivalents, as will be appreciated by those of skill in the art.

(12) A driver circuit 1, in accordance with the present invention comprises an input buffer 2, one or more variable gain amplifiers (VGA) 3.sub.i to 3.sub.n, and a last stage amplifier 4. The last stage amplifier 4 is responsible to deliver the current required to generate a desired output voltage. A gain controller 5 may be included in the driver circuit 1 or external thereto for sending gain control signals to one or each of the VGA's 3.sub.i to 3.sub.n. The gain controller 5 may receive a gain control signal VG_CTRL from an external source and/or the gain controller 5 may be part of a feedback loop, which compares the levels of the electrical signals from a tap (shown in broken lines) to a desired level and controls the gain of the VGA's 3.sub.i to 3.sub.n accordingly. The driver circuit 1 may be embedded between a digital to analog converter (DAC) 6 for generating an analog signal, which has been digitally processed, and an electro-optical transducer 7, e.g. a Mach-Zehnder modulator. A transmitter may comprise the driver circuit 1 in combination with the electro-optical transducer 7, and a light source, e.g. a laser, 10. Accordingly, the light source 10 generates an optical signal, which may then be modulated using the first and second output electrical signals from the driver circuit 1.

(13) If properly designed, the distortion introduced by the driver circuit 1 may be mainly generated in the last stage amplifier 4. Design and optimization of the last stage amplifier 4 is key to obtain good linearity. The proposed solution description is based in a SiGe Bipolar Transistor technology, i.e. first base terminal, second collector terminal, and third emitter terminal; however, the principle presented may be applied to CMOS or other technologies, e.g. first gate terminal, second drain terminal, and third source terminal.

(14) With reference to FIG. 2, a conventional driver circuit with differential output voltage may comprise a differential pair of transistors Q.sub.3 and Q.sub.4 as the last stage amplifier 4. In the last stage amplifier 4, the linear range of the differential pair Q.sub.3 and Q.sub.4 may be limited by their hyperbolic transfer function (See FIG. 3). FIG. 3 illustrates the differential pair transfer function and an ideal linear transfer function. Therefore, nonlinearities increase once the differential pair input voltage exceeds the differential pair linear region, e.g. outside the linear region may be defined as V.sub.in<0.75 V.sub.in_max and V.sub.in>0.75 V.sub.in_max. V.sub.in_max being the target or desired input voltage that generates the target or desired output voltage V.sub.out_max, required by the subsequent modulator 7. Accordingly, in the illustrated conventional driver circuit, in order to reach the target output voltage (V.sub.out_max) V.sub.in must equal 1.15*V.sub.in_max, since V.sub.in_max falls outside the linear region of the transfer function of the differential pair Q.sub.3 and Q.sub.4. The linear input voltage range of the differential pair Q.sub.3 and Q.sub.4 may be extended by using degeneration resistor(s) R.sub.1, however, the extended linear range comes at the expense of lower gain. Further extension of the linear range requires increase of the final stage current and degeneration, i.e. higher power consumption.

(15) The embodiment in accordance with the present invention, illustrated in FIG. 4, includes the combination of degeneration resistors R.sub.1 for extended linearity, and an auxiliary circuit, which may be comprised of auxiliary transistors Q.sub.3b and Q.sub.4b, for extending the linear region of the last stage amplifier 4. The last stage amplifier 4 includes a voltage level shifter 11, and a differential pair circuit 12. The voltage level shifter receives the input voltages from the previous VGA 3.sub.n at V.sub.INP and V.sub.INN. Interconnection between the last amplifier stage 4 and the previous VGA stage 3.sub.n requires the voltage level shifter 11 to shift the reference for the input electrical signals. Accordingly, the transistors Q.sub.1a and Q.sub.2a act as voltage buffers that shift the reference for the electrical signal. A first terminal, e.g. base or gate, of each buffer transistor Q.sub.1a and Q.sub.2a is connected to the voltage inputs V.sub.INN and V.sub.INP, while the second and third terminals, e.g. collector or drain, and emitter or source, are connected between a voltage source V.sub.CC and respective current sources I.sub.1a and I.sub.2a for biasing the buffer transistors Q.sub.1a and Q.sub.2a. The third terminal, e.g. emitter or source, of each buffer transistor Q.sub.1a and Q.sub.2a may be connected to a first terminal, e.g. base or gate, of the differential pair Q.sub.3a and Q.sub.4a, respectively, whereby the differential pair Q.sub.3a and Q.sub.4a transform the input voltages to output currents, which are transformed to output voltages by the load, e.g. the optical modulator 7, at outputs V.sub.OUTN and V.sub.OUTP. The second terminals of the differential pair Q.sub.3a and Q.sub.4a are connected to the outputs V.sub.OUTN and V.sub.OUTP, and the third terminals of the differential pair Q.sub.3a and Q.sub.4a are connected to the a respective current source I.sub.3 and I.sub.4 for biasing the differential pair Q.sub.3a and Q.sub.4a. The third terminals are also interconnected by the degeneration resistance R.sub.1.

(16) The differential pair circuit 12 may comprise two additional auxiliary transistors Q.sub.3b and Q.sub.4b that are biased off, but turn on once the input voltage exceeds a set value, e.g. a maximum input voltage V.sub.max_linear of the differential pair Q.sub.3a and Q.sub.4a that produces a linear output. The auxiliary circuit, e.g. the auxiliary transistors Q.sub.3b and Q.sub.4b, may be used to extend the linear region of the last stage amplifier 4, i.e. beyond that of the differential pair Q.sub.3a and Q.sub.4a. First terminals, e.g. base or gate, of the auxiliary transistors Q.sub.3b and Q.sub.4b may be connected to the third terminals of auxiliary buffer transistors Q.sub.1b and Q.sub.2b. Third terminals, e.g. source or emitter, of the auxiliary transistors Q.sub.3b and Q.sub.4b may be connected to ground as degenerated common-emitters, with resistors R.sub.4 and R.sub.5, respectively. The maximum input voltage V.sub.max_linear may be determined experimentally for each differential pair or selected based on experience, e.g. a predetermined average, minimum or maximum of a plurality of previous devices.

(17) Ideally, substantially matching the maximum input voltage of the differential pair Q.sub.3a and Q.sub.4a transfer function, i.e. the maximum input voltage V.sub.max_linear that produces a linear output, to the voltage that turns on the auxiliary transistors Q.sub.3b and Q.sub.4b may extend the linear operation range of the differential pair-based amplifier circuit 12 used in the last stage amplifier 4. Accordingly, as the input voltage approaches the maximum input voltage for the differential pair Q.sub.3a and Q.sub.4a, the auxiliary transistors Q.sub.3b and Q.sub.4b turn on.

(18) Auxiliary transistor bias input voltage is obtained from the auxiliary voltage buffer circuit, e.g. comprised of auxiliary voltage buffer transistors Q.sub.1b and Q.sub.2b, in parallel with the buffer transistors Q.sub.1a and Q.sub.2a, respectively. First terminals, e.g. gate or base, of the buffer transistors Q.sub.1a and Q.sub.2a and the respective auxiliary buffer transistors Q.sub.1b and Q.sub.2b may be connected to the same node, and second and third terminals connected between the voltage source V.sub.CC and respective current sources I.sub.1b and I.sub.2b. A DC voltage shift is introduced using shift resistors R.sub.2 and R.sub.3 in series with the respective third terminals of the auxiliary buffer transistors Q.sub.1b and Q.sub.2b. Capacitors C.sub.1 and C.sub.2, which may be in parallel with shift resistors R.sub.2 and R.sub.3, increase the current from the auxiliary voltage buffer transistors Q.sub.1b and Q.sub.2b, at increased frequencies.

(19) For example, when the input signal V.sub.INP and V.sub.INN is larger than V.sub.max_linear, e.g. 0.75 V.sub.in_max or 0.7 V, the input voltage, buffered by auxiliary voltage buffer transistors Q.sub.1b and Q.sub.2b, respectively, and shifted by shift resistor R.sub.2 and R.sub.3current source I.sub.1b and I.sub.2b, respectively, raises the voltage of the first terminal, e.g. base, of the respective auxiliary transistors Q.sub.3b and Q.sub.4b, which output a current that is added in parallel with differential pair transistor Q.sub.3a and Q.sub.4a, respectively, thereby extending the linear region of the transfer function of the last stage amplifier 4 and the driver 1.

(20) Process, voltage and temperature variation will change the voltage at which the auxiliary transistors Q.sub.3b and Q.sub.4b turn on, therefore, the voltage is made controllable by using the voltage drop in the shift resistors R2, R3. For this goal, the bias voltage of the auxiliary transistors Q.sub.3b and Q.sub.4b at their inputs in sensed by a controller Aux Bias using sensing resistors R7 and R8; this voltage is compared in comparator 11 with a reference voltage V.sub.REF while varying variable current sources I.sub.1b and I.sub.2b (see FIG. 1). Then a feedback loop with controller Aux Bias is used to vary the magnitude of the currents sources I.sub.1b and I.sub.2b, such that the auxiliary transistors Q.sub.3b and Q.sub.4b turn on at the same desired input voltage magnitude, e.g. V.sub.max_linear.

(21) The output of the auxiliary transistors Q.sub.3b and Q.sub.4b, e.g. the second terminals, e.g. drain or collector, may be connect to the differential pair output currents, therefore, the total output current is the addition of the differential pair Q.sub.3a and Q.sub.4a and the auxiliary transistors Q.sub.3b and Q.sub.4b.

(22) The obtained transfer function of the last stage amplifier 4 of FIG. 4, as illustrated in FIG. 5, is more linear, therefore, the target output voltage (V.sub.out_max) for the modulator 7 is obtained at an input voltage V.sub.in equal to the target input voltage V.sub.in_max, i.e. with 15% less input voltage.

(23) With reference to FIG. 6, the auxiliary transistors Q.sub.3b and Q.sub.4b extend the amplifier linear operation. For example, as illustrated by circles in FIG. 6, an output voltage equal to the target output voltage V.sub.out_max has 5.2% total harmonic distortion (THD) in a standard implementation, while using the auxiliary transistors Q.sub.3a and Q.sub.4a reduces the THD to 1.8%. Furthermore, current in the last stage amplifier 4 may increase due to the auxiliary transistors Q.sub.3a and Q.sub.4a by 2.3%, when the output voltage V.sub.out equals the target output voltage V.sub.out_max, e.g. from 59.17 mA to 61.13 mA. If the standard amplifier is modified to obtain 1.8% THD, its current consumption may increase by 17.7%, e.g. from 59.17 mA to 69.17 mA.

(24) With reference to FIG. 7, any impact on the frequency response due to the use of the auxiliary transistors Q.sub.3a and Q.sub.4a may be minimized by shielding their capacitance from the output, e.g. using cascode transistors Q.sub.3a with Q.sub.5 and Q.sub.4a with Q.sub.6. In the illustrated example the second terminal, e.g. drain, of the transistor pair transistors Q.sub.3a and Q.sub.4a, are connected with the third terminals, e.g. source, of the cascode transistors Q.sub.5 and Q.sub.6, while the first terminals, e.g. bases, of the cascode transistors Q.sub.5 and Q.sub.5 are both connected together and to a bias voltage, exemplified by a voltage source V.sub.casc. The example in FIG. 8 uses cascode transistors Q.sub.5 and Q.sub.6, but other circuit techniques are within the scope of the invention.

(25) With reference to FIG. 8, THD varies across frequency; however, the auxiliary transistors Q.sub.3a and Q.sub.4a reduce overall THD across frequency, making the driver 4 of the present invention an ideal solution for broadband circuits.

(26) The foregoing description of one or more embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.