High-speed DC shifting predrivers with low ISI

Abstract

A DC-shifting predriver has an input port configured for coupling to a serial data stream, an inverting output amplifier having an feedback node and an output port configured for coupling to a transistor at the input to a high-speed DAC or TX driver, and a capacitor AC-coupled between the input port and the feedback node. A weak feedback inverter having structure similar to, but less drive strength than the inverting output amplifier is coupled between the output port and the feedback node to act as a positive feedback latch. The predriver provides a DC shift up to 3V with high reliability and minimal intersymbol interference for data rates from 10 GS/s to 28 GS/s or higher. The predriver may provide multiple input ports implemented as a predriver array in an M-bit system, and the output amplifier may consist of N stages.

Claims

1. A high-speed DC-shifting predriver, comprising: an input port configured for coupling to a serial data stream; at least one inverting output amplifier having a feedback node, and having an output port configured for coupling to a transistor (input to DAC or TX driver); a capacitor AC-coupled between the input port and the feedback node; and a positive feedback latch coupled between the output port and the feedback node, the positive feedback latch having a lower drive strength than the inverting output amplifier.

2. The predriver of claim 1 wherein the positive feedback latch comprises a weak feedback inverter.

3. The predriver of claim 2 wherein the weak feedback inverter has structure similar to that of the inverting output amplifier.

4. The predriver of claim 1 wherein the at least one inverting output amplifier is configured to amplify voltage at the input port by an amount greater than 0.5V.

5. The predriver of claim 4 wherein the at least one output amplifier is configured to amplify voltage at the input port to within a range from about [VDDioVDDcore] to VDDio.

6. The predriver of claim 1 wherein the serial data stream has a data period, and wherein the predriver is configured to reduce intersymbol interference for a pseudorandom binary sequence to below 5% of the data period.

7. The predriver of claim 1 wherein the input port comprises M inputs each coupled to a corresponding one of M bits output from the serial data stream, where M is an integer.

8. The predriver of claim 1 wherein the input port comprises M inputs each coupled to a corresponding one of M bits output from the serial data stream, where M is an integer, and wherein the transistor comprises an input to an M-bit DAC or TX driver.

9. The predriver of claim 8 wherein the at least one inverting output amplifier comprises N amplification stages, where N is an integer.

10. The predriver of claim 1 wherein the at least one inverting output amplifier comprises N amplification stages, where N is an integer.

11. The predriver of claim 1 configured to eliminate substantially all overstress responsive to random data input and/or long 1 input transmitted at data rates up to about 10 GS/s.

12. The predriver of claim 1 fabricated as an integrated circuit.

13. A method, implemented in a DC-shifting transistor predriver for reducing intersymbol interference in a serial data stream transmitted at a high data rate, comprising: providing an inverting output amplifier having a feedback node, and having an output port configured for coupling to the transistor; receiving the serial data stream at the feedback node through an AC-coupling capacitor; and coupling a positive feedback latch between the output port and the feedback node, the positive feedback latch having a lower drive strength than the inverting output amplifier.

14. The method of claim 13 wherein the positive feedback latch comprises a weak feedback inverter.

15. The method of claim 14 wherein the weak feedback inverter has structure similar to that of the inverting output amplifier.

16. The method of claim 13 further comprising amplifying, by the inverting output amplifier, the serial data stream by an amount greater than 0.5V.

17. The method of claim 16 wherein the amplifying step comprises amplifying the serial data stream by an amount from about [VDDioVDDcore] to VDDio.

18. The method of claim 13 wherein serial data stream has a data period, and wherein the intersymbol interference is less than 5% of the data period.

19. The method of claim 13 wherein the inverting output amplifier comprises N amplification stages, where N is an integer.

20. The method of claim 13 wherein the transistor comprises an input to a DAC or TX driver.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other systems, methods, features and advantages of the invention will be or will become apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features and advantages be included within this description, be within the scope of the invention, and be protected by the accompanying claims. Component parts shown in the drawings are not necessarily to scale, and may be exaggerated to better illustrate the important features of the invention. Dimensions shown are exemplary only. In the drawings, like reference numerals may designate like parts throughout the different views, wherein:

(2) FIG. 1 is a block diagram of a circuit known in the prior art for implementing a predriver for a high-speed TX driver or DAC.

(3) FIG. 2 is a block diagram of another circuit known in the prior art for implementing a predriver for a high-speed TX driver or DAC, having AC-coupled buffers at the first stage of the predriver array.

(4) FIG. 3 is an exemplary eye diagram illustrating how ISI is calculated.

(5) FIG. 4 is an eye diagram showing characteristic ISI curves for an output waveform when random data is input to a prior art predriver at 28 GS/s with poles at 5.3 MHz and 40 MHz.

(6) FIG. 5 is a graph showing comparative plots of voltage waveforms at Node A of a circuit known in the prior art for implementing a predriver for a high-speed TX driver or DAC.

(7) FIG. 6 is an eye diagram showing characteristic ISI curves, in a prior art 5-stage predriver, for an output voltage waveform at 28 GS/s with poles at 5.3 MHz and 40 MHz, given random input followed by a long stream of 1's.

(8) FIG. 7 is a block diagram of a circuit known in the prior art for a predriver for a high-speed TX driver or DAC, with AC-coupled input that introduces parasitic capacitance.

(9) FIG. 8 is a block diagram of one embodiment a high-speed DC-shifting predriver according to the present invention.

(10) FIG. 9 is a graph of waveforms for input and output voltage in a high-speed DC-shifting predriver according to the present invention.

(11) FIG. 10 is a graph showing the voltage waveform at Node A in a high-speed DC-shifting predriver according to one embodiment of the present invention, given input consisting of random data followed by repeating l's followed by random data.

(12) FIG. 11 is an eye diagram showing characteristic ISI curves for an output waveform when random data followed by a long stream of 1's at 28 GS/s as input to one embodiment of a high-speed DC-shifting predriver of the present invention.

(13) FIG. 12 is a conceptual manufacturing diagram for shielding a Node A within input nodes on a CMOS chip in one embodiment of a high-speed DC-shifting predriver according to the invention.

(14) FIG. 13 is a block diagram illustrating one application for a high-speed DC-shifting predriver of the present invention as buffer stage for an H-bridge transmitter DAC driver used for PAM4 signal processing.

DETAILED DESCRIPTION OF THE INVENTION

(15) The following disclosure presents apparatus and methods of the present invention that achieve a high-speed DC-shifting predriver with high reliability and minimal ISI. The invention employs a weak inverter as a positive feedback latch across the output stage of the predriver to ensure that a serial data stream can be amplified at a high data rate with low risk of overstress to drive an input transistor, e.g. for a DAC or TX driver.

(16) FIG. 8 shows a block diagram of one embodiment a high-speed DC-shifting predriver 80 according to the present invention. For purposes of illustration, predriver 80 is shown as a simplified model having a single amplification stage. Other embodiments of the invention are contemplated wherein the amplification may be carried out using a plurality of N stages, as shown in FIG. 2. Also for simplicity of illustration, predriver 80 is modeled with a single input port 81, although in practice it may include a plurality of M input ports to drive an M-bit DAC or TX driver configured for processing M data slices, also as shown in FIG. 2.

(17) The input port 81 may be configured to receive a serial data stream 83. Sources 85 of serial data stream 83 may include a serializer or a retimer, according to preferred implementations of the invention. Serial data stream 83 may be transmitted at any desired data rate; however, simulations have demonstrated that predriver 80 may process data rates up to about 10 GS/s or higher, with high reliability, i.e., low ISI with no or minimal overstress. As used herein, the term overstress means exceeding the rated gate voltage of a device. In one embodiment, predriver 80 can process data rates with high reliability between about 10 GS/s and about 28 GS/s. In another embodiment, predriver 80 can process data rates up to 56 GS/s with similar reliability.

(18) The input port 81 may be coupled to a feedback node 86 through an AC-coupling capacitor C.sub.AC. In an exemplary embodiment, capacitor C.sub.AC may have a capacitance range of about 50 fF to about 150 fF. For certain implementations of the invention, i.e. fabrication of predriver 80 on an integrated circuit and passage of high data rates, parasitic capacitance CP1 and CP2 are modeled as shown. Feedback node 86 is located at the input to an inverting output amplifier 87. In one embodiment, the amplifier 87 may be configured to amplify voltage of an input signal by a magnitude between about 0.5V and 2.0V at the inverted output node 88. In another embodiment, amplifier 87 may be configured to amplify that same voltage by an amount greater than 2.0V.

(19) According to the invention, predriver 80 includes a positive feedback latch 89 coupled between the inverted output node 88 and the feedback node 86. The positive feedback latch 89 is configured so that is has a lower drive strength than the inverting output amplifier 87. The latch functionality helps to ensure that the feedback node 86 is always driven strongly as data is being transmitted. Furthermore, coupling the positive feedback latch 89 in this manner in place of a feedback resistor removes any frequency dependent time constant from the circuit. This has the advantageous effect of minimizing ISI due to random datastreams, as demonstrated below by eye diagram analysis. In a preferred embodiment, positive feedback latch 89 may comprise a weak feedback inverter. As used herein, a weak feedback inverter refers to an inverting amplifier in the feedback loop of amplifier 87 that has a lower drive strength than that of amplifier 87. In one embodiment, the weak feedback inverter that serves positive feedback latch 89 may have a similar structure as that of amplifier 87. This configuration for positive feedback ensures that a reliable voltage will occur at the feedback node 86, without causing overstress or reliability concerns.

(20) FIG. 9 shows a graph of waveforms for voltage at input port 81 and for voltage at node 86 in a high-speed DC-shifting predriver according to the present invention. In this exemplary implementation, predriver 80 is configured to provide a DC shift of about 2.0V. The same predriver circuit 80 was subjected to reliability tests using various simulations. In one example, predriver 80 was subjected to a test input data stream consisting of random data, followed by a long stream of binary ones, followed by more random data. The random data was generated as a pseudorandom binary sequence such as defined by the PRBS15 standard. The results are provided in the graph of FIG. 10, which shows the voltage waveform at node 86. A threshold for overstress is shown as the horizontal line at 3.0V. As illustrated in the graph, the positive feedback latch of predriver 80 ensures that feedback node 86 recovers quickly, that there is no substantial overstress, and that |Vgs| and |Vgd| are each consistently kept below 1V.

(21) FIG. 11 shows an eye diagram of characteristic ISI curves for an output waveform from a predriver 80 according to the invention. The eye diagram results from an input data stream of pseudorandom data followed by a long stream of binary ones at 28 GS/s. In this particular embodiment, the predriver 80 was configured as a 5-stage, 2.0V-shifting predriver with a fanout of 2. By inspection of the eye width 110, it can be seen that the predriver exhibited very good ISI. That is, the eye width 110 is within about 1.75 ps or 5% of Tperiod, where Tperiod is approximately 35.0 ps.

(22) The chart below summarizes the advantages of a predriver according to the present invention over the performance issues inherent in the conventional solution that uses an AC-coupled buffer:

(23) TABLE-US-00001 Issue AC Coupled Buffer Predriver 80 Area large resistor required negligible Reliability start-up and long 1 pattern none show Vgs/Vgd overstress Performance error prone and ISI increases no degradation with different data patterns due to different patterns Support of increases complexity no issue lower data rates

(24) FIG. 12 shows a conceptual manufacturing diagram for further optimizing a high-speed DC-shifting predriver 120 according to another embodiment of the invention. The diagram provides a cross-sectional view of a layer of semiconductor substrate or CMOS chip fabricated so that the feedback node 86 is shielded on all sides by an input node 121 connected to the predriver input port. Shielding node 86 in this manner minimizes the parasitic capacitance C.sub.P2. With C.sub.P2 reduced so that C.sub.P2<<1%, C.sub.P2 increases to 10%, as compared to conventional metal-oxide-metal (MoM) capacitors, where CP2/CP1 is about 5%/5%. With the effect of C.sub.P2 so minimized, the size of C.sub.AC is limited by the voltage divider between C.sub.AC and the node 86 and by the output capacitance of the much smaller feedback inverter 89.

(25) FIG. 13 shows a block diagram illustrating one application for a high-speed DC-shifting predriver of the present invention. In this application, the predriver comprises an N-stage predriver array, used as a buffer stage for an H-bridge transmitter DAC driver used for PAM4 signal processing. A first such predriver array 131 is configured for driving an M-bit PMOS DAC 133, and a second such predriver array 132 is configured for driving an M-bit NMOS DAC 134. Both predriver arrays 131 and 132 are identical copies with deep N-wells to use separate predriver VSS from the substrate to GND. Timing is matched by using equally sized PMOS and NMOS DACs 133 and 134 having equal VDDVSS (V.sub.CORE) on the two predriver arrays.

(26) Additional information on the form and operation of the H-bridge transmitter DAC driver is provided in co-pending and U.S. Provisional Application 62/854,219 that is fully incorporated herein by reference.

(27) Exemplary embodiments of the invention have been disclosed in an illustrative style. Accordingly, the terminology employed throughout should be read in a non-limiting manner. Although minor modifications to the teachings herein will occur to those well versed in the art, it shall be understood that what is intended to be circumscribed within the scope of the patent warranted hereon are all such embodiments that reasonably fall within the scope of the advancement to the art hereby contributed, and that that scope shall not be restricted, except in light of the appended claims and their equivalents.