Methods and apparatus for online timing mismatch calibration for polar and segmented power amplifiers

Abstract

An apparatus and methods for timing mismatch in a power amplifier includes a segmented PA with two-path timing mismatch calibration to improve ACLR performance over different signal transitions, process, voltage and temperature (PVT) variations and device aging; a fast and efficient algorithm for measuring and calibrating the delay of two paths (signal path and control path); a signal magnitude variation detection circuit, such as flash ADC, with improved comparator's performance for RF signal processing and minimum delay. A method for choosing the threshold voltage of the magnitude variation detection circuit, according to status of the signals and orthogonal frequency-division multiplexing (OFDM) related standards; other critical blocks.

Claims

1. An apparatus for calibrating timing mismatch in a power amplifier, comprising: a segmented power amplifier (PA); a digital signal processor (DSP); and a delay controller connected to the digital signal processor (DSP) and configured to be driven by the digital signal processor (DSP) through an Enable signal, wherein the digital signal processor (DSP) is configured to measure and calibrate a delay between a signal path and a control path, wherein the digital signal processor (DSP) comprises: a signal processing encoder configured to process an input signal to produce a baseband signal (S.sub.BB) and a magnitude signal (S.sub.mag); a PA magnitude control connected to the signal processing encoder, wherein the PA magnitude control is configured to use the magnitude signal (S.sub.mag) to generate a PA reference signal (S.sub.PA_Ref), and wherein the PA magnitude control is configured to generate the Enable signal to the delay controller when variation in magnitudes of the input signal exceeds a threshold voltage; a signal conditioning circuit connected to the signal processing encoder and the PA magnitude control, wherein the signal conditioning circuit is configured to condition the baseband signal (S.sub.BB), based on the PA reference signal (S.sub.PA_Ref), to produce a pre-distorted baseband signal (S.sub.BB_PD); a programmable delay element connected to the PA magnitude control; and a delay tuning circuit connected to the programmable delay element for controlling the programmable delay element to generate a PA retiming signal (S.sub.PA_Retimed).

2. The apparatus for calibrating timing mismatch in a power amplifier according to claim 1, wherein the delay controller comprises a waveform detector and a delay counter.

3. The apparatus for calibrating timing mismatch in a power amplifier according to claim 2, wherein the waveform detector comprises a voltage buffer, an RF ADC, an inverter, and a transient detector.

4. The apparatus for calibrating timing mismatch in a power amplifier according to claim 3, wherein the waveform detector comprises a voltage buffer, a radiofrequency analog-to-digital converter (RF ADC), an inverter, and a transient detector.

5. The apparatus for calibrating timing mismatch in a power amplifier according to claim 4, wherein the RF ADC comprises a flash ADC that comprises a voltage ladder and a set of comparators.

6. The apparatus for calibrating timing mismatch in a power amplifier according to claim 4, wherein the transient detector is a D Flip-Flop base transient detector.

7. A method for calibrating timing mismatch in a power amplifier using the apparatus according to claim 1, comprising: processing, using the signal processing encoder, the input signal to produce the baseband signal (S.sub.BB) and the magnitude signal (S.sub.mag); producing the PA reference signal (S.sub.PA_Ref) by the PA magnitude control; choosing the threshold voltage for the variation in the magnitudes of the input signal; generating the Enable signal to the delay controller when the variation in the magnitudes of the input signal exceeds the threshold voltage; generating a delay tuning signal from the delay controller to the programmable delay element; and generating the PA retiming signal (S.sub.PA_Retimed) by the programmable delay element to minimize time mismatch between the signal path and the control path.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows system level blocks illustrating an example of a complete power amplifier (PA) with delay detection and digital signal processor (DSP) in accordance with embodiments of the invention.

(2) FIG. 2 shows a simplified system level diagram corresponding to the detailed System from FIG. 1.

(3) FIG. 3 shows a 4-Level baseband signal conditioning by DSP. Signal conditions for enabling the calibration engine; the pre-distorted signal is measured at the input of the switchable driver.

(4) FIG. 4 shows a 7-Level baseband signal triggers Enable through high-to-low transition.

(5) FIG. 5 shows an example of a signal at the switchable driver, indicating the jump and a threshold voltage needed for jump detection.

(6) FIG. 6 shows details of an exemplary delay controller in accordance with one embodiment of the invention.

(7) FIG. 7 shows an example of delay counter implementation in accordance with one embodiment of the invention.

(8) FIG. 8 shows signal at the switchable driver, indicating the jump and multiple threshold voltages in accordance with one embodiment of the invention.

(9) FIG. 9 shows details of a waveform detector in accordance with one embodiment of the invention.

(10) FIG. 10 shows a schematic illustrating a voltage buffer in accordance with one embodiment of the invention.

(11) FIG. 11 shows a schematic illustrating an RF ADC in accordance with one embodiment of the invention.

(12) FIG. 12 shows a schematic illustrating a fast comparator in accordance with one embodiment of the invention.

(13) FIG. 13 shows a schematic illustrating a D Flip-flop based transient detector in accordance with one embodiment of the invention.

(14) FIG. 14 shows simulation results of input signal present at the input of the switchable drivers, illustrating at 2 s, the input signal transitions and generates a jump. The signal has been amplified by an extra amplifier to increase the system sensitivity. The horizontal V.sub.2P, V.sub.3P, and V.sub.4P lines show three threshold voltages used in the flash ADC for the signal jump detection.

(15) FIG. 15 shows an example, in which the comparator positioned in the middle level (V.sub.3D) is the only one that toggles while the other two comparators (V.sub.2D and V.sub.4D) stay in their original levels.

(16) FIG. 16 shows an example, in which the toggling is detected by the D-flip-flops, and then the control signal (Q3 curve) is generated and may be used to stop the comparator.

DETAILED DESCRIPTION

(17) Embodiments of the invention relate to apparatus and methods for efficient and accurate timing calibrations in multi-path power amplifiers (PAs). The timing calibration schemes of the invention can be applied to any multi-path power amplifiers, such as polar power amplifiers (PA) and linear segmented RF power amplifiers. FIG. 2 shows a simplified block diagram of a direct converter transmitter 100 that can be calibrated with methods of the invention, and FIG. 1 shows another diagram of this transmitter with the components in the digital signal processor illustrated.

(18) FIG. 1 shows a top-level architecture of a digitally assisted reconfigurable linear segmented PA 100 with an innovative timing mismatch calibration in accordance with one embodiment of the invention. The configuration of the PA sections is digitally controlled depending on the magnitude of the input signal, i.e., if more power is needed to deliver to the antenna, more segments in the segmented PA 105 may be turned on by the switchable driver 104. The signal conditioning block 113 will always know how many segments in the segmented PA 105 have been activated through S.sub.PA_REF, and it tunes the digital gain of S.sub.BB to generate S.sub.BB_PD.

(19) The power consumption of the PA is correlated with the power delivered to the antenna. Without calibration, there may be a timing mismatch between the PA section control path (signal processing encoder 112, PA magnitude block 114, programmable delay element 116) and the RF signal path (signal processing encoder 112, signal conditioning block 113, DAC 117, frequency modulator 118, LNA 102, PGA 103). In accordance with embodiments of the invention, novel building blocks are developed to form a novel and efficient timing mismatch calibration architecture. The key blocks in this calibration architecture include a delay controller 106 and a programmable delay element 116.

(20) The programmable delay element 116 may be realized digitally inside the DSP 101. The delay is matched to the one experienced by the signal applied to the switchable drivers V.sub.SD such that the PA section's control signal is aligned with the input RF signal. The delay controller 106 tunes the programmable delay element 116 through a delay tuning signal 115, which is an output of the delay controller 106. The architecture works as follows: the PA magnitude block 114 manages the magnitude variations of the input signals and generates the PA segmentation control signals for signal pre-warping, and the PA magnitude block 114 also synchronizes the signals using the signal conditioning block 113 such that S.sub.PA_REF is time aligned with the pre-distorted S.sub.BB_PD signal.

(21) This pre-distorted signal S.sub.BB_PD travels through the DAC 117, the frequency modulator 118, low noise amplifier (LNA) 102, and programmable gain amplifier (PGA) 103, and finally reaches the input (V.sub.SD) of the switchable drivers 104. It is necessary that the PA control signals be aligned with the V.sub.SD signal to reconstruct the original signals and hence reduce the spectral leakage into adjacent channels. Through calculation and tests, to satisfy the standards that demand adjacent channel leakage ratio (ACLR) to be below 40 dB, it is necessary to keep the timing mismatch below 500 sec.

(22) The PA magnitude block 114 also generates the Enable signal, which enables the calibration when a large enough variation occurs on the input signal (e.g., exceeding a threshold). This type of large signal variation facilitates the design of the timing calibration system and increases its robustness. When the delay controller 106 is enabled by the Enable signal, it measures the time delay experienced by S.sub.BB_PD signal at the input (V.sub.SD) of the switchable drivers 104. A high accuracy reference clock and a digital control loop may be used for this purpose. Once this delay is estimated, the programmable delay element 116 is adjusted to match the measured delay and generates S.sub.PA_retimed.

(23) In accordance with embodiments of the invention, a design of the delay controller 106 may be as follows:

(24) The appropriate time to enable the calibration algorithm is when the input signal amplitude crosses from region N to region N1 (signal amplitude reduces), as illustrated in FIG. 3. In this case, the pre-warped (pre-distorted) signal, S.sub.BB_PD, experiences a large low-to-high voltage variation due to increased digital gain of baseband signal, S.sub.BB. FIG. 3 shows the change of S.sub.BB_PD due to S.sub.BB changing from region 2 to region 1, which leads to a sharp transition of S.sub.BB_PD.

(25) When the baseband signal S.sub.BB crosses the boundary between region 2 and region 1, the digital gain suddenly changes from 4 to 8; hence, a large positive step variation in S.sub.BB_PD appears. The signal V.sub.SD measured at the input of the switchable driver varies by 50% of the full scale in the case of 4 segments, and around 30% of the full scale in the case of 7 segments. This signal variation is large enough to be detected by the delay controller 106. In the case of the 7 segments, the best conditions for re-calibration are illustrated in FIG. 4 for one of the segments.

(26) FIG. 4 shows a 7-Level baseband signal triggers Enable through high-to-low transition. The grey dotted lines in FIG. 4 indicate the segment boundaries. The arrows indicate the change direction of the signal at the input V.sub.in (X-axis) and the change in direction of the output voltage V.sub.out (Y-axis) after signal pre-warping. More transitions happen for the least-significant-bits (LSBs) than for the most-significant-bits (MSBs) due to the nature of the typical orthogonal frequency-division multiplexing (OFDM) signals usually with 6 to 12 dB peak-to-average ratio. Therefore, signal transitions in multiple segments can be used for the calibration algorithm. Through the Enable flag signal shown in FIG. 1, a smart algorithm for deciding when the calibration process is enabled can be implemented.

(27) Assuming the conditions for the timing mismatch calibration are identified in the digital signal processor (DSP 101), and assuming the enable signal indicates when the engine should measure the timing error, the following exemplary implementation of the timing calibration scheme is proposed. One skilled in the art would appreciate that this example is for illustration only and that other modifications and variations are possible without departing from the scope of the invention.

(28) FIG. 5 shows an example of a signal at the switchable driver, indicating the jump and a threshold voltage needed for jump detection, i.e., a moment suitable for starting the calibration. Every transition between segments can be used for timing calibration. Because the amplifier's gain is well-controlled, a proper and robust reference voltage and a very fast threshold level detector are required.

(29) For the case in which the magnitude of the input signal (before the segmentation process) decreases and moves from one segment to the next, the digital conditioning signal suddenly increases and reaches the full-scale value at that moment. The Enable signal is generated and alerts the calibration scheme that a signal transition suitable for timing mismatch calibration is imminent. At the moment when the incoming signal crosses the segmentation threshold, the signal conditioning increases the digital gain to the next level, and the signal jump is then perceptible at input of the switchable drivers. At this moment, the jump is detected, and the signal delay is measured by comparing the moment of the jump at the V.sub.SD node and the moment when the Enable signal rises. The purpose of the Enable signal is to serve as a flag for calibration as well as the reference signal for measuring the timing offset. A fast threshold detector may be used to detect the jump at V.sub.SD.

(30) As noted above with reference to FIG. 1, a delay controller (shown as 106 in FIG. 1) is used to control the delays. FIG. 6 shows details of an example of a delay controller 200, which includes a waveform detector 201 and a delay counter 202. The waveform detector 201 continuously monitors variations of V.sub.SD (here in a differential form V.sub.SD+ and V.sub.SD). The delay counter 202 counts the delay after the Enable signal. After the transient, detectors get reset by the Enable signal. When waveform detector 201 detects the desired V.sub.SD jump, it issues a Stop signal to stop the delay counter 202 from counting. In this way, the desired delay of S.sub.BB_PD to V.sub.SD is measured and recorder by the delay counter 202. The delay counter 202 generates relevant delay tuning signals to the DSP 101.

(31) In accordance with embodiments of the invention, the delay counter 202 may operate as follows:

(32) If the enable signal is 0, the output of the transient detectors 213 (stop signal) is unchanged as 0. That indicates the signal is not crossing different digital gain regions, and the calibration circuits is dormant. This action keeps the programmable delay invariant. When the Enable signal is activated, the amplitude of the input signal is compared with the threshold voltages in the RF ADC 212. If the differential signal is higher than the differential reference voltages, a close to rail-to-rail digital swing could be generated at input transient detectors. One or multiple outputs of the transient detectors 213 change to a 1.

(33) Once the output of transient detectors 213 (stop signal) changes to a 1, it stays at that level until the Enable signal goes low and tells the DSP to stop counting. A counter inside the DSP 101 is started by the Enable signal and it stops when the outputs of the transient detector 213 are activated. Before the comparison starts, the counter is reset with the Enable signal itself. The circuit shown in FIG. 7 displays an exemplary implementation of this scheme, which is fundamentally a time to digital converter (TDC). The counter counts the number of clock cycles within the time period from Enable to Stop. This value (delay time) is reported to the DSP 101 to generate a proper compensation delay through the programmable delay element 116 shown in FIG. 1.

(34) Notice in this system that the resolution of the counter-based system is dictated by the period of the clock. More sophisticated time-to-digital converter schemes can be used to improve this resolution.

(35) The robustness of the calibration scheme increases if instead of employing a single comparator, multiple (e.g., a set of 4 or 5) comparators with different threshold voltages are used as illustrated in FIG. 8. The range of coverage increases in this way and the circuit behaves more likely a flash ADC.

(36) The use of multiple comparators facilitates a more precise determination of when to update the programmable delay element 116. More comparators with different levels allow better transitions. However, the loading due to multiple comparators may limit the speed of the comparators.

(37) FIG. 9 shows details of the parts in a waveform detector (shown as 201 in FIG. 6). As shown in FIG. 9, the waveform detection block 300 mainly consists of four parts, a voltage buffer 211, an RF ADC 212, an inverter, and a transient detector 213.

(38) The voltage buffer 211 may be realized through an AC-coupled single stage amplifier. One example of a voltage buffer is illustrated in FIG. 10. The gain (gm*R1) of the voltage buffer 211, for example, may be calibrated to be close to 2. The gm is the transconductance of transistors M1.

(39) The RF ADC 212 compares the amplified signal of V.sub.SD as V.sub.O+ and V.sub.O with reference voltages. When the V.sub.O+ and V.sub.O keep moving below or above the reference voltages, the RF ADC 212 is fast enough to amplify the signal and generate a clock-like signal toggling between 0 and 1 at its output.

(40) Any suitable implementations for RF ADC (e.g., flash ADC) known in the art may be used with embodiments of the invention. FIG. 11 shows one exemplary implementation of an RF ADC 400, using a flash ADC that employs a voltage ladder and a set of fast comparators 401. As shown in FIG. 11, positive and negative reference voltages, such as V.sub.IP and V.sub.IN, are generated from resistive voltage division networks, and the fast comparators 401 compare the differential input V.sub.O+ and V.sub.O with two reference voltages V.sub.P and V.sub.N, respectively. Here, the signals are processed continuously, and the comparators are able to toggle between GND and VDD for the case when inputs V.sub.O+ and V.sub.O are crossing the reference voltage continuously.

(41) A fast comparator 401 in FIG. 11 may be implemented with any suitable scheme, such as that shown in FIG. 12. In this example, V.sub.O+ and V.sub.O are compared with reference voltages V.sub.P and V.sub.N. The current reuse topology in FIG. 12, with NMOS and PMOS used simultaneously, benefits the targeted fast toggling with two reasons: (1) In comparison with conventional NMOS only input, NMOS and PMOS input increases driving strength; and (2) The M.sub.2NI and M.sub.2NF are loaded by M.sub.2PF and M.sub.2PI instead of M.sub.IP, which generates a symmetric structure of NMOS and PMOS transistors with similar transconductances and the targeted fast toggling is more symmetrical for output above or below half of V.sub.DD. This comparator is sufficiently fast to detect fast signals (e.g., up to >6 GHz). V.sub.CL and V.sub.CH are processed and combined by digital logic as the outputs of comparator 401. This comparator is especially suitable for low power supply applications.

(42) Any suitable transient detector circuits known in the art may be used with embodiments of the invention. An exemplary implementation of D Flip-Flop base transient detector 213 is shown in FIG. 13. A 0 Enable signal will reset the output to be 0. When the enable signal is 1, the flip-flops output will change and keep at 1 if a clock signal can be applied. The clock signal comes from the output of the fast comparator 401, which indicates whether the signal is above, equal to (crossing), or below the threshold voltages.

(43) Simulations of this timing mismatch calibration scheme have been performed to validate the scheme. The results are shown in FIGS. 14-16. The names of the signals correspond to the wire names in FIG. 13.

(44) In FIG. 14, the curve (V.sub.O+) shows the input signal present at the input of the switchable drivers. At 2 s, the input signal transitions and generates a jump. The signal has been amplified by an extra amplifier to increase the system sensitivity. The horizontal V.sub.2P, V.sub.3P, and V.sub.4P lines show three threshold voltages used in the flash ADC for the signal jump detection. The system has 5 levels in total, with small spacing as shown in FIG. 8.

(45) In FIG. 15, the comparator positioned in the middle level (V.sub.3D) is the only one that toggles while the other two comparators (V.sub.2D and V.sub.4D) stay in their original levels.

(46) In FIG. 16, the toggling is detected by the D-flip-flops in 213, and then the control signal (Q3 curve) is generated and used to stop the comparator.

(47) Embodiments of the invention have been described with reference to a limited number of examples. One skilled in the art would appreciate that these examples are for illustration only and are not meant to limit the scope of the invention. Instead, the scope of the invention should only be limited by the attached claims.

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