Fifty percent duty cycle detector and method thereof

Abstract

A fifty percent duty cycle detector includes a single-ended-to-differential converter (S2D) configured to receive a first clock and output a second clock and a third clock that are complementary; a controllable swap circuit configured to receive the second clock and the third clock and output a fourth clock and a fifth clock in accordance with a logical control signal; a time-to-digital converter (TDC) configured to receive the fourth clock and the fifth clock and output a digital word; and a finite state machine configured to receive the digital word and output the logical control signal and a ternary decision.

Claims

1. A fifty percent duty cycle detector comprising: a single-ended-to-differential converter (S2D) configured to receive a first clock and output a second clock and a third clock that are complementary; a controllable swap circuit configured to receive the second clock and the third clock and output a fourth clock and a fifth clock in accordance with a logical control signal; a time-to-digital converter (TDC) configured to receive the fourth clock and the fifth clock and output a digital word; and a finite state machine (FSM) configured to receive the digital word and output the logical control signal and a ternary decision.

2. The fifty percent duty cycle detector of claim 1, wherein the digital word represents a timing difference between a rising edge of the fourth clock and a subsequent rising edge of the fifth clock.

3. The fifty percent duty cycle detector of claim 1, wherein the TDC is an all-digital circuit that comprises a plurality of inverters, logic gates, and flip-flops.

4. The fifty percent duty cycle detector of claim 1, wherein: the controllable swap circuit assigns the second clock and the third clock to be the fourth clock and the fifth clock, respectively, when the logical control signal is in a first state, and assigns the second clock and the third clock to be the fifth clock and the fourth clock, respectively, when the logical control signal is in a second state.

5. The fifty percent duty cycle detector of claim 4, wherein the FSM first sets the logical control signal to the first state and obtains a first value of the digital word, then sets the logical control signal to the second state and obtains a second value of the digital word, and then determines a value of the ternary decision in accordance with a comparison between the first value and the second value of the digital word.

6. A method of fifty percent duty cycle detection comprising: receiving a first clock; converting the first clock into a second clock and a third clock using a single-ended-to-differential converter (S2D); assigning the second clock and the third clock to be a fourth clock and a fifth clock, respectively, and obtaining a first digital word by performing a first time-to-digital conversion that detects a timing difference between the fourth clock and the fifth clock; assigning the third clock and the second clock to be the fourth clock and the fifth clock, respectively, and obtaining a second digital word by performing a second time-to-digital conversion that detects a timing difference between the fourth clock and the fifth clock; and making a ternary decision based on comparing the first digital word and the second digital word.

7. The method of fifty percent duty cycle detection of claim 6, wherein performing a first time-to-digital conversion and a second time-to-digital conversion comprises using a time-to-digital converter that is an all-digital circuit that comprises a plurality of inverters, logic gates, and flip-flops.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows a schematic diagram of a prior art 50% duty cycle detector.

(2) FIG. 2 shows a schematic diagram of a 50% duty cycle detector in accordance with an embodiment of the present disclosure.

(3) FIG. 3 shows a schematic diagram of a single-ended-to-differential converter.

(4) FIG. 4 shows a schematic diagram of a controllable swap circuit.

(5) FIG. 5 shows an exemplary timing diagram of the 50% duty cycle detector of FIG. 2.

(6) FIG. 6 shows a flow diagram of a method of frequency doubling in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION OF THIS DISCLOSURE

(7) The present disclosure is directed to fifty percent duty cycle detection. While the specification describes several example embodiments of the disclosure considered favorable modes of practicing the invention, it should be understood that the invention can be implemented in many ways and is not limited to the particular examples described below or to the particular manner in which any features of such examples are implemented. In other instances, well-known details are not shown or described to avoid obscuring aspects of the disclosure.

(8) Persons of ordinary skill in the art understand terms and basic concepts related to microelectronics that are used in this disclosure, such as voltage, signal, single-ended, differential, finite state machine, CMOS (complementary metal oxide semiconductor), NMOS (n-channel metal oxide semiconductor), inverter, logic gates, flip-flops, digital circuit, switch, low-pass filter, and duty cycle. Terms like these are used in a context of microelectronics, and the associated concepts are apparent to those of ordinary skills in the art and thus will not be explained in detail here.

(9) Those of ordinary skill in the art will recognize basic symbols used herein, like a switch symbol and an inverter symbol. As well, artisans will understand the structure and operations of such devices.

(10) This present disclosure is disclosed in terms of an engineering sense (i.e., in a manner that recognizes that engineers are the target audience). For instance, regarding two variables X and Y, when it is said that X is equal to Y, it means that X is approximately equal to Y, i.e. a difference between X and Y is smaller than a specified engineering tolerance. When it is said that X is zero, it means that X is approximately zero, i.e. X is smaller than a specified engineering tolerance. When it is said that X is substantially smaller than Y, it means that X is negligible with respect to Y, i.e. a ratio between X and Y is smaller than an engineering tolerance and therefore X is negligible when compared to Y.

(11) In this present disclosure, a signal is a voltage of a variable level that can vary with time, or a digit with a value that can vary with time. When a signal is a voltage, it is called a voltage signal and a level of the signal at a moment represents a state of the signal at that moment. When a signal is a digital, it is called a digital signal, and a value of the signal at a moment represents a state of the signal at that moment.

(12) A logical signal is a voltage signal of two states: a low state and a high state. The low state is also referred to as a 0 state, while the high stage is also referred to as a 1 state. Regarding a logical signal Q, when we say, Q is high or Q is low, what we mean is Q is in the high state or Q is in the low state. Likewise, when we say, Q is 1 or Q is 0, what we mean is Q is in the 1 state or Q is in the 0 state.

(13) A ternary signal is a voltage signal of three states: a 1 state, a 0 state, and a 1 state.

(14) When a logical signal toggles from low to high, it undergoes a low-to-high transition and exhibits a rising edge. When a logical signal toggles from high to low, it undergoes a high-to-low transition and exhibits a falling edge.

(15) A switch is controlled by a logical control signal, and the switch is approximately a short circuit and is said to be turned on when said logical control signal is high (i.e. 1); and said switch is approximately an open circuit and said to be turned off when said logical control signal is low (i.e. 0).

(16) A first logical signal is said to be a logical inversion of a second logical signal, if the first logical signal and the second logical signal are always in opposite states. That is, when the first logical signal is low (i.e. 0), the second logical signal is high (i.e. 1); when the first logical signal is high (i.e. 1), the second logical signal is low (i.e. 0). When a first logical signal is said to be a logical inversion of a second logical signal, the first logical signal and the second logical signal are said to be complementary to each other.

(17) An inverter receives a first logical signal and outputs a second logical signal such that the second logical signal is a logical inversion of the first signal.

(18) A digital word is a digital signal of an integer value that can be embodied by a collection of a plurality of logical signals in accordance with a certain encoding scheme.

(19) A circuit is a collection of a transistor, a resistor, and/or other electronic devices inter-connected in a certain manner to embody a certain function.

(20) A schematic diagram of a 50% duty cycle detector 200 in accordance with an embodiment of the present disclosure is shown in FIG. 2. 50% duty cycle detector 200 comprises: a single-ended-to-differential converter (S2D) 210 configured to receive a first clock C.sub.1 and output a second clock C.sub.2 and a third clock C.sub.3, wherein the second clock C.sub.2 and the third clock C.sub.3 are complementary; a controllable swap circuit 220 configured to receive the second clock C.sub.2 and the third clock C.sub.3 and output a fourth clock C.sub.4 and a fifth clock C.sub.5 in accordance with a logical control signal C.sub.x; a time-to-digital converter (TDC) 230 configured to receive the fourth clock C.sub.4 and the fifth clock C.sub.5 and output a digital word D.sub.w that quantifies a timing difference between a rising edge of the fourth clock C.sub.4 and a subsequent rising edge of the fifth clock C.sub.5; and a finite state machine (FSM) 240 configured to receive the digital word D.sub.w and output the logical control signal C.sub.x and a ternary decision D.sub.o indicating a duty cycle of the first clock C.sub.1 is smaller than 50%, or equal to 50%, or greater than 50%. For brevity, hereafter the first (second, third, fourth, fifth) clock C.sub.1 (C.sub.2, C.sub.3, C.sub.4, C.sub.5) is simply referred to as C.sub.1 (C.sub.2, C.sub.3, C.sub.4, C.sub.5); the digital word D.sub.w is simply referred to as D.sub.w; the logical control signal C.sub.x is simply referred to as C.sub.x; and the ternary decision D.sub.o is simply referred to as D.sub.o.

(21) A schematic diagram of a single-ended-to-differential converter (S2D) 300 that can be used to embody the S2D 210 is shown in FIG. 3. S2D 300 comprises inverters 310, 320, 330, 340, and 350. Inverters 310 and 320 are cascaded to form a non-inverting buffer configured to receive C.sub.1 and output C.sub.2 so that C.sub.2 is substantially the same as C.sub.1. Inverter 330 forms an inverting buffer so that C.sub.3 is substantially a logical inversion of C.sub.1. Inverters 340 and 350 form a cross-coupling pair to ensure C.sub.2 and C.sub.3 are a logical inversion of each other. S2D 300 is well known in the prior art and thus no further explanation is needed. Since C.sub.2 is substantially the same as C.sub.1, a duty cycle of C.sub.2 is substantially the same as a duty cycle of C.sub.1. Hence, detecting a duty cycle of C.sub.2 is substantially equivalent to detecting a duty cycle of C.sub.1. From an engineering viewpoint, C.sub.2 can be said to be the same as C.sub.1, while C.sub.3 can be said to be the same as a logical inversion of C.sub.1.

(22) A schematic diagram of a controllable swap circuit 400 that can be used to embody the controllable swap circuit 220 is shown in FIG. 4. Controllable swap circuit 400 comprises four switches 410, 420, 430, and 440 controlled by C.sub.x, C.sub.x, C.sub.x, and C.sub.x, respectively, wherein C.sub.x is a logical inversion of C.sub.x. When C.sub.x is 0 and thus C.sub.x is 1, switches 410 and 440 are turned on while switches 420 and 430 are turned off, causing C.sub.4 to be equal to C.sub.2 and C.sub.5 to be equal to C.sub.3; this is a straight connection scenario and no swapping takes place. When C.sub.x is 1 and thus C.sub.x is 0, switches 410 and 440 are turned off while switches 420 and 430 are turned on, causing C.sub.4 to be equal to C.sub.3 and C.sub.5 to be equal to C.sub.2; this is a cross connection scenario and a swapping takes place. A controllable swap function is thus fulfilled.

(23) An exemplary timing diagram of the 50% duty cycle detector 200 is shown in FIG. 5. Let a period of C.sub.1 be T. Let a pulse width of C.sub.1 be T.sub.w. C.sub.2 is the same as C.sub.1, C.sub.3 is a logical inversion of C.sub.2, and thus both C.sub.2 and C.sub.3 have the same period T. A pulse width of C.sub.2 is T.sub.w, while a pulse width of C.sub.3 is TT.sub.w. A duty cycle of C.sub.2 is T.sub.w/T100%. A duty cycle of C.sub.3 is (1T.sub.w/T)100%. When C.sub.x is 0, rising edge 511 of C.sub.2 leads to rising edge 512 of C.sub.4 at time t.sub.a, rising edge 521 of C.sub.3 leads to rising edge 522 of C.sub.5 at time t.sub.b, and rising edge 531 of C.sub.2 leads to rising edge 532 of C.sub.4 at time t.sub.c. When C.sub.x is 1, rising edge 511 of C.sub.2 leads to rising edge 513 of C.sub.5 at time t.sub.a, rising edge 521 of C.sub.3 leads to rising edge 523 of C.sub.4 at time t.sub.b, and rising edge 531 of C.sub.2 leads to rising edge 533 of C.sub.5 at time t.sub.c.

(24) TDC 230 detects a timing difference between a rising edge of C.sub.4 and a subsequent rising edge of C.sub.5 (i.e. a distance between t.sub.a and t.sub.b when C.sub.x is 0, and a distance between t.sub.b and t.sub.c when C.sub.x is 1) and represents the timing difference by D.sub.w; a larger value of D.sub.w indicates a greater timing difference between the rising edge of C.sub.4 and the subsequent rising edge of C.sub.5. When C.sub.x is 0, C.sub.4 is the same as C.sub.2 and C.sub.5 is the same as C.sub.3; in this case, D.sub.w has a first value, say D.sub.w0, that effectively represents T.sub.w, i.e. a timing difference between a rising edge of C.sub.2 and a subsequent rising edge of C.sub.3; for instance, a timing difference between rising edge 511 of C.sub.2 and rising edge 521 of C.sub.3. When C.sub.x is 1, C.sub.4 is the same as C.sub.3 and C.sub.5 is the same as C.sub.2; in this case, D.sub.w has a second value, say D.sub.w1, that effectively represents TT.sub.w, i.e. a timing difference between a rising edge of C.sub.3 and a subsequent rising edge of C.sub.2; for instance, a timing difference between rising edge 521 of C.sub.3 and rising edge 531 of C.sub.2. When D.sub.w0 is greater (smaller) than D.sub.w1, it indicates T.sub.w is greater (smaller) than TT.sub.w, and therefore a duty cycle of C.sub.2 is greater (smaller) than 50%. When D.sub.w0 is equal to D.sub.w1, it indicates C.sub.2 has a 50% duty cycle.

(25) FSM 240 first sets C.sub.x to 0 and obtains D.sub.w0; then it sets C.sub.x to 1 and obtains D.sub.w1; then it determines a value of D.sub.o in accordance with a comparison between D.sub.w0 and D.sub.w1: D.sub.o is 1 if D.sub.w0 is smaller than D.sub.w1; D.sub.o is 0 if D.sub.w0 is equal to D.sub.w1; and D.sub.o is 1 if D.sub.w0 is greater than D.sub.w1.

(26) Time-to-digital converters are well known in the prior art and thus not described in detail here. Any time-to-digital converter circuit known in the prior art can be used to embody TDC 230 at the discretion of circuit designer. A distinct feature of using TDC 230 in the 50% duty cycle detector 200 is: as long as TDC 230 is monotonic (i.e., a larger time difference between a rising edge of C.sub.4 and a subsequent rising edge of C.sub.5 will lead to a larger value or at least the same value of D.sub.w), a linearity of TDC 230 is unimportant because whatever impairment due to nonlinearity will affect both the value of D.sub.w0 and the value of D.sub.w1, and the impairment will be offset since we're interested only in the relative difference between D.sub.w0 and D.sub.w1. Many known TDC are directed to achieving a high linearity at the cost of large layout area and power consumption. The 50% duty cycle detector 200 doesn't have high linearity requirement for TDC 230, and therefore it can allow an efficient design. In an embodiment, TDC 230 is an all-digital TDC that comprises a plurality of inverters, logic gates, and flip-flops that are purely digital circuits. All-digital TDC is known in the prior art and thus not described in detail here.

(27) The 50% duty cycle detector 200 needs to take only six cycles of C.sub.1 (one cycle to set C.sub.x to 0, two cycle to obtain D.sub.w0, one cycle to set C.sub.x to 1, and two cycles to obtain D.sub.w1) to obtain a value of D.sub.o, therefore it is very fast. For instance, if C.sub.1 is a 40 MHz clock, a clock period is 25 ns, it takes merely 150 ns to obtain D.sub.o.

(28) The 50% duty cycle detector 200 can be an all-digital circuit design that uses logic gates exclusively and is highly area efficient using a modern complementary metal oxide semiconductor (CMOS) process.

(29) As demonstrated by a flow chart 600 shown in FIG. 6, a method of 50% duty cycle detection in accordance with an embodiment of the present disclosure comprises: (step 610) receiving a first clock; (step 620) converting the first clock into a second clock and a third clock that are complementary using a single-ended-to-differential converter (S2D); (step 630) assigning the second clock and the third clock to be a fourth clock and a fifth clock, respectively, and obtaining a first digital word by performing a first time-to-digital conversion that detects a timing difference between the fourth clock and the fifth clock; (step 640) assigning the third clock and the second clock to be the fourth clock and the fifth clock, respectively, and obtaining a second digital word by performing a second time-to-digital conversion that detects a timing difference between the fourth clock and the fifth clock; and (step 650) making a ternary decision based on comparing the first digital word and the second digital word.

(30) Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the disclosure. Accordingly, the above disclosure should not be construed as limited only by the metes and bounds of the appended claims.