SYSTEMS AND METHODS FOR ASSEMBLING PROCESSOR SYSTEMS

Abstract

This disclosure generally relates to processor systems comprising printed circuit boards, I/O chips and processor chips with mated contacts. Contacts are formed on an upper surface of a printed circuit board having a through-hole and on a processor chip inside the through-hole. The processor chip may be a superconducting quantum processor chip comprising qubits, couplers, Digital to Analog converters, QFP shift registers and analog lines. Contacts are formed on an upper surface on an I/O chip and mated with the contacts on the printed circuit board and the processor chip. Contacts may be Indium bump bonds or superconducting solder bonds. The processor chip and the I/O chip may include a shield layer, a substrate layer and a thermally conductive layer.

Claims

1. A processor system comprising: a processor chip, the processor chip having a major face, a perimeter which bounds the major face of the processor chip and that has a set of dimensions, and a plurality of contacts, the contacts of the processor chip distributed along the perimeter of the processor chip; a printed circuit board, the printed circuit board having a through-hole and a plurality of contacts, the through-hole having a perimeter with a set of dimensions, the dimensions of the through-hole larger than corresponding dimensions of the processor chip to receive the processor chip at least partially by the through-hole, the contacts of the printed circuit board distributed about the perimeter of the through-hole; and an input/output (I/O) chip, the I/O chip having a major face, a perimeter which bounds the major face of the I/O chip and that has a set of dimensions that are larger than corresponding dimensions of the through-hole of the printed circuit board, a first plurality of contacts, and a second plurality of contacts, the first plurality of contacts of the I/O chip distributed along the perimeter of the I/O chip, the second plurality of contacts distributed along the perimeter of the I/O chip spaced inwardly from the first plurality of contacts with respect to the perimeter of the I/O chip, at least a portion of the major face of the I/O chip covering at least a portion of the major face of the processor chip and at least a portion of the major face of the I/O chip covering at least a portion of the major face of the printed circuit board, the first plurality of contacts of the I/O chip positioned to mate with the plurality of contacts of the printed circuit board, and the second plurality of contacts of the I/O chip positioned to mate with the plurality of contacts of the processor chip.

2. The processor system of claim 1 wherein the plurality of contacts of the processor chip, the plurality of contacts of the printed circuit board and the first and the second plurality of contacts of the I/O chip are at least one of: Indium bump bonds and superconducting solder bonds.

3. The processor system of claim 1 wherein the processor chip is a superconducting processor chip including a plurality of qubits, couplers, Digital to Analog Converters, QFP shift registers and analog lines; and the I/O chip includes Digital to Analog Converters, frequency-multiplexed resonant (FMR) read-in, frequency-multiplexed resonant (FMR) readout, microwave and analog lines.

4. The processor system of claim 1 wherein the I/O chip further comprises: a shield layer below the first and the second plurality of contacts, the shield layer comprising a material with high critical temperature relative to a material comprising the processor chip, the shield layer pierced by superconducting vias leading to the first and the second plurality of contacts; and a substrate layer having a first surface that covers a second surface of the I/O chip, the second surface of the I/O chip opposed to the first surface of the I/O chip across a thickness of the I/O chip.

5. (canceled)

6. (canceled)

7. The processor system of claim 4 wherein the I/O chip further comprises a thermally conductive layer that covers a second surface of the substrate layer, the second surface of the substrate layer opposed to the first surface of the substrate layer across a thickness of the substrate layer.

8. (canceled)

9. (canceled)

10. The processor system of claim 4 wherein the first and the second plurality of contacts of the I/O chip are located in the shield layer.

11. The processor system of claim 1 wherein the processor chip further comprises a shield layer below the plurality of contacts of the processor chip, the shield layer comprising a first material with high critical temperature relative to a material comprising the processor chip, and a number of superconducting vias that through the shield layer to provide a communicatively coupling to the plurality of contacts of the processor chip.

12. The processor of claim 11 wherein the I/O chip further comprises an I/O shield layer that underlies the first and the second plurality of contacts, the I/O shield layer comprising a second material with high critical temperature relative to a material comprising the processor chip, and a number of superconducting vias through the I/O shield layer that provide a communicative coupling to the first and the second plurality of contacts of the processor chip, the first material different from the second material.

13. (canceled)

14. (canceled)

15. The processor system of claim 1 wherein the processor chip further comprises a substrate layer having a first surface that covers a second surface of the processor chip, the first surface of the substrate layer opposed to the first surface of the processor chip across a thickness of the processor chip.

16. The processor system of claim 15 wherein the processor chip further comprises a thermally conductive layer that covers a second surface of the substrate layer, the second surface of the substrate layer opposed to the first surface of the substrate layer across a thickness of the substrate layer.

17.-21. (canceled)

22. A method of fabricating a processor system, the processor system comprising: a processor chip; a printed circuit board, the printed circuit board having a through-hole with a perimeter that has dimensions that are larger than corresponding dimensions of a perimeter of the processor chip; and an input/output (I/O) chip, the I/O chip having a perimeter that has dimensions that are larger than corresponding dimensions of the through-hole of the printed circuit board, the method comprising: forming a plurality of contacts on, at, or recessed in a first surface of the processor chip that extend along a perimeter of the processor chip; forming a plurality of contacts distributed on, at, or recessed in a first surface of the printed circuit board that extend along the perimeter of the through-hole; forming a first plurality of contacts distributed on, at, or recessed in a first surface around a perimeter of the I/O chip, and a second plurality of contacts distributed on, at, or recessed in the first surface along the inside of the perimeter of the I/O chip; aligning the processor chip at least partially inside the through-hole of the printed circuit board; at least partially covering the first surface of the I/O chip with at least a portion of the first surface of the processor chip and with a least a portion of the first surface of the printed circuit board; and mating the first plurality of contacts on the I/O chip with the plurality of contacts on the printed circuit board and the second plurality of contacts on the I/O chip with the plurality of contacts on the processor chip.

23. The method of claim 22 wherein forming a plurality of contacts on, at, or recessed in a first surface of the processor chip, forming a plurality of contacts distributed on, at, or recessed in a first surface of the printed circuit board and forming a first plurality and a second plurality of contacts distributed on, at, or recessed in a first surface of the I/O chip includes forming a plurality of contacts on, at, or recessed in a first surface of the processor chip, forming a plurality of contacts distributed on, at, or recessed in a first surface of the printed circuit board and forming a first plurality and a second plurality of contacts distributed on, at, or recessed in a first surface of the I/O chip selected from a group comprising: Indium bump bonds and superconducting solder bonds.

24. The method of claim 22 wherein forming a plurality of contacts on, at, or recessed in a first surface of the processor chip includes forming a plurality of contacts on, at, or recessed in a first surface of a processor chip comprising a plurality of qubits, couplers, Digital to Analog Converters, QFP shift registers and analog lines; and forming a first plurality and a second plurality of contacts distributed on, at, or recessed in a first surface of the I/O chip includes forming a first plurality and a second plurality of contacts distributed on, at, or recessed in a first surface of a I/O chip comprising Digital to Analog Converters, frequency-multiplexed resonant (FMR) read-in, frequency-multiplexed resonant (FMR) readout, microwave and analog lines.

25. The method of claim 22 further comprising: forming an I/O shield layer below the first and the second plurality of contacts on the I/O chip, the shield layer comprising a material with high critical temperature relative to a material comprising the processor chip, the shield layer including a number of superconducting vias that provide a communicative path to the contacts; and forming an I/O substrate layer having a first surface covering a second surface of the I/O chip, the second surface of the I/O chip opposed to the first surface of the I/O chip across a thickness of the I/O chip.

26. (canceled)

27. (canceled)

28. The method of claim 25 further comprising: forming an I/O thermally conductive layer covering a second surface of the I/O substrate layer, the second surface of the I/O substrate layer opposed to the first surface of the I/O substrate layer across a thickness of the I/O substrate layer.

29. (canceled)

30. (canceled)

31. The method of claim 25 wherein forming a first and a second plurality of contacts distributed on, at, or recessed in a first surface of the PO chip includes forming a first, and a second plurality of contacts distributed on, at, or recessed in the I/O shield layer.

32. The method of claim 22 further comprising: forming a processor shield layer below the plurality of contacts on the processor chip, the shield layer comprising a first material with relatively high critical temperature relative to a material comprising the processor chip, the shield layer pierced by superconducting vias leading to the contacts.

33. The method of claim 32 further comprising forming an I/O shield layer below the first and the second plurality of contacts on the I/O chip, the I/O shield layer comprising a second material with high critical temperature relative to a material comprising the processor chip, and forming one or more superconducting vias that extend through the I/O shield layer to the first and second plurality of contacts, the first material different from the second material.

34. (canceled)

35. (canceled)

36. The method of claim 22 further comprising forming a processor substrate layer having a first surface covering a second surface of the processor chip, the second surface opposed to the first surface of the processor chip across a thickness of the processor chip.

37. The method of claim 36 further comprising forming a processor chip thermally conductive layer covering a second surface of the substrate layer, the second surface of the substrate layer opposed to the first surface of the substrate layer across a thickness of the substrate layer.

38.-43. (canceled)

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)

[0014] In the drawings, identical reference numbers identify similar elements or acts. The sizes and relative positions of elements in the drawings are not necessarily drawn to scale. For example, the shapes of various elements and angles are not necessarily drawn to scale, and some of these elements may be arbitrarily enlarged and positioned to improve drawing legibility. Further, the particular shapes of the elements as drawn, are not necessarily intended to convey any information regarding the actual shape of the particular elements, and may have been solely selected for ease of recognition in the drawings.

[0015] FIG. 1A is a plan view of an example layout of a printed circuit board comprising a plurality of contacts, according to the present disclosure.

[0016] FIG. 1B is a cross-sectional view of an example layout of an assembly comprising a plurality of contacts and a plurality of printed circuit boards.

[0017] FIG. 2A is a planar view of an example layout of an input/output (I/O) integrated circuit structure or chip comprising a plurality of contacts, according to the present disclosure.

[0018] FIG. 2B is a cross-sectional view of an example layout of an I/O integrated circuit structure or chip comprising a plurality of contacts, according to the present disclosure

[0019] FIG. 3A is a planar view of an example layout of an processor integrated circuit structure or chip comprising a plurality of contacts, according to the present disclosure.

[0020] FIG. 3B is a cross-sectional view of an example layout of a processor integrated circuit structure or chip comprising a plurality of contacts, according to the present disclosure.

[0021] FIG. 4 is a cross-sectional view of an example processor system showing the relative position of a printed circuit board, a processor chip and an I/O chip with mated pads.

[0022] FIG. 5 is a flow chart of an example method of assembling an I/O chip comprising a plurality of contacts, according to the present disclosure.

[0023] FIG. 6 is a flow chart of an example method of assembling a processor chip comprising a plurality of contacts, according to the present disclosure.

[0024] FIG. 7 is a flow chart of an example method assembling a processor system comprising a printed circuit board, a processor chip and an I/O chip, according to the present disclosure.

[0025] FIG. 8 is a schematic diagram illustrating an example arrangement frequency multiplex resonant (FMR) readout arrays in a superconducting processor.

[0026] FIG. 9 shows a schematic diagram of an example embodiment as a system that includes two superconducting qubits and a controllable coupler.

DETAILED DESCRIPTION

[0027] In the following description, certain specific details are set forth in order to provide a thorough understanding of various disclosed implementations. However, one skilled in the relevant art will recognize that implementations may be practiced without one or more of these specific details, or with other methods, components, materials, etc. In other instances, well-known structures associated with computer systems, server computers, and/or communications networks have not been shown or described in detail to avoid unnecessarily obscuring descriptions of the implementations.

[0028] Unless the context requires otherwise, throughout the specification and claims that follow, the word comprising is synonymous with including, and is inclusive or open-ended (i.e., does not exclude additional, unrecited elements or method acts).

[0029] Reference throughout this specification to one implementation or an implementation means that a particular feature, structure or characteristic described in connection with the implementation is included in at least one implementation. Thus, the appearances of the phrases in one implementation or in an implementation in various places throughout this specification are not necessarily all referring to the same implementation. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more implementations.

[0030] As used in this specification and the appended claims, the singular forms a, an, and the include plural referents unless the context clearly dictates otherwise. It should also be noted that the term or is generally employed in its sense including and/or unless the context clearly dictates otherwise.

[0031] The headings and Abstract of the Disclosure provided herein are for convenience only and do not interpret the scope or meaning of the implementations.

[0032] Generally, processors, including analog or quantum processors, are rectangular microchips which are wirebonded to printed circuit boards (PCBs). Where the processor is a superconducting quantum processor, the PCB is also a superconducting PCB. As the size of a processor, for example a quantum processor, increases, the number of input/output lines also increases, leading to increased complexity of assembly of the processor. For example, as the number of input/output lines increases, the complexity of the processor sample-holder also increases, leading to increased physical space requirement. In some implementations, for example where the processor is housed in an isolated environment (e.g., a cryogenic environment), increased physical space needs may become unpractical. Similarly, a larger number of input/output lines requires a larger number of electrical filtering, leading to growing physical space requirements and growing power requirements. Also, with an increased number of input/output lines, wirebonding becomes more difficult, potentially requiring more time and specialized technicians. For superconducting processors that operates at cryogenic temperatures, the probability that a wirebonding fails during cool-down also increases with an increased number of input/output lines, potentially causing expensive delays in testing and deployment of the processor. Therefore, there is the need to at least partially limiting penalties in hardware assembly when the complexity of a processor increases.

[0033] The present disclosure describes systems and methods of assembly of superconducting processors comprising a superconducting printed circuit board (PCB), an input/output (I/O) chip and a superconducting processor chip, collectively bonded though a plurality of contacts. In the present disclosure and the appended claims, the words contact and contacts are used to indicated bonding materials and structures used to assemble a PCB, input/output chip and a processor chip.

[0034] Contacts may, for example and without limitation, take the form of Indium bump bonds, superconducting solder bonds, or similar structures. A person skilled in the art will understand that chips featuring solder bonds may be mated through a reflow process, while Indium bonds (or bonds comprising another superconducting material that remain pliable through a wide range of temperatures) may be mated through a mechanical process (e.g., a press). In some implementations, a combination of bumps and pads may be used.

[0035] FIG. 1A is a plan view of an example layout 100a of a printed circuit board (PCB) 101 comprising a plurality of contacts, according to the present disclosure.

[0036] In some implementations, PCB 101 may be a superconducting PCB. In at least one implementation, PCB 101 is an assembly of multiple PCBs, as shown in FIG. 1B. PCB 101 comprises a through-hole 102, located approximately centered in PCB 101. Through-hole 102 has a size larger than a processor chip (not shown in FIG. 1A) and is able to accommodate a processor chip. PCB 101 comprises a plurality of contacts 103 (only one called out in FIG. 1A to reduce clutter) near a perimeter 104 of through-hole 102. Contacts 103 are distributed in a pattern similar to a pattern used on an outer ring of contacts on an I/O chip (not shown in FIG. 1A, see FIG. 2A). Contacts 103 may, for example and without limitation, take the form of Indium bump bonds, superconducting solder bonds, or similar structures. A person skilled in the art will understand that the number of contacts 103 shown in FIG. 1A is an example and on other implementations, a larger or smaller number of contacts 103 may be used. Similarly, the pattern of contacts 103 shown in FIG. 1A is an example, and in other implementations contacts 103 may be distributed in another pattern, similar to the pattern used on an outer ring of contacts on an I/O chip. Layout 100a of PCB 101 may be used in a processor assembly as shown in FIG. 4. Also shown in FIG. 1A is a cross-section line 150 for illustrative purpose to aid in the description of FIG. 1B and FIG. 4.

[0037] FIG. 1B is a cross-sectional view of an example assembly 100b comprising a plurality of contacts as described in FIG. 1A and a plurality of printed circuit boards (PCBs) 101-1 through 101-n (collectively, 101), taken along cross-section line 150 (not shown in FIG. 1B). PCB 101 has a through-hole 102, as described above with reference to FIG. 1A. In at least one implementation, each PCB 101-1 through 101-n is placed in the assembly of multiple PCBs so as to collectively define through-hole 102. Layout 100b of PCB 101 may be used in a processor assembly as shown in FIG. 4.

[0038] FIG. 2A is a planar view of an example layout 200 of an input/output (I/O) integrated circuit structure or chip 201 comprising a plurality of contacts, according to the present disclosure.

[0039] I/O chip 201 comprises I/O circuitry, including Digital to Analog Converters (DACs), frequency-multiplexed resonant (FMR) read-in, frequency-multiplexed resonant (FMR) readout, microwave and analog lines. I/O chip layout 200 comprises a first or outer ring of contacts 202 (only one contact 202 called out in FIG. 2A to reduce clutter) distributed in a pattern similar to the pattern of contacts 103 of PCB layout 100a of FIG. 1A or 100b of FIG. 1B. Contacts 202 may, for example and without limitation, take the form of Indium bump bonds, superconducting solder bonds, or similar structures. I/O chip 201 further comprises a second or inner ring of contacts 203 (only one contact 203 called out in FIG. 2A to reduce clutter) distributed in a pattern similar to the pattern used for contacts on a processor chip (not shown in FIG. 2A, see FIG. 3A). Contact 203 may, for example and without limitation, take the form of Indium bump bonds, superconducting solder bonds, or similar structures. A person skilled in the art will understand that the number of contacts 202 and 203 shown in FIG. 2A is an example and on other implementations, a larger or smaller number of contacts 202 and/or 203 may be used. Contacts 202 and contacts 203 are shown in FIG. 2A as having similar size to one another; however, this is an illustrative example and in other implementations, contacts 202 and contacts 203 may have different sizes from one another and may be comprised of different material from one another.

[0040] Similarly, the pattern of contacts 202 and 203 shown in FIG. 2A is an illustrative example, and in other implementations contacts 202 and 203 may be distributed in another pattern, for instance where contacts 202 are distributed in a pattern similar to the pattern of contacts 103 of PCB layout 100a or 100b and where contacts 203 are distributed in a pattern similar to the pattern of contacts used on a processor chip.

[0041] I/O chip 201 is shown in FIG. 2A as having similar size as PCB 101 of FIGS. 1A and 1B; however, the relative size of PCB 101 and I/O chip 201 in FIGS. 1A and 1B and FIG. 2A is an illustrative example and PCB 101 may be larger than I/O chip 201, for example, as shown in FIG. 4.

[0042] In some implementations, I/O chip layout 200 of I/O chip 201 comprises a grid of tiles 204 (only one called out in FIG. 2A to reduce clutter).

[0043] Each tile 204 comprises a frequency-multiplexed resonant (FMR) read-in and/or a FMR readout (FMRR), communicatively coupled to at least one other element on a processor chip by a bump bond or a solder bond or other coupling, as described in more details in FIG. 8. Read-in microwave lines and readout microwave lines are communicatively coupled to tiles 204.

[0044] FIG. 2A shows a cross-section line 250 for illustrative purpose to aid in the description of FIG. 2B.

[0045] FIG. 2B is a cross-sectional view of the layout 200 of the I/O chip 201, as described in FIG. 2A, along cross-section line 250 of FIG. 2A (not shown in FIG. 2B), the I/O chip 201comprising a plurality of contacts, according to the present disclosure. I/O chip 201 comprises a first or outer ring of contacts 202 (only one called out in FIG. 2B) distributed on an upper surface 205a of I/O chip 201, in a pattern similar to the pattern of contacts 103 of PCB layout 100a of FIG. 1A and 100b or FIG. 1B. Contacts 202 may, for example and without limitation, take the form of Indium bump bonds, superconducting solder bonds, or similar structures. I/O chip 201 further comprises a second or inner ring of contacts 203 (only one called out in FIG. 2B to reduce clutter) as described in FIG. 2A. In some implementations, I/O chip layout 200 of I/O chip 201 comprises a grid of tiles 204 (only one called out in FIG. 2B to reduce clutter) as described in FIG. 2A.

[0046] I/O chip 201 comprises a shield layer 206 below, underlying or spaced inwardly of contacts 202 and 203. Shield layer 206 may be a type-II superconducting shield layer with a relatively high critical temperature with respect to the critical temperature of the material comprising a processor integrated circuit or chip (shown in FIG. 3A and 3B). Alternatively, shield layer 206 may be comprised of another type of superconducting material with a relatively high critical temperature with respect to the critical temperature of the material comprising a processor integrated circuit or chip. Trapped flux can be largely mitigated through high critical temperature (T.sub.c) shields, for example comprising type-II superconductors, whose superconducting transition happens significantly before the superconducting transition of the sensitive circuitry of I/O chip 201. The excess flux is trapped by the high-T.sub.c shield while the sensitive circuitry is still in a normal (i.e., non-superconducting) state. When the sensitive circuitry is superconducting, it is substantially isolated from the excess magnetically flux, thus excess flux will not be trapped herein. In some implementations, contacts 202 and 203 are part of shield layer 206.

[0047] Superconducting vias 207 (only one called out in FIG. 2B to reduce clutter) extend through shield layer 206, leading excess magnetic flux to contacts 202 and 203. Additionally, one or more holes may extend through shield layer 206, where excess magnetic flux is deliberately trapped, thus removed from sensitive areas of I/O chip 201 and a processor chip, and/or by slots to guide excess magnetic flux away from sensitive areas of I/O chip 201 and a processor integrated circuit or chip.

[0048] I/O chip 201 also comprises a substrate layer 208, having an upper surface 209a adjacent to a bottom surface 205b of I/O chip 201, bottom surface 205b opposite upper surface 205a across a thickness 205c of I/O chip 201. Substrate layer 208 serves as a substrate upon which I/O circuitry is fabricated.

[0049] In some implementations, I/O chip 201 also comprises a thermally conductive layer 210, having an upper surface 211a and a bottom surface 211b, opposite upper surface 211a across a thickness 211c of thermally conductive layer 210. Upper surface 211a is adjacent to a bottom surface 209b of substrate layer 208, bottom surface 209b opposite upper surface 209a, across a thickness 209c of substrate layer 208. Thermally conductive layer 210 can comprise copper, gold or another material which remains thermally conductive near 0 Kelvin.

[0050] I/O chip layout 200 of I/O chip 201 may be used in a processor assembly, for example as shown in FIG. 4 and described below with respect thereto.

[0051] FIG. 3A is a planar view of an example layout 300 of a processor chip 301 comprising a plurality of contacts, according to the present disclosure.

[0052] In some implementations, processor chip 301 may be a superconducting processor chip, for example a superconducting quantum processor chip. Processor chip 301 has a size smaller than through-hole 102 of PCB 101 of FIGS. 1A and 1B and is able to fit inside through-hole 102 with an outermost surface either flush with an outermost surface of PCB 101, below the outermost surface of PCB 101, or proud of outermost surface of PCB 101. Processor chip 301 includes processor circuitry. When processor chip 301 is a quantum processor, it includes circuitry or circuit components such as, for example, qubits, couplers, Digital-to-Analog Converters (DACs), Quantum Flux Parametron (QFP) shift registers and analog lines. Processor chip 301 comprises a plurality of contacts 302 (only one called out in FIG. 3A to reduce clutter) distributed in a pattern similar to the pattern of contacts 203 of I/O chip layout 200 of I/O chip 201 of FIG. 2A. Contact 302 may, for example and without limitation, take the form of Indium bump bonds, superconducting solder bonds, or similar structures. A person skilled in the art will understand that the number of contacts 302 shown in FIG. 3A is an illustrative example and on other implementations, a larger or smaller number of contacts 302 may be used. Similarly, the pattern of contacts 302 shown in FIG. 3A is an illustrative example, and in other implementations contacts 302 may be distributed in another pattern, where contacts 302 are distributed in a pattern similar to the pattern of contacts used on a I/O integrated circuit or chip.

[0053] Processor chip 301 may be comprises of material substantially different from a material comprising I/O chip 201. I/O chip 201 may be comprised of a superconducting material, for example Niobium, while processor chip 301 may be comprised of a different superconducting material, for example Aluminum, for example in cases where lower-noise materials are favored for a superconducting processor chip and higher-reliability fabrication processes, rather than lower noise materials, are favored for I/O chips.

[0054] In some implementations, processor chip layout 300 of processor chip 301 comprises a grid of tiles 303 (only one called out in FIG. 3A to reduce clutter). Each tile 303 may comprise, for example, circuitry or circuit components such as qubits, couplers, qubit read-in and/or readout devices and DACs, and be communicatively coupled to one tile of an I/O chip, for example, one tile 204 of I/O chip layout 200 of FIG. 2A, by, for example, a bump bond or a solder bond, as described in more details in FIG. 8.

[0055] FIG. 3A shows a cross-section line 350 for illustrative purpose to aid in the description of FIG. 3B.

[0056] FIG. 3B is a cross-sectional view of example processor chip layout 300 of the processor chip 301 of FIG. 3A, along cross-section line 350 (not shown in FIG. 3B), processor chip 301 comprising a plurality of contacts, according to the present disclosure. Processor chip 301 comprises a plurality of contacts 302 (only one called out in FIG. 3B to reduce clutter) distributed flush with upper surface 304a of processor chip 301 in a pattern similar to the pattern of contacts 203 of I/O chip layout 200 of FIG. 2A. Contact 302 may, for example and without limitation, take the form of Indium bump bonds, superconducting solder bonds, or similar structures. In some implementations, processor chip layout 300 of processor chip 301 comprises a grid of tiles 303 (only one called out in FIG. 3B to reduce clutter), as described in FIG. 3A.

[0057] Processor chip 301 comprises a shield layer 305 below, underlying or spaced inwardly of contacts 302. Shield layer 305 may be a type-II superconducting shield layer with a relatively high critical temperature with respect to the critical temperature of the material comprising processor chip 301. Alternatively, shield layer 305 may be comprised of another type of superconducting material with a relatively high critical temperature with respect to the critical temperature of the material comprising processor chip 301. In some implementations, shield layer 305 is comprised of a different material than shield layer 206 of I/O chip 201 of FIG. 2B.

[0058] Superconducting vias 306 (only one called out in FIG. 3B to reduce clutter) extend through shield layer 305, leading excess magnetic flux to contacts 302. Additionally, holes may extend through shield layer 305, where excess magnetic flux is deliberately trapped, thus removed from sensitive areas of processor chip 301, and by slots to guide excess magnetic flux away from sensitive areas of processor chip 301.

[0059] Processor chip 301 also comprises a substrate layer 307, having an upper surface 308a adjacent to a bottom surface 304b of processor chip 301, bottom surface 304b opposite upper surface 304a across a thickness 304c of processor chip 301. Substrate layer 307 serves as a substrate upon which circuitry of processor 304 is fabricated, for example an electrically insulative substrate.

[0060] In some implementations, processor chip 301 also comprises a thermally conductive layer 309, having an upper surface 310a and a bottom surface 310b, opposite upper surface 310a across a thickness 310c of thermally conductive layer 309. Upper surface 310a is adjacent to a bottom surface 308b of substrate layer 307, bottom surface 308b opposite upper surface 308a, across a thickness 308c of substrate layer 307. Thermally conductive layer 309 can comprise copper, gold or another material which remains thermally conductive near 0 Kelvin.

[0061] Processor chip 301 may be used in a processor assembly as shown in FIG. 4.

[0062] FIG. 4 is a cross-sectional view of an example processor system 400 showing a relative position of printed circuit board 101 of FIGS. 1A or 1B, processor chip 301 of FIG. 3A and 3B and I/O chip 201 of FIG. 2A and 2B with mated contacts, along cross-section lines 150, 250 and 350 of FIGS. 1, 2A and 3A, respectively.

[0063] Processor system 400 comprises a printed circuit board (PCB), for example PCB 101 of FIGS. 1A or 1B, a processor chip, for example, processor chip 301 of FIG. 3A and 3B, and an I/O chip, for example I/O chip 201 of FIGS. 2A and 2B. Processor chip 301 is located at least partially within through-hole 102 of PCB 101. I/O chip 201 is located above PCB 101 and processor chip 301, with respect to the plane of the page of FIG. 4, so contacts 202 of I/O chip 201 mate with contacts 103 of PCB layout 100a or 100b and contacts 203 of I/O chip 201 mate with contacts 302 of processor chip 301.

[0064] Processor chip 301 also comprises a shield layer 305, a substrate layer 307 and a thermally conductive layer 309, as described above in FIG. 3B.

[0065] In some implementations, a thermalization layer 401 may be positioned adjacent to a bottom surface 310b of thermally conductive layer 309 of processor chip 301 to thermalize processor chip 301.

[0066] I/O chip 201 also comprises a shield layer 206, a substrate layer 208 and a thermally conductive layer 210, as described above in FIG. 2B. In some implementations, a path 402 to thermalization layer 401 may be positioned adjacent to bottom surface 211b of thermally conductive layer 210 of I/O chip 201.

[0067] FIG. 5 is a flow chart of an example method 500 of assembling an I/O chip comprising a plurality of contacts, according to the present disclosure. Method 500 may be used as part of an assembly of I/O chip having I/O chip layout 200, and will be described with reference to FIGS. 2A, 2B, and 5.

[0068] Method 500 comprises acts 502 to 510; however, a person skilled in the art will understand that the number of acts is an example, and, in some implementations, certain acts may be omitted, further acts may be added, and/or the order of the acts may be changed.

[0069] Method 500 starts at 502, by forming thermally conducting layer 210. Thermally conductive layer 210 can comprise copper, gold or another material which remains thermally conductive near 0 Kelvin.

[0070] At 504, substrate layer 208 is formed on upper surface 211a of thermally conductive layer 210. Substrate layer 208 serves as a substrate upon which I/O circuitry is fabricated.

[0071] At 506, I/O chip 201 is assembled on upper surface 209a of substrate layer 208. I/O chip 201 comprises I/O circuitry, including DACs, frequency-multiplexed resonant (FMR) read-in, frequency-multiplexed resonant (FMR) readout, microwave and analog lines. In some implementations, I/O chip 201 comprises a grid of tiles 204, each tile 204 comprising a frequency-multiplexed resonant (FMR) readout and/or FMR read-in.

[0072] At 508, shield layer 206 is formed (e.g., deposited). Shield layer 206 may be a type-II superconducting shield layer with a relatively high critical temperature, pierced by superconducting vias 207. Alternatively, shield layer 206 may be pierced by holes or slots.

[0073] At 510, first or outer ring of contacts 202 and second or inner ring of contacts 203 are formed (e.g., deposited, patterned (e.g., masked and etched)) on I/O chip 201. Contacts 202 are distributed in a pattern similar to the pattern of contacts 103 of PCB layout 100a or 100b of PCB 101, while contacts 203 distributed in a pattern similar to the pattern used for contacts 302 of processor chip layout 300 of processor chip 301. Contacts 202 and 203 can, for example and without limitation, take the form of Indium bump bonds, superconducting solder bonds, or similar structures.

[0074] FIG. 6 is a flow chart of an example method 600 of assembling a processor chip comprising a plurality of contacts, according to the present disclosure. Method 600 may be used as part of an assembly of processor chip layout 300 and will be described with reference to FIGS. 3A and 3B.

[0075] Method 600 comprises acts 602 to 610; however, a person skilled in the art will understand that the number of acts is an example, and, in some implementations, certain acts may be omitted, further acts may be added, and/or the order of the acts may be changed.

[0076] Method 600 starts at 602, by forming (e.g., depositing) thermally conducting layer 309. Thermally conductive layer 309 can comprise copper, gold or another material which remains thermally conductive near 0 Kelvin.

[0077] At 604, substrate layer 307 is formed (e.g., depositing) on upper surface 310a of thermally conductive layer 309. Substrate layer 307 serves as a substrate upon which processor circuitry is fabricated.

[0078] At 606, processor chip 301 is assembled on upper surface 308a of substrate layer 307. Processor chip 301 comprises processor circuitry, for example, qubits, couplers, Digital-to-Analog Converters (DACs), Quantum Flux Parametron (QFP) shift registers and analog lines. In some implementations, processor chip layout 300 of processor chip 301 comprises a grid of tiles 303. Each tile 303 may comprise, for example, circuitry or circuit components such as qubits, couplers, qubit readout and/or read-in devices and DACs.

[0079] Optionally, at 608, shield layer 305 is formed (e.g., deposited). Shield layer 305 may be a type-II superconducting shield layer with a relatively high critical temperature, pierced by superconducting vias 306. Alternatively, shield layer 305 may include holes or slots.

[0080] At 610, contacts 302 are formed (e.g., deposited, patterned (e.g., masked and etched)) on processor chip 301. Contacts 302 are distributed in a pattern similar to the pattern of contacts 203 of I/O chip layout 200 of I/O chip 201 of FIG. 2A. Contact 302 may, for example and without limitation, take the form of Indium bump bonds, superconducting solder bonds, or similar structures.

[0081] FIG. 7 is a flow chart of an example method 700 of assembling a processor system, for example processor system 400 of FIG. 4, comprising a printed circuit board, a processor chip and an I/O chip. Method 700 will be described with reference to processor system 400 of FIG. 4. Method 700 comprises acts 702 to 704; however, a person skilled in the art will understand that the number of acts is an example, and, in some implementations, certain acts may be omitted, further acts may be added, and/or the order of the acts may be changed.

[0082] Method 700 starts at 702. At 702, processor chip 301 is aligned inside through-hole 102 of PCB layout 100a or 100b.

[0083] At 704, I/O chip 201 is placed over PCB 101 and processor chip 301 so that contacts 202 of I/O chip 201 are mated with corresponding contacts 103 of PCB 101 and contacts 203 of I/O chip 200 are mated with corresponding contacts 302 of processor chip 301. Solder bonds contacts may be mated through a reflow process, while Indium bonds (or bonds comprising another superconducting material that remain pliable through a wide range of temperatures) may be mated through a mechanical process (e.g., a press).

[0084] FIG. 8 is a schematic diagram illustrating an example implementation of a portion 800 of a superconducting processor. Portion 800 includes an array of frequency multiplex resonant (FMR) readouts 802-1, 802-2, 802-3, and 802-4 (collectively referred to in the present application as FMR readouts 802), 804-1, 804-2, 804-3, and 804-4 (collectively referred to in the present application as FMR readouts 804), 806-1, 806-2, 806-3, and 806-4 (collectively referred to in the present application as FMR readouts 806), and 808-1, 808-2, 808-3, and 808-4 (collectively referred to in the present application as FMR readouts 808). FMR readouts 802 are communicatively coupled to input line 810. FMR readouts 804 are communicatively coupled to input line 812. FMR readouts 806 are communicatively coupled to input line 814. FMR readouts 808 are communicatively coupled to input line 816.

[0085] In one implementation, input lines 810, 812, 814, and 816 are separate input lines. In another implementation, some or all of input lines 810, 812, 814, and 816 are communicatively coupled to one another, for example wired together.

[0086] FMR readouts 802 are communicatively coupled to other circuitry or circuit components of the superconducting processor (not shown in FIGS. 1A and 1B) at 818-1, 818-2, 818-3, and 818-4 respectively. FMR readouts 804 are communicatively coupled to other circuitry or circuit components of the superconducting processor at 820-1, 820-2, 820-3, and 820-4 respectively. FMR readouts 806 are communicatively coupled to other circuitry or circuit components of the superconducting processor at 822-1, 822-2, 822-3, and 822-4 respectively.

[0087] FMR readouts 808 are communicatively coupled to other circuitry or circuit components of the superconducting processor at 824-1, 824-2, 824-3, and 824-4 respectively.

[0088] In one implementation, FMR readouts are communicatively coupled to other circuitry or circuit components of the superconducting processor in-situ. In another implementation, FMR readouts are communicatively coupled to other circuitry or circuit components of the superconducting processor by superconducting vias. In the present application, a via (vertical interconnect access) is an electrical connection between layers in a physical electronic circuit (e.g., an integrated circuit) that goes through the plane of one or more adjacent layers. In yet another implementation, FMR readouts are communicatively coupled to other circuitry or circuit components of the superconducting processor on a separate chip using bump bonds, solder bonds, or another suitable electrical communicative coupling.

[0089] FMR readouts 802 may be used as tiles 204 in I/O chip layout 200, as described in FIG. 2A. Further description and uses of FMR readouts 802 can be found in US patent application No. 62/860098.

[0090] FIG. 9 shows a schematic diagram of an exemplary implementation of a system 900 comprising a controllable coupler 901. Controllable coupler 901 includes a loop of superconducting material 902 interrupted by a Josephson junction 903 and is used to couple a first qubit 910 and a second qubit 920. First qubit 910 is comprised of a loop of superconducting material (or qubit loop) 911 interrupted by a compound Josephson junction

[0091] (CJJ) 912 and is coupled to controllable coupler 901 through the exchange of flux 904 between controllable coupler 901 and first qubit 910. Second qubit 920 is comprised of a loop of superconducting material (or qubit loop) 921 interrupted by a CJJ 922 and is coupled to controllable coupler 901 through the exchange of flux 905 between controllable coupler 901 and second qubit 920. Loop of superconducting material 902 is threaded by flux 906 created by electrical current flowing through a magnetic flux inductor 907. Controllable coupler 901 may be used to provide communicative coupling between qubits and thus be used in a quantum processor, in accordance with the presently described systems, devices, articles, and methods. Other examples of controllable couplers and qubits are presented in U.S. Pat. Nos. 7,898,282, and 7,800,395.

[0092] The above described method(s), process(es), or technique(s) could be implemented by a series of processor readable instructions stored on one or more nontransitory processor-readable media. Some examples of the above described method(s), process(es), or technique(s) method are performed in part by a specialized device such as an adiabatic quantum computer or a quantum annealer or a system to program or otherwise control operation of an adiabatic quantum computer or a quantum annealer, for instance a computer that includes at least one digital processor. The above described method(s), process(es), or technique(s) may include various acts, though those of skill in the art will appreciate that in alternative examples certain acts may be omitted and/or additional acts may be added. Those of skill in the art will appreciate that the illustrated order of the acts is shown for exemplary purposes only and may change in alternative examples. Some of the exemplary acts or operations of the above described method(s), process(es), or technique(s) are performed iteratively. Some acts of the above described method(s), process(es), or technique(s) can be performed during each iteration, after a plurality of iterations, or at the end of all the iterations.

[0093] The above description of illustrated implementations, including what is described in the Abstract, is not intended to be exhaustive or to limit the implementations to the precise forms disclosed. Although specific implementations of and examples are described herein for illustrative purposes, various equivalent modifications can be made without departing from the spirit and scope of the disclosure, as will be recognized by those skilled in the relevant art. The teachings provided herein of the various implementations can be applied to other methods of quantum computation, not necessarily the exemplary methods for quantum computation generally described above.

[0094] The various implementations described above can be combined to provide further implementations. All of the commonly assigned US patent application publications, US patent applications, foreign patents, and foreign patent applications referred to in this specification and/or listed in the Application Data Sheet are incorporated herein by reference, in their entirety, including but not limited to: US Provisional patent application No. 62/904,462, US Provisional patent application No. 62/860,098, U.S. Pat. Nos. 7,898,282, and 7,800,395.

[0095] These and other changes can be made to the implementations in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific implementations disclosed in the specification and the claims, but should be construed to include all possible implementations along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.