Abstract
Various methods and circuital arrangements for complete turn OFF of branches of a multi-branch cascode amplifier are presented. According to one aspect, a protection circuit coupled to a source node of an output transistor of a branch couples a reference voltage to the source node of the output transistor when the branch is turned OFF, and decouples the reference voltage from the source node when the branch is turned ON. According to another aspect, the protection circuit includes a switch whose off capacitance is sufficiently low so as not to affect performance of the branch when the branch is ON, and whose on resistance is sufficiently low to sufficiently reduce an RF amplitude at the source node of the output transistor when the branch is OFF and other branches are ON, and therefore allow use of low-voltage thin-oxide transistors in the branch. Further aspects include a second switch and use of transistor switches.
Claims
1. A multi-branch cascode amplifier comprising: a plurality of stacked cascode amplifier branches, each branch comprising a common-source input transistor and one or more common-gate cascode transistors comprising an output transistor whose drain, that is coupled to a supply voltage, is a common output node of the multi-branch cascode amplifier, the each branch configured to operate according to an ON state for amplification at the common output node of an input RF signal coupled to the input transistor of the branch, and an OFF state for no amplification of the input RF signal; and a protection circuit coupled to a source node of the output transistor of a first branch of the plurality of stacked cascode amplifier branches, wherein: during the OFF state of the first branch and the ON state of one or more other branches of the plurality of stacked cascode amplifier branches, the protection circuit is configured to selectively couple a reference voltage to the source node of the output transistor of the first branch.
2. The multi-branch cascode amplifier of claim 1, wherein when the reference voltage is coupled to the source node of the output transistor of the first branch, a gate-to-source voltage of said output transistor is less than 0 Volts.
3. The multi-branch cascode amplifier of claim 1, wherein a biasing voltage to a gate of the output transistor of the first branch during the ON state and the OFF state of the first branch is a same biasing voltage.
4. The multi-branch cascode amplifier of claim 1, wherein: the protection circuit comprises a first switch comprising a first terminal coupled to the source node of the output transistor of the first branch, and a second terminal coupled to the reference voltage, during the ON state of the first branch, the first switch is open and thereby decouples the reference voltage from the source node of said output transistor via an off capacitance of the first switch, and during the OFF state of the first branch and the ON state of the one or more other branches, the first switch is closed and thereby couples the reference voltage to the source node of said output transistor via an on resistance of the first switch.
5. The multi-branch cascode amplifier of claim 4, wherein the on resistance of the first switch is configured to affect an impedance seen at the source node of said output transistor at a frequency of operation of the input RF signal so that an amplitude of an amplified version of the input RF signal by the one or more other branches that is coupled to said source node via an off capacitance of said output transistor is sufficiently reduced to operate a transistor of the first branch that is directly coupled to said output transistor within a tolerable voltage range of said transistor.
6. The multi-branch cascode amplifier of claim 5, wherein, at the frequency of operation of the input RF signal, the on resistance of the first switch is equal to, or smaller than, one tenth of a magnitude of an impedance seen at the source node of said output transistor looking down the first branch when the first branch is OFF.
7. The multi-branch cascode amplifier of claim 4, wherein each of the common-source input transistors and the one or more common-gate cascode transistors of the first branch is a thin-oxide transistor having a maximum tolerable voltage that is smaller than a peak voltage provided by a combination of: a) the supply voltage, and b) an amplified version of the input RF signal by the one or more other branches at the common output node of the multi-branch cascode amplifier.
8. The multi-branch cascode amplifier of claim 7, wherein: the first switch is one of: a) an electromechanical switch, b) a MEMS switch, and c) a transistor switch.
9. The multi-branch cascode amplifier of claim 8, wherein the transistor switch c) is an NMOS FET transistor, wherein: a source node of c) defines the first terminal of the first switch, a drain node of c) defines the second terminal of the first switch, and a gate node of c) is coupled to a control signal configured to control the first switch to close or open.
10. The multi-branch cascode amplifier of claim 4, wherein the protection circuit further comprises: a capacitor coupled to said source node via a first terminal of the capacitor; a second switch coupled to a second terminal of the capacitor at a first terminal of the second switch, a second terminal of the second switch coupled to the reference ground, wherein: during the ON state of the first branch, the second switch is open and thereby decouples the reference ground from the second terminal of the capacitor via an off capacitance of the second switch, and during the OFF state of the first branch and the ON state of the one or more other branches, the second switch is closed and thereby couples the reference ground to the second terminal of the capacitor via an on resistance of the second switch.
11. The multi-branch cascode amplifier of claim 10, wherein: the on resistance of the first switch is substantially larger than the on resistance of the second switch, and a combined impedance of the protection circuit is configured to affect an impedance seen at the source node of said output transistor at a frequency of operation of the input RF signal so that an amplitude of an amplified version of the input RF signal by the one or more other branches that is coupled to said source node via an off capacitance of said output transistor is sufficiently reduced to operate a transistor of the first branch that is directly coupled to said output transistor within a tolerable voltage range of said transistor.
12. The multi-branch cascode amplifier of claim 11, wherein, at the frequency of operation of the input RF signal, a magnitude of an impedance provided by a series connection of the on resistance of second switch with the capacitor is equal to, or smaller than, one tenth of a magnitude of an impedance seen at the source node of said output transistor looking down the first branch when the first branch is OFF.
13. The multi-branch cascode amplifier of claim 10, wherein each of the common-source input transistors and the one or more common-gate cascode transistors of the first branch is a thin-oxide transistor having a maximum tolerable voltage that is smaller than a peak voltage provided by a combination of: a) the supply voltage, and b) an amplified version of the input RF signal by the one or more other branches at the common output node of the multi-branch cascode amplifier.
14. The multi-branch cascode amplifier of claim 13, wherein: the supply voltage is about 1.2 Volts, each branch consists of the common-source input transistor and the common-gate cascode output transistor, and the common-source input transistor and the common-gate cascode output transistor of each branch is a thin-oxide transistor with a maximum tolerable voltage of about 1.32 Volts.
15. The multi-branch cascode amplifier of claim 10, wherein the first switch is a PMOS FET transistor and the second switch is an NMOS FET transistor, wherein: a drain node of the PMOS FET transistor defines the first terminal of the first switch, a source node of the PMOS FET transistor defines the second terminal of the first switch, a gate node of the PMOS FET transistor is coupled to a first control signal configured to control the first switch to close or open, a drain node of the NMOS FET transistor defines the first terminal of the second switch, a source node of the NMOS FET transistor defines the second terminal of the second switch, and a gate node of the NMOS FET transistor is coupled to a second control signal configured to control the second switch to close or open.
16. The multi-branch cascode amplifier of claim 15, wherein: a voltage level of the first control signal and of the second control signal is within a range defined by the reference ground and the supply voltage.
17. The multi-branch cascode amplifier of claim 15, further comprising a second protection circuit coupled to a source node of a common-gate cascode transistor of the one or more common-gate cascode transistors of the first branch that is different from the output transistor of the first branch; wherein: during the OFF state of the first branch and the ON state of one or more other branches of the plurality of stacked cascode amplifier branches, the second protection circuit is configured to selectively couple a second reference voltage to the source node of said common-gate cascode transistor of the first branch so that a gate-to-source voltage of said common-gate cascode transistor is less than 0 Volts, and a biasing voltage to a gate of said common-gate cascode transistor of the first branch during the ON state and the OFF state of the first branch is a same biasing voltage.
18. The multi-branch cascode amplifier of claim 1, wherein for each of the plurality of stacked cascode amplifier branches, the common-source input transistor and the one or more common-gate cascode transistors comprise thin metal-oxide-semiconductor (MOS) field effect transistors (FETs).
19. The multi-branch cascode amplifier of claim 18, wherein said transistors are fabricated using one of: a) silicon-on-insulator (SOI) technology, b) silicon-on-sapphire (SOS) technology, and c) bulk silicon (Si) technology.
20. The multi-branch cascode amplifier of claim 1, wherein the multi-branch cascode amplifier is monolithically integrated.
21. An electronic module comprising the multi-branch cascode amplifier of claim 1.
22. A radio frequency (RF) front-end module, comprising: a receiver section for amplifying an RF signal according to different modes of operation, the receiver section comprising the multi-branch cascode amplifier of claim 1 operating as a low-noise amplifier (LNA).
23. A method for turning OFF a branch of a multi-branch cascode amplifier, the method comprising: turning ON a plurality of branches of the multi-branch cascode amplifier by: providing to each branch of the plurality of branches respective gate biasing voltages to a common-source input transistor and one or more common-gate cascode transistors of the branch for operation of the branch as an amplifier during a respective ON state of the branch; and turning OFF one branch of the plurality of branches by: setting the biasing voltage of the common-source input transistor to the reference ground, V.sub.GND, and coupling a reference voltage to a source node of an output transistor of the branch so that a gate-to-source voltage of said output transistor is less than 0 Volts, and maintaining a same biasing voltage of the respective gate biasing voltages to a gate of the output transistor of said branch during the ON state and the OFF state of the branch.
24. The method according to claim 23, wherein the coupling of the reference voltage to the source node of the output transistor affects an impedance seen at the source node of said output transistor at a frequency of operation of the amplifier so that an amplitude of an amplified RF signal by one or more other turned ON branches that is coupled to said source node via an off capacitance of said output transistor is sufficiently reduced to operate a transistor of the first branch that is directly coupled to said output transistor within a tolerable voltage range of said transistor.
Description
BRIEF DESCRIPTION OF DRAWINGS
(1) The accompanying drawings, which are incorporated into and constitute a part of this specification, illustrate one or more embodiments of the present disclosure and, together with the description of example embodiments, serve to explain the principles and implementations of the disclosure.
(2) FIG. 1 shows a prior art configuration of a stacked transistor amplifier.
(3) FIG. 2A shows a prior art configuration of a multi-branch cascode amplifier.
(4) FIG. 2B shows a configuration of a multi-branch cascode amplifier, including a protection circuit that selectively couples a source node of a common-gate cascode output transistor of a branch to a reference ground.
(5) FIG. 3A shows a configuration of a multi-branch cascode amplifier according to an embodiment of the present disclosure, including a protection circuit that selectively couples a source node of a common-gate cascode output transistor of a branch to a reference voltage.
(6) FIG. 3B shows an equivalent representation of the configuration of FIG. 3A for a case of a turned OFF branch.
(7) FIG. 3C shows an equivalent representation of the configuration of FIG. 3A for a case of a turned ON branch.
(8) FIG. 3D shows the configuration of FIG. 3A for an exemplary implementation of the protection circuit using a transistor switch.
(9) FIG. 4A shows a configuration of a multi-branch cascode amplifier according to an embodiment of the present disclosure, including a protection circuit that selectively couples a source node of a common-gate cascode output transistor of a branch to one of a reference voltage and a reference ground.
(10) FIG. 4B shows an equivalent representation of the configuration of FIG. 4A for a case of a turned OFF branch.
(11) FIG. 4C shows an equivalent representation of the configuration of FIG. 4A for a case of a turned ON branch.
(12) FIG. 4D shows the configuration of FIG. 4A for an exemplary implementation of the protection circuit using transistor switches.
(13) FIG. 5A shows a configuration of a multi-branch cascode amplifier according to an embodiment of the present disclosure comprising two branches, each branch comprising a plurality of common-gate cascode transistors, including protection circuits coupled to the common-gate cascode transistors of each branch.
(14) FIG. 5B shows a circuital arrangement for providing reference voltages to the protection circuits of the configurations of FIG. 5A (or FIG. 5C).
(15) FIG. 5C shows a configuration of a multi-branch cascode amplifier according to an embodiment of the present disclosure comprising a plurality of branches, each branch comprising a plurality of common-gate cascode transistors, including protection circuits coupled to the common-gate cascode transistors of each branch.
(16) FIG. 6 is a process chart showing various steps of a method for turning OFF a branch of a multi-branch cascode amplifier.
(17) Like reference numbers and designations in the various drawings indicate like elements.
DETAILED DESCRIPTION
(18) Throughout the present disclosure, embodiments and variations are described for the purpose of illustrating uses and implementations of inventive concepts of various embodiments. The illustrative description should be understood as presenting examples of the inventive concept, rather than as limiting the scope of the concept as disclosed herein.
(19) As described above with reference to FIG. 2A, by providing a same biasing voltage V.sub.Bias22 to the gate of the output cascode transistor M22 during the ON state and the OFF state of the branch (M21, M22), the drain-to-gate voltage V.sub.DG_M22 of the transistor M22 can be reduced and kept, for example, within a tolerable voltage range of a thin oxide transistor (e.g., 1.32 volts). In this configuration, further protection to the transistors of the turned OFF branch (M21, M22) can be provided via a protection circuit (210) shown in FIG. 2B. The protection circuit (210) includes a resistor Rx coupled at a first terminal of the resistor Rx to a switching terminal (e.g., throw) of a switch SW.sub.X (e.g., single-pole single-throw SPST), a second terminal of the resistor Rx is coupled to a common node N.sub.21 of the source of transistor M22 and the drain of the transistor M21, and a common terminal (e.g., pole) of the switch SW.sub.X is coupled to the reference ground, V.sub.GND. A control signal, V.sub.CTRL, controls a state of the switch SW.sub.X based on an ON or OFF state of the branch (M21, M22). When the branch is OFF, the switch SW.sub.X is closed and a voltage at the common node N.sub.21 is formed based on a leakage current of the transistor M22 flowing to the reference ground, V.sub.GND, through the resistor Rx. A resistance of Rx can be selected to provide a voltage at the common node N.sub.21 so that the transistors M21 and M22 are not subjected to any voltage beyond their respective tolerable voltage ranges. On the other hand, when the branch is OFF, the switch SW.sub.X is open and effectively no current flows through an open circuit provided by the resistor Rx coupled to the common node N.sub.21.
(20) The protection circuit (210) shown in FIG. 2B can protect the transistors M21 and M22 during the OFF state of the branch (M21, M22), and therefore allow usage of, for example, thin oxide transistors having lower maximum tolerable voltages, while having a minimum effect on the branch during the ON state of the branch. However, during the OFF state of the branch (M21, M22) the output transistor M2 is conducting (transistor is ON) and therefore, as previously described, can negatively affect performance of the amplifier (200A) as provided by other active branches.
(21) FIG. 3A shows a configuration of a multi-branch cascode amplifier (300A) according to an embodiment of the present disclosure, including a protection circuit (310) that addresses the problem with the protection circuit (210) described with reference to FIG. 2B. As shown in FIG. 3A, the protection circuit (310) comprises a switch SW.sub.X (e.g., single-pole single-throw SPST) that selectively couples, under control of the control signal, V.sub.CTRL, a common-gate cascode output transistor (e.g., M22) of a branch (e.g., M21, M22) to a reference voltage, V.sub.DD2. For example, when the branch (M21, M22) is OFF, the switch SW.sub.X is closed and therefore couples the reference voltage, V.sub.DD2, to the common node N.sub.21, and when the branch (M21, M22) is ON, the switch is open and therefore decouples the reference voltage, V.sub.DD2, from the common node N.sub.21. It should be noted that although FIG. 3A shows one branch (e.g., M21, M22) comprising the protection circuit (e.g., 310), such exemplary configuration should not be considered as limiting the scope of the present teachings, as the protection circuit (310) can be provided to protect any branch (e.g., M11, M12) of a multi-branch cascode amplifier, whether including two branches (shown in FIG. 3A) or more branches (e.g., shown in FIG. 5B later described). Furthermore, teachings according to the present disclosure equally apply to multi-branch cascode amplifiers whose branches include more than a single common-gate cascode transistor as shown in FIG. 5A and FIG. 5C later described.
(22) With continued reference to FIG. 3A, when the branch (M21, M22) is OFF, the reference voltage V.sub.DD2 defines the source voltage of the transistor M22 and the drain voltage of the transistor M21. According to an embodiment of the present disclosure, a voltage level of the reference voltage V.sub.DD2 is chosen so that the M22 transistor does not conduct any current (i.e., M22 is OFF). This can be achieved if a gate-to-source voltage V.sub.GS_M22 of the transistor M22 is negative. As understood by a person skilled in the art, transistor M22 is OFF if: V.sub.G_M22V.sub.S_M22<0, or, since V.sub.S_M22=V.sub.DD2, transistor M22 is OFF if: V.sub.DD2>V.sub.G_M22. On the other hand, the reference voltage, V.sub.DD2 also defines a drain-to-source voltage V.sub.DS_M21 and drain-to-gate voltage V.sub.DG_M21 of the input transistor M21 which has to be kept within a tolerable voltage range of the transistor M21. If such tolerable voltage range is defined by a maximum value, V.sub.DS_M21_MAX or V.sub.DG_M21_MAX, then according to an embodiment of the present disclosure, the voltage V.sub.DD2 can be chosen such that: V.sub.DS_M21_MAX>V.sub.DD2>V.sub.G_M22 and V.sub.DG_M21_MAX>V.sub.DD2. Such value of the reference voltage V.sub.DD2, together with the protection circuit (310) allows: a) applying a same biasing voltage to the gate of the output cascode transistor during the ON state and the OFF state of the branch (M21, M22) and therefore allows usage of, for example, thin-oxide transistors, b) protecting the transistors M21 and M22 during the OFF state of the branch from voltages higher than their tolerable voltage ranges, and c) complete turn OFF of an OFF branch to reduce impact of the OFF branch on a performance of the multi-branch amplifier provided by other turned ON branches.
(23) According to an exemplary embodiment of the present disclosure, V.sub.DD2 can be the supply voltage V.sub.DD. Because the biasing voltage at the gate of the output cascode transistor M22 is smaller than a level of the supply voltage V.sub.DD, using such supply voltage as the reference voltage coupled to the switch SW.sub.X of the protection circuit (310) of FIG. 3A would satisfy the requirements for the level of the reference voltage V.sub.DD2 described above, and therefore can provide the above-described benefits.
(24) According to an exemplary embodiment of the present disclosure, the switch SW.sub.X can be an electromechanical switch, a MEMS switch, a semiconductor switch, a transistor switch, or any other switch configuration known to a person skilled in the art that can provide a sufficiently low on resistance, R.sub.ON, when the switch is closed (i.e., branch is OFF), and a sufficiently low off capacitance, C.sub.OFF, when the switch is open (i.e., branch is ON). FIG. 3B and FIG. 3C provide equivalent representations of a turned ON and turned OFF branch including the protection circuit (310) at RF frequencies.
(25) FIG. 3B shows an equivalent representation at RF frequencies of the configuration of FIG. 3A for a case of a turned OFF branch (M21, M22), including respective off capacitances C.sub.OFF21 and C.sub.OFF22 of the transistors M21 and M22 (neither conducts), and on resistance, R.sub.ONX of the switch SW.sub.X. A person skilled in the art would clearly understand such representation of the branch (M21, M22) in the OFF state of the branch, including the equivalent reference ground, V.sub.GND, coupling provided by the reference voltage, V.sub.DD2, at the RF frequencies.
(26) With continued reference to FIG. 3B, the off capacitances C.sub.OFF21 and C.sub.OFF22 of the transistors M21 and M22 form a capacitive voltage divider that divides an RF voltage (e.g., provided by other ON branches) having an amplitude V.sub.0 at the drain of the output cascode transistor M22 (common to the drain of the output cascode transistor M12), and provides a divided version of the RF voltage at the common node N.sub.21 having an amplitude V.sub.N21 that is approximately equal to V.sub.0*C.sub.OFF22/(C.sub.OFF21+C.sub.OFF22). As a result, and assuming that the on resistance, R.sub.ONX, of the switch SW.sub.X is absent (e.g., relatively high impedance value), during the OFF state of the branch (M21, M22), a peak voltage at the common node N.sub.21 can be represented by a combination of a DC voltage V.sub.DD2, and the AC voltage V.sub.0*C.sub.OFF22/(C.sub.OFF21+C.sub.OFF22), or the sum V.sub.DD2+V.sub.0*C.sub.OFF22/(C.sub.OFF21+C.sub.OFF22), which can be sufficiently high to damage the input transistor M21 (e.g., due to high drain-to-source and/or drain-to-gate voltage of M21). This highlights a requirement to choose a switch SW.sub.X having an on resistance, R.sub.ONX, that allows reducing of the peak voltage at the common node, N.sub.21, as described below.
(27) With continued reference to FIG. 3B, according to an exemplary embodiment of the present disclosure, the switch SW.sub.X is chosen so that R.sub.ONX0.1*(1/jC.sub.OFF21) wherein =2f; f is the highest frequency component of the RF signal; and j is the unit imaginary number. By choosing a switch SW.sub.X with a sufficiently low on resistance, R.sub.ONX, compared to an impedance (1/jC.sub.OFF21) of the off capacitance C.sub.OFF21 at the frequencies of operation of the RF signal, a combined parallel impedance R.sub.ONX(1/jC.sub.OFF21) can be approximated to R.sub.ONX. Therefore, for such sufficiently low on resistance, R.sub.ONX, of the switch SW.sub.X, a peak voltage at the common node N.sub.21 can be represented by a combination of a DC voltage V.sub.DD2, and the AC voltage V.sub.0*R.sub.ONX/(R.sub.ONX+(1/jC.sub.OFF22))=V.sub.0*(j*C.sub.OFF22*R.sub.ONX), or in other words, by the sum V.sub.DD2+V.sub.0*(jC.sub.OFF22*R.sub.ONX), which can be sufficiently low to be within the tolerable voltage range of the input transistor M21. According to an exemplary embodiment of the present disclosure, a value of the resistance R.sub.ONX may be chosen to be less than one tenth the impedance value of the off capacitance C.sub.OFF21 described above. In such embodiment, the peak voltage at the common node N.sub.21 is about V.sub.DD2+0.1*V.sub.0.
(28) FIG. 3C shows an equivalent representation at RF frequencies of the configuration of FIG. 3A for a case of a turned ON branch (M21, M22), including an off capacitance, C.sub.OFFX, of the switch SW.sub.X. According to an embodiment of the present disclosure, the switch SW.sub.X can be chosen so that its off capacitance, C.sub.OFFX, is sufficiently low so that it does not negatively impact performance of the turned ON branch (M21, M22). In other words, the impedance of the off capacitance, C.sub.OFFX, of the switch SW.sub.X at the frequencies of operation of the RF signal is sufficiently high so as not to affect the RF signal at the common node N.sub.21 during amplification of the RF signal through the branch (M21, M22).
(29) As shown in FIG. 3D, according to an exemplary embodiment of the present disclosure, the switch SW.sub.X used in the protection circuit (310) of FIG. 3A can be a transistor switch Mx. For example, the transistor switch Mx can be an NMOS (FET) transistor switch as shown in FIG. 3D with a drain node coupled to the reference voltage, V.sub.DD2, the source node coupled to the common node N.sub.21, and a gate node coupled to the control signal, V.sub.CTRL. Alternatively, the transistor switch Mx can be a PMOS (FET) transistor switch so long as it can satisfy requirements for its on resistance, R.sub.ONX, and off capacitance, C.sub.OFFX, as described above with reference to FIG. 3B and FIG. 3C. For example, a size of the transistor switch Mx can be chosen to be small enough to provide a sufficiently low off capacitance, C.sub.OFFX, and a level of the control voltage, V.sub.CTRL, can be chosen to be sufficiently high to provide a low on resistance, R.sub.ONX, when the transistor switch Mx is conducting (i.e., switch is closed).
(30) As understood by a person skilled in the art, the on resistance, R.sub.ONX, of the transistor switch Mx shown in FIG. 3D may be a function of a gate-to-source voltage provided to the transistor via a voltage level of the control signal, V.sub.CTRL, wherein a higher value of the gate-to-source voltage provides a lower value of the on resistance, R.sub.ONX. In some cases, setting the voltage level of the control signal, V.sub.CTRL, for turning ON the transistor switch Mx to the level of the supply voltage, V.sub.DD, may be sufficiently high to provide a sufficiently low on resistance, R.sub.ONX, of the transistor switch, Mx. In cases where the level of the supply voltage, V.sub.DD, is not sufficiently high, a higher voltage level of the control signal, V.sub.CTRL, for turning ON the transistor switch Mx may be provided by a level shifter that provides a level-shifted version of the supply voltage, V.sub.DD. A person skilled in the art is well aware of various implementation designs and circuits for generating such level-shifted voltage, which designs are beyond the scope of the present application. On the other hand, the level of the control signal, V.sub.CTRL, for turning OFF the transistor switch Mx may be set to, for example, zero Volts (e.g., short to V.sub.GND). It should be noted that because higher voltage levels may be applied to the transistor switch Mx shown in FIG. 3D, such transistor may be chosen to be a thick-oxide transistor which inherently provides a higher maximum tolerable voltage for a given fabrication process.
(31) FIG. 4A shows a configuration of a multi-branch cascode amplifier (400A) according to another embodiment of the present disclosure, including a protection circuit (410) that addresses the problem with the protection circuit (210) described with reference to FIG. 2B. As shown in FIG. 4A, the protection circuit (410) comprises a first switch SW.sub.X1 (e.g., single-pole single-throw SPST) that similarly to the switch SW.sub.X of the protection circuit (310) of FIG. 3A, selectively couples, under control of the control signal, V.sub.CTRL1, the common node, N.sub.21, at the source of common-gate cascode output transistor (e.g., M22) of a branch (e.g., M21, M22), to a reference voltage, V.sub.DD2. In addition to the first switch, SW.sub.X1, the protection circuit (410) includes a second switch, SW.sub.X2, which selectively couples (at RF frequencies of operation) the common node, N.sub.21, to the reference ground, V.sub.GND, through a capacitor, C10. As can be seen in FIG. 4A, the capacitor C10 is coupled to the common node, N.sub.21, at a first terminal of the capacitor C10, and is coupled to a switching terminal (e.g., throw) of the second switch, SW.sub.X2, at a second terminal of the capacitor C10. Furthermore, a common terminal (e.g., pole) of the second switch, SW.sub.X2, is coupled to the reference ground, V.sub.GND.
(32) FIG. 4B shows an equivalent representation at RF frequencies of the configuration of FIG. 4A for a case of a turned OFF branch (M21, M22), including respective off capacitances C.sub.OFF21 and C.sub.OFF22 of the transistors M21 and M22 (neither conducts); an on resistance, R.sub.ONX1 of the first switch SW.sub.X1, and an on resistance, R.sub.ONX2 of the second switch SW.sub.X2 in series connection with the capacitor C10. As clearly understood by a person skilled in the art, during the OFF state of the branch (M21, M22), the combination of the series-connected capacitor C10 and an on resistance, R.sub.ONX2 of the second switch, SW.sub.X2, can allow further control of an impedance value (at the frequencies of operation) between the common node N.sub.21 and the reference ground, V.sub.GND, at the frequencies of operation of the RF signal, and therefore control of an amplitude of an AC component at the common node N.sub.21. On the other hand, during the OFF state of the branch (M21, M22), the capacitor C10 can block any DC path (e.g., for a leakage current) to the reference ground, V.sub.GND, and therefore maintain the cascode transistor M22 turned OFF via application of the reference voltage, V.sub.DD2, at the common node N.sub.21.
(33) With continued reference to FIG. 4B, by choosing the capacitor C10 and the second switch, SW.sub.X2, such that a corresponding combined impedance value (C10 in series with R.sub.ONX2) at the frequencies of operation of the RF signal is substantially lower than an impedance value (i.e., R.sub.ONX1) of the first switch, SW.sub.X1, the effect of a higher impedance value of the first switch, SW.sub.X1, on an amplitude of an AC component at the common node, N.sub.21, can be canceled. In other words, the first switch, SW.sub.X1, may be chosen to present a higher value on resistance, R.sub.ONX1, without affecting effectiveness of the protection circuit (410) in protecting the input transistor M21 in the OFF state of the branch (M21, M22). It should be noted that such higher value of the on resistance, R.sub.ONX1, may not necessarily be based on a design choice, but rather on a design constraint. For example, as described above with reference to FIG. 3D, in a case of a transistor based switch (e.g., SW.sub.X1 of FIG. 3D), a size of the switch may be chosen in view of an off capacitance, C.sub.OFFX, of the switch, and the on resistance value, R.sub.ONX, may be lowered by applying a larger voltage control signal, V.sub.CTRL. However, such larger voltage, as provided for example by a level shifter, may not necessarily be available in a target system of the multi-branch amplifier. As clearly understood by a person skilled in the art, the various embodiments of the protection circuit according to the present teachings may be adapted to different voltage levels available in different target systems.
(34) With continued reference to FIG. 4B, according to an exemplary embodiment of the present disclosure, the second switch, SW.sub.X2, and the capacitor C10 may be chosen such that the combined impedance R.sub.ONX2+1/jC10 is substantially smaller than R.sub.ONX1 at the frequencies of operation of the RF signal (e.g., at the lowest frequency of operation). Accordingly, the parallel impedance Z.sub.410=R.sub.ONX1(R.sub.ONX2+1/jC10) seen at the common node, N.sub.21, contributed by the protection circuit (410) can be approximated to Z.sub.410=R.sub.ONX2+1/jC10. Furthermore, by choosing a value of the capacitor C10 and the switch SW.sub.X2 such that at the frequencies of operation of the RF signal: Z.sub.410=R.sub.ONX2+1/jC100.1*(1/jC.sub.OFF21), then for such sufficiently low on impedance presented by the protection circuit (410), a peak voltage at the common node N.sub.21 can be represented by a combination of a DC voltage V.sub.DD2, and the AC voltage V.sub.0*Z.sub.410/(Z.sub.410+1/jC.sub.OFF22), or in other words, by the sum V.sub.DD2+V.sub.0*Z.sub.410/(Z.sub.410+1/jC.sub.OFF22), which can be sufficiently low to be within the tolerable voltage range of the input transistor M21 (i.e., smaller than a maximum limit of a drain-to-source voltage and a drain-to-gate voltage).
(35) FIG. 4C shows an equivalent representation at RF frequencies of the configuration of FIG. 4A for a case of a turned ON branch (M21, M22), including an off capacitance, C.sub.OFFX1, of the switch SW.sub.X1 and off capacitance, C.sub.OFFX2, of the switch SW.sub.X2. According to an embodiment of the present disclosure, the switches SWx1 and SWx2 can be chosen so that their respective off capacitances, C.sub.OFFX1 and C.sub.OFFX2 are sufficiently low so that they do not impact performance of the turned ON branch (M21, M22). In other words, the impedance of each of the off capacitances, C.sub.OFFX1 and C.sub.OFFX2, of the switches SW.sub.X1 and SW.sub.X2 at the frequencies of operation of the RF signal is sufficiently high so as not to affect the RF signal at the common node N.sub.21 during amplification of the RF signal through the branch (M21, M22).
(36) As shown in FIG. 4D, according to an exemplary embodiment of the present disclosure, the switches SW.sub.X1 and SW.sub.X2 used in the protection circuit (410) of FIG. 4A can be transistor switches Mxp and Mxn. For example, as shown in FIG. 4D, the transistor switch Mxp can be a PMOS transistor switch with a source node coupled to the reference voltage, V.sub.DD2, the drain node coupled to the common node N.sub.21, and a gate node coupled to the control signal, V.sub.CTRL_P. Additionally, as shown in FIG. 4D, the transistor switch Mxn can be an NMOS transistor switch with the source node coupled to the reference ground, V.sub.GND, the drain node coupled to the capacitor C10, and the gate node coupled to a control signal, V.sub.CTRL N. It should be noted that the teachings according to the present disclosure of the protection circuit (410) shown in FIG. 4D are not limited to the specific transistor types shown, and therefore any transistor switch, including NMOS or PMOS, can be used for any of the switches SW.sub.X1 and SW.sub.X2, so long as the transistor switches can satisfy requirements for their respective on resistances and off capacitances described above with reference to FIG. 4B and FIG. 4C.
(37) With continued reference to FIG. 4D, according to an exemplary embodiment of the present disclosure, a size of the PMOS transistor switch Mxp can be chosen to be small enough to provide a sufficiently low off capacitance, C.sub.OFFX1. A person skilled in the art would know that given the current state of transistor fabrication technology, for a given transistor size, a PMOS transistor may exhibit a higher on resistance compared to an NMOS transistor. Therefore, the small size PMOS transistor switch Mxp shown in FIG. 4D, the small size chosen to provide a sufficiently low off capacitance for a reduced impact on the RF signal when the branch is ON, may present a relatively high on resistance, (e.g., R.sub.ONX1 of FIG. 4B) that may not be sufficiently low to protect the input transistor M21 when the branch is OFF. However, by choosing the capacitance C10 and a size of the NMOS transistor switch Mxn to satisfy requirements for its on resistance and off capacitance described above with reference to FIG. 4B and FIG. 4C, a level of the AC voltage at the common node, N.sub.21, can be sufficiently reduced so as to protect the input transistor M21 when the branch (M21, M22) is OFF. In addition, since the on resistance of the PMOS transistor Mxp is not required to be largely reduced, a voltage level provided by the control signal, V.sub.CTRL_P to turn ON the PMOS transistor Mxp can be relatively low, such as, for example, equal to V.sub.GND. Accordingly, the configuration of the protection circuit (410) may be suitable for integration of the multi-branch amplifier (400A) shown in FIG. 4A in target system having supply voltages of limited level.
(38) FIG. 5A shows a configuration of a multi-branch cascode amplifier (500A) according to an embodiment of the present disclosure comprising two branches, (M11, . . . , M1n) and (M21, . . . , M2n), each branch comprising a plurality of common-gate cascode transistors, (M12, . . . , M1n) and (M22, M2n) and respective common-source input transistors M11 and M12. Furthermore, as shown in FIG. 5A, each branch includes respective protection circuits (510) coupled to the sources of the common-gate cascode transistors of the branch, wherein each protection circuit (510) may be any one of the protection circuits described above (e.g., 310, 410). As shown in FIG. 5A, a same biasing voltage (V.sub.Bias2, . . . , V.sub.Biasn) can be provided to each common-gate cascode transistor of a branch in either the ON state or the OFF state of the branch. In the OFF state of a branch, all cascode transistors and the input transistor of the branch may be turned OFF, wherein as described above, the turning OFF of the cascode transistors may be provided by coupling a reference voltage to a source node of the cascode transistors via the protection circuits (510). A person skilled in the art would clearly know how to apply the above teachings to the configuration shown in FIG. 5A. Furthermore, it should be noted that as shown in the multi-branch amplifiers (300A, 400A, 500A) of FIGS. 3A, 4A, and 5A, control of the current through such amplifiers is provided by selectively activating one or more of the branches, each branch contributing to a portion of the current through the amplifiers that is based on, for example, a sizing of the branch, and not by adjusting biasing voltages to the gates of the transistors of the branches as known to a person skilled in the art. By maintaining constant gate biasing voltages to the branches, optimum performance of each branch can be maintained. Finally, during a deactivated mode of the amplifiers (e.g., 300A, 400A, 500A) wherein all of the branches are turned OFF, biasing voltages to the gates of the cascode transistors as well as the input transistors of all the branches may be set to zero volts (e.g., gates shorted to V.sub.GND) so long as the protection circuits do not couple the reference voltages to the branches.
(39) Furthermore, it should be noted that although in the exemplary configuration of FIG. 5A each (source node of a) common-gate cascode transistor of each branch is shown coupled to a respective protection circuit (510), according to some embodiments of the present disclosure, one or more, and not necessarily all, of the common-gate cascode transistors of each branch is coupled to a respective protection circuit (510). In general, the closer a common-gate cascode transistor is to the output (common drain node of all the output cascode transistors), the larger the AC component (e.g., V.sub.0) at the source node of such common-gate cascode transistor may be, and therefore, the more susceptible the corresponding transistor whose drain node is coupled to the source node of said common-gate cascode transistor may be to being subjected to higher voltage levels (and therefore requiring protection). It should also be noted that elements (switches, capacitors) of each protection circuit (510) may be sized according to the sizes of the transistors to which the protection circuit is coupled according to the description provided above with reference to FIGS. 3B-3C and FIGS. 4B-4C. Furthermore, it should be noted that although not shown in FIG. 5A, each protection circuit (510) may be coupled to a same or different supply voltages (e.g., V.sub.DD2 coupled to (410) of FIG. 4A), and may be controlled via control lines shared amongst the protection circuits (510) or via individual control lines to each of the control circuits (510).
(40) With continued reference to FIG. 5A, turning OFF of the cascode transistors (e.g., M22, . . . , M2n) of a turned OFF branch (e.g., M21, M2n) may be provided by a reference voltage (e.g., V.sub.DD2) coupled to a common node (e.g., N21, . . . , N2(n1)) of the branch (e.g., M21, . . . , M2n) through a respective protection circuit (510). In particular, a level of the reference voltage, V.sub.DD2, provided to the protection circuit (510) may be scaled according to a position of the common node, (e.g., N21, . . . , N2(n1)) in the stacked transistor configuration to which the protection circuit (510) is coupled. Applying the above teachings to the configuration of FIG. 5A, a person skilled in the art would clearly establish that a level of a reference voltage, V.sub.DD2k of a protection circuit (510k) that is coupled to a common node, N.sub.2k, of the branch (M21, . . . , M2n), can be provided by the expressions: V.sub.DS_M2k_MAX+V.sub.S_M2k>V.sub.DD2k>V.sub.G_M2(k+1) and V.sub.DG_M2k_MAX+V.sub.G_M2k>V.sub.DD2k, wherein: V.sub.DS_M2k_MAX and V.sub.DG_M2k_MAX, respectively, represent maximum values of tolerable drain-to-source and drain-to-gate voltage range of a transistor M2k whose drain node is coupled to the common node N.sub.2k; and V.sub.G_M2(k+1) represents a gate voltage (e.g., V.sub.Bias(k+1)) of a transistor M2(k+1) whose source node is coupled to the common node N.sub.2k.
(41) According to an exemplary embodiment of the present disclosure, the reference voltage to each of the protection circuits (510) of a branch of the configuration shown in FIG. 5A, can be provided by a resistive ladder network (Rk1, . . . , Rk(n1)) shown in FIG. 5B that is coupled between a reference voltage, V.sub.DD2, and the reference ground, V.sub.GND, wherein nodes of the resistive ladder network resistively divide the reference voltage, V.sub.DD2, to generate the reference voltages (V.sub.DD21, . . . , V.sub.DD2(n1)) provided to a respective protection circuit (510). As shown in FIG. 5B, the exemplary resistive ladder network may include a plurality of series connected resistors (Rk1, . . . , Rk(n1)) forming common nodes that may carry the reference voltages (V.sub.DD21, . . . , V.sub.DD2(n2)), and the reference voltage V.sub.DD2(n1) provided to the protection circuit (510) coupled to the output common-gate cascode transistor Mkn may be the reference voltage V.sub.DD2.
(42) FIG. 5C is a configuration of a multi-branch cascode amplifier (500C) according to an embodiment of the present disclosure comprising a plurality k of branches, (M11, . . . , M1n), . . . , and (Mk1, . . . , Mkn), each branch comprising a plurality of common-gate cascode transistors, (M12, . . . , M1n), . . . , and (Mk2, . . . , Mkn) and respective common-source (input) transistors M11, . . . , and Mk1. Furthermore, each branch may include respective one or more protection circuits (510) coupled to one or more of the common-gate cascode transistors of the branch. A person skilled in the art would understand that the configuration shown in FIG. 5C represents a generalization of the above teachings to a multi-branch amplifier having a generic number of branches, each branch having a generic number of cascode transistors. Accordingly, the person skilled in the art would clearly know how to apply the above teachings to the multi-branch cascode configuration (500C) of FIG. 5C.
(43) It should be noted that teachings according to the present disclosure may apply to multi-branch cascode amplifiers (e.g., per FIG. 5C) that are used as low-noise amplifiers (LNAs) in, for example, receiver sections of RF front-end modules. Furthermore, the present teachings may also be adapted for use as power amplifiers (PAs) in, for example, transmitter sections of RF front-end modules. In some cases, adapting of the multi-branch cascode amplifiers (e.g., per FIG. 5C) for use as PAs may include choosing different values of the gate capacitors (e.g., C.sub.Bn, C.sub.B(n1), . . . of FIG. 5C) coupled to the gates of the cascode transistors (e.g., M1n, M1(n1), . . . of FIG. 5C). According to some embodiments of the present disclosure, such choosing may be to provide a coupling of an RF signal at a source node of a cascode transistor of a branch (e.g., M1n, M1(n1), . . . , M11) to a corresponding gate node of the cascode transistor to control a division (distribution) of an RF voltage at an output node (e.g., drain of M1n of FIG. 5C) of the branch across the transistors of the branch.
(44) FIG. 6 is a process chart (600) showing various steps of a method for turning OFF a branch of a multi-branch cascode amplifier. As can be seen in the process chart (600), such method comprises: turning ON a plurality of branches of the multi-branch cascode amplifier by providing to each branch of the plurality of branches respective gate biasing voltages to a common-source input transistor and one or more common-gate cascode transistors of the branch for operation of the branch as an amplifier during a respective ON state of the branch, per step (610); turning OFF one branch of the plurality of branches by setting the biasing voltage of the common-source input transistor to the reference ground, V.sub.GND, and coupling a reference voltage to a source node of an output transistor of the branch so that a gate-to-source voltage of said output transistor is less than 0 Volts, per step (620); and maintaining a same biasing voltage of the respective gate biasing voltages to a gate of the output transistor of said branch during the ON state and the OFF state of the branch, per step (630).
(45) It should be noted that the various embodiments of the multi-branch amplifier circuits according to the present disclosure may be implemented as a monolithically integrated circuit (IC) according to any fabrication technology and process known to a person skilled in the art.
(46) Applications that may include the novel apparatus and systems of various embodiments include electronic circuitry used in high-speed computers, communication and signal processing circuitry, modems, single- or multi-processor modules, single or multiple embedded processors, data switches, and application-specific modules, including multilayer, multi-chip modules. Such apparatus and systems may further be included as sub-components within a variety of electronic systems, such as televisions, cellular telephones, personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (e.g., mp3 players), vehicles, medical devices (e.g., heart monitor, blood pressure monitor, etc.) and others. Some embodiments may include a number of methods.
(47) The term MOSFET technically refers to metal-oxide-semiconductor FET; another synonym for MOSFET is MISFET, for metal-insulator-semiconductor FET. However, MOSFET has become a common label for most types of insulated-gate FETs (IGFETs). Despite that, it is well known that the term metal in the names MOSFET and MISFET is now often a misnomer because the previously metal gate material is now often a layer of polysilicon (polycrystalline silicon). Similarly, the oxide in the name MOSFET can be a misnomer, as different dielectric materials are used with the aim of obtaining strong channels with smaller applied voltages. Accordingly, the term MOSFET as used herein is not to be read as literally limited to metal-oxide-semiconductor FET, but instead includes IGFETs in general.
(48) As should be readily apparent to one of ordinary skill in the art, various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice and various embodiments of the invention may be implemented in any suitable IC technology (including but not limited to MOSFET and IGFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, silicon-on-insulator (SOI), silicon-on-sapphire (SOS), GaN HEMT, GaAs pHEMT, and MESFET technologies. However, the inventive concepts described above are particularly useful with an SOI-based fabrication process (including SOS), and with fabrication processes having similar characteristics. Fabrication in CMOS on SOI or SOS enables low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (in excess of about 10 GHz, and particularly above about 20 GHz). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design.
(49) Voltage levels may be adjusted or voltage and/or logic signal polarities reversed depending on a particular specification and/or implementing technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, serially stacking components (particularly FETs) to withstand greater voltages, and/or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and/or to provide additional functions without significantly altering the functionality of the disclosed circuits.
(50) The examples set forth above are provided to give those of ordinary skill in the art a complete disclosure and description of how to make and use the embodiments of the present disclosure, and are not intended to limit the scope of what the applicant considers to be the invention. Such embodiments may be, for example, used within mobile handsets for current communication systems (e.g. WCDMA, LTE, WiFi, etc.) wherein amplification of signals with frequency content of above 100 MHz and at power levels of above 50 mW may be required. The skilled person may find other suitable implementations of the presented embodiments.
(51) Modifications of the above-described modes for carrying out the methods and systems herein disclosed that are obvious to persons of skill in the art are intended to be within the scope of the following claims. All patents and publications mentioned in the specification are indicative of the levels of skill of those skilled in the art to which the disclosure pertains. All references cited in this disclosure are incorporated by reference to the same extent as if each reference had been incorporated by reference in its entirety individually.
(52) It is to be understood that the disclosure is not limited to particular methods or systems, which can, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting. As used in this specification and the appended claims, the singular forms a, an, and the include plural referents unless the content clearly dictates otherwise. The term plurality includes two or more referents unless the content clearly dictates otherwise. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the disclosure pertains.
(53) A number of embodiments of the disclosure have been described. Nevertheless, it will be understood that various modifications can be made without departing from the spirit and scope of the present disclosure. Accordingly, other embodiments are within the scope of the following claims.
