NOISE SHAPER VARIABLE QUANTIZER

Abstract

A signal processing circuit includes a filter generating a quantizer input signal from a noise shaping input signal and a quantizer output signal. A quantizer divides the quantizer input signal by a scaling factor to produce a noise shaping output signal and multiplies the noise shaping output signal by the scaling factor to produce the quantizer output signal. Receiver circuitry scales the quantizer output signal by a second scaling factor. A dynamic range optimization circuit compares a current value of the noise shaping input signal to a threshold value, lowers or raises the scaling factor in response to the comparison, and proportionally lowers or raises the scaling factor such that a ratio between the scaling factor and second scaling factor remains substantially constant.

Claims

1. A signal processing circuit, comprising: a transmitter section including a noise shaper, the noise shaper comprising: a filter receiving a noise shaping input signal and a quantizer output signal, the filter configured to generate a quantizer input signal based at least upon the noise shaping input signal and the quantizer output signal; and a quantizer receiving the quantizer input signal and configured to divide the quantizer input signal by a first scaling factor to produce a noise shaping output signal, and to multiply the noise shaping output signal by the first scaling factor to product the quantizer output signal; a receiver section including: receiver circuitry receiving the noise shaping output signal, the receiver circuitry configured to scale the quantizer output signal by a second scaling factor; a dynamic range optimization circuit configured to: determine whether an absolute value of the noise shaping input signal is less than a threshold value; lower the first scaling factor in response to the absolute value of the noise shaping input signal being less than the threshold value; decrease the second scaling factor in response to the absolute value of the noise shaping input signal being less than the threshold value, proportionally to the lowering of the first scaling factor such that a ratio between the first scaling factor and the second scaling factor remains substantially constant.

2. The signal processing circuit of claim 1, wherein the noise shaping input signal represents audio data; and wherein the receiver section comprises: a current steering digital to analog converter (DAC) configured to generate an analog output signal from the noise shaping output signal by selectively connecting or disconnecting current sources and current sinks to differential outputs in response to the noise shaping output signal, the current sources and current sinks being scaled by the second scaling factor; a power amplifier configured to amplify the analog output signal; and a speaker driven by the analog output signal; wherein adjustment of the first scaling factor and the second scaling factor by the dynamic range optimization circuit proportionally to one another serves to prevent transients resulting from scaling factor adjustment from being present in the noise shaping output signal and therefore from causing audible pops to be played by the speaker.

3. The signal processing circuit of claim 1, wherein the dynamic range optimization circuit is further configured to increase the first scaling factor in response to the absolute value of the noise shaping input signal being greater than the threshold value and increase the second scaling factor in response to the absolute value of the noise shaping input signal being greater than the threshold value, proportionally to the increase in the first scaling factor such that the ratio between the first scaling factor and second scaling factor remains substantially constant.

4. The signal processing circuit of claim 1, further comprising a dither generator configured to generate a dither signal having a range defined by the first scaling factor; and wherein the transmitter section includes a summing circuit configured to inject the dither signal into the quantizer input signal prior to quantization thereof by the quantizer.

5. The signal processing circuit of claim 1, wherein the quantizer applies a truncation to the quantizer input signal after division thereof by the first scaling factor.

6. The signal processing circuit of claim 1, wherein the first scaling factor is a power of two.

7. The signal processing circuit of claim 1, wherein the quantizer input signal and quantizer output signal are digital; and wherein the quantizer is implemented digitally.

8. The signal processing circuit of claim 1, wherein the quantizer input signal and quantizer output signal are analog; and wherein the quantizer is implemented in an analog fashion, with the quantizer comprising: an analog to digital converter (ADC) receiving the quantizer input signal and digitizing the quantizer input signal to produce the noise shaping output signal such that it is scaled by the first scaling factor; and a digital to analog converter (DAC) receiving the noise shaping output signal and converting the noise shaping output signal to produce the quantizer output signal such that it is multiplied by the first scaling factor.

9. The signal processing circuit of claim 1, wherein the receiver section is implemented digitally.

10. The signal processing circuit of claim 1, wherein the receiver section is implemented in an analog fashion.

11. The signal processing circuit of claim 1, wherein the filter comprises: an input summer configured to subtract an error signal from the noise shaping input signal to produce the quantizer input signal; an error summer configured to subtract the quantizer input signal from the quantizer output signal to produce an intermediate output; and a noise shaping filter configured to apply a noise shaping filter function to the intermediate output to produce the error signal.

12. The signal processing circuit of claim 1, wherein the filter comprises: a sigma delta modulator receiving the noise shaping input signal and the quantizer output signal as output and applying a two-input one-output filtering thereto to produce the quantizer input signal.

13. The signal processing circuit of claim 12, wherein the two-input one-output filtering has a transfer function of:
Y(z)=L_0(z)U(z)L_1(z)V(z), with the noise shaping input signal being U(z) and the quantizer output signal being V(z).

14. The signal processing circuit of claim 1, wherein the absolute value of the noise shaping signal is determined from a current value of the noise shaping input signal.

15. A signal processing method, comprising: generating a quantizer input signal based at least upon a noise shaping input signal and a quantizer output signal; and dividing the quantizer input signal by a first scaling factor to produce a noise shaping output signal, and multiplying the noise shaping output signal by the first scaling factor to product the quantizer output signal; scaling the quantizer output signal by a second scaling factor; determining whether an absolute value of the noise shaping input signal is less than a threshold value; lowering the first scaling factor in response to the absolute value of the noise shaping input signal being less than the threshold value; and decreasing the second scaling factor in response to the absolute value of the noise shaping input signal being less than the threshold value, proportionally to the lowering of the first scaling factor such that a ratio between the first scaling factor and the second scaling factor remains substantially constant.

16. The method of claim 15, further comprising: generating an analog output signal from the noise shaping output signal by selectively connecting or disconnecting current sources and current sinks to differential outputs in response to the noise shaping output signal, the current sources and current sinks being scaled by the second scaling factor; amplifying the analog output signal; and driving a speaker with the analog output signal; wherein adjustment of the first scaling factor and the second scaling factor proportionally to one another serves to prevent transients resulting from scaling factor adjustment from being present in the noise shaping output signal and therefore from causing audible pops to be played by the speaker.

17. The method of claim 15, further comprising: increasing the first scaling factor in response to the absolute value being greater than the threshold value and increasing the second scaling factor in response to the absolute value being greater than the threshold value, proportionally to the increase in the first scaling factor such that the ratio between the first scaling factor and second scaling factor remains substantially constant.

18. The method of claim 15, further comprising generating a dither signal having a range defined by the first scaling factor; and injecting the dither signal into the quantizer input signal prior to quantization thereof.

19. The method of claim 15, further comprising applying a truncation to the quantizer input signal after division thereof by the first scaling factor.

20. The method of claim 15, wherein the first scaling factor is a power of two.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0028] FIG. 1 is a block diagram of a first known noise shaping quantizer.

[0029] FIG. 2 is a block diagram of a second known noise shaping quantizer.

[0030] FIG. 3 includes a series of graphs showing values of signals in an audio playback circuit utilizing the known noise shaping quantizer of FIG. 2 while performing audio signal scaling at the noise shaper input, compensating it into the receiver and into the noise shaper filter memory, with the occurrence of pop due to the audio signal scaling being visible.

[0031] FIG. 4 is a block diagram of a first noise shaping variable quantizer broadly described herein.

[0032] FIG. 5 is a block diagram of a first noise shaping variable quantizer broadly described herein, with dither that is scaled together with quantization.

[0033] FIG. 6 is a graph showing how the probability distribution of the dither injected into the signal in the noise shaping variable quantizer of FIG. 5 changes during operation with the scaling of the quantization.

[0034] FIG. 7 is a block diagram showing an embodiment of the quantizer of FIG. 5 in which the dither is subtracted prior to production of the quantizer output.

[0035] FIG. 8 is a block diagram showing an embodiment of the quantizer of FIG. 4 in which dither is not injected.

[0036] FIG. 9 is a block diagram showing an embodiment of the quantizer of FIG. 5 in which the quantizer is digital.

[0037] FIG. 10 is a block diagram showing an embodiment of the quantizer of FIG. 5 in which the quantizer is analog.

[0038] FIG. 11 is a schematic block diagram showing specifics of the ADC and DAC of the analog quantizer of FIG. 10 for use with a digital receiver section.

[0039] FIG. 12A is a schematic block diagram showing first possible specifics of the ADC and DAC of the analog quantizer of FIG. 10 for use with an analog receiver section.

[0040] FIG. 12B is a schematic block diagram showing second possible specifics of the ADC and DAC of the analog quantizer of FIG. 10 for use with an analog receiver section.

[0041] FIG. 13 is a block diagram showing an embodiment of noise shaping variable quantizer described herein where the quantizer is digital and the receiver section is analog.

[0042] FIG. 14 is a schematic block diagram of the current steering DAC of FIG. 13.

[0043] FIG. 15 is a block diagram showing an embodiment of a noise shaping variable quantizer described herein where the quantizer is digital and the receiver section is digital as well.

[0044] FIG. 16 is a block diagram showing an embodiment of a noise shaping variable quantizer described herein where the quantizer is analog and the receiver section is digital.

[0045] FIG. 17 is a block diagram showing an embodiment of a noise shaping variable quantizer described herein where the quantizer and the receiver section are both analog.

[0046] FIG. 18 is a block diagram showing the noise shaping filter of a digital quantizer described herein, the noise shaping filter utilizing error feedback.

[0047] FIG. 19 is a block diagram showing the noise shaping filter of an analog quantizer described herein, the noise shaping filter utilizing error feedback.

[0048] FIG. 20 is a block diagram showing the noise shaping filter of a digital quantizer described herein, the noise shaping filter utilizing sigma delta modulation.

[0049] FIG. 21 is a block diagram showing the noise shaping filter of an analog quantizer described herein, the noise shaping filter utilizing sigma delta modulation.

[0050] FIG. 22 is a schematic block diagram of a digital audio playback circuit described herein utilizing a digital noise shaping variable quantizer with error based feedback.

[0051] FIG. 23 includes a series of graphs showing values of signals in the digital audio playback circuit of FIG. 22 during operation.

[0052] FIG. 24 is a block diagram of an analog to digital audio conversion circuit described herein.

DETAILED DESCRIPTION

[0053] The following disclosure enables a person skilled in the art to make and use the subject matter disclosed herein. The general principles described herein may be applied to embodiments and applications other than those detailed above without departing from the spirit and scope of this disclosure. This disclosure is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed or suggested herein.

[0054] A. Broad Concept and Associated Embodiment

[0055] Now described herein with initial reference to FIG. 4 is a sample signal processing chain 20 including a transmitter section (e.g., a noise shaping quantizer) 21 and a receiver section 35 (e.g., a digital to analog converter, DAC). The transmitter section 21 may be analog or digital, and the receiver section 35 may be analog or digital.

[0056] Described now is a generic case, applicable to both analog and digital implementations. The noise shaping quantizer 21 includes a noise shaping filter 23 that receives a noise shaping input signal nsh.sub.in. The noise shaping filter 23 performs filtering and utilizes error feedback to produce a quantizer input signal quantizer.sub.input. A quantizer 24 receives the quantizer input signal quantizer.sub.input and, under control of a dynamic range optimization circuit (DYRO control circuit) 34 as will be explained below, performs noise shaping and on-the-fly scaling on the noise shaping input signal nsh.sub.in to produce a noise shaped output signal nsh.sub.out.

[0057] The quantizer input signal quantizer.sub.input is divided by an adjustable factor (e.g., a scaling factor) in a divider 26. A truncation circuit 27 operates on the output of the divider 26, resulting in data loss, for example by rounding, saturation, or introducing of other non-linearities, producing the noise shaping output signal nsh.sub.out. A feedback multiplier 28 multiplies the noise shaping output signal nsh.sub.out by the same adjustable factor to produce a quantizer output signal quantizer.sub.output provided to the noise shaping filter 23 for use in performing noise shaping. The receiver section 35 multiplies the noise shaping output signal nsh.sub.out by another adjustable factor (e.g., a scaling factor) to produce an output signal OUT. The adjustable factor and adjustable factor may also be referred to as scaling factors herein. The different potential valuables of the adjustable factors and may be represented by an index k, for example, .sub.k and .sub.k.

[0058] The DYRO control circuit 34 monitors the noise shaping input signal nsh.sub.in and based upon the amplitude thereof, adjusts the adjustable factor and the adjustable factor on the fly so as to balance output signal OUT swing with its quantization noise, as will be described below, with such adjusting maintaining the ratio / as being a fixed constant.

[0059] There are physical limits to the divider 26 and the feedback multiplier 28, as well as to the receiver section 35, that limits the output signal OUT swing. To work within these constraints, the DYRO control circuit 34 compares the noise shaping input signal nsh.sub.in to a series of accurately defined thresholds, and sets the adjustable factor and the adjustable factor on the fly based upon those comparisons.

[0060] In detail, and may each take one of i different values. As a first order approximation, the following relationship is present:

[00001]$\frac{ns{h}_{in}}{{}_i}ns{h}_{out}.$

[0061] For a given maximum value of the absolute value of the noise shaping output signal nsh.sub.out, denoted as nsh.sub.out.sub.max (which is set by limits inherent to the implementation of the quantizer 24), the following relationship is therefore present:

nsh.sub.in.sub.max(i)nsh.sub.out.sub.max.Math..sub.i.

[0062] nsh.sub.in.sub.max(i) is therefore the maximum of the absolute value of the noise shaping input nsh.sub.in at the value of .sub.i.

[0063] Assume, as an example, that i=1, . . . , 3. Therefore, .sub.i=[.sub.1; .sub.2; .sub.3], with .sub.1>.sub.2>.sub.3, and at =[.sub.1; .sub.2; .sub.3], with .sub.1>.sub.2>.sub.3, and with those values being such that / remains a fixed constant. Given the example value of i=1, . . . ,3 the thresholds are therefore TH.sub.i=[TH.sub.1, TH.sub.2, and TH.sub.3], with TH.sub.1>TH.sub.2>TH.sub.3. In general, the greater the adjustable factors and , the greater the output signal OUT swing but also the greater the quantization noise. Conversely, the lesser the adjustable factors and , the lesser the output signal OUT swing and the lesser the quantization noise.

[0064] During operation, the DYRO control circuit 34 compares the current value (e.g., a current value) of the noise shaping input signal nsh.sub.in to the thresholds TH.sub.1, TH.sub.2, and TH.sub.3. If the noise shaping input signal nsh.sub.in is greater than TH.sub.1, then the adjustable factors are set by the DYRO control circuit 34 as follows:

=.sub.1 and =.sub.1.

[0065] If the noise shaping input signal nsh.sub.in is greater than TH.sub.2 but less than TH.sub.1, then the adjustable factors are set by the DYRO control circuit 34 as follows:

=.sub.2 and =.sub.2.

[0066] If the noise shaping input signal nsh.sub.in is greater than TH.sub.3 but less than TH.sub.2, then the adjustable factors are set by the DYRO control circuit 34 as follows:

=.sub.3 and =.sub.3.

[0067] If i were to be greater than 3, then additional thresholds and adjustable factors would be present, and further comparisons consistent with the above described comparisons would be performed.

[0068] The result of this above-described operation is that the quantizer output quantizer.sub.output will practically have the same amplitude as the quantizer quantizer.sub.input while the quantization noise will be reduced.

[0069] These comparison and adjustable factor setting operations are performed continuously or periodically on the noise shaping input signal nsh.sub.in, and therefore the adjustment of the adjustable factors and is performed continuously or periodically. The result of this is that the output signal OUT will practically have the same amplitude while quantization noise present at the receiver section 35 OUT will be reducedthus, dynamic range at OUT is increased.

[0070] In some implementation instances, the DYRO control circuit 34 may implement a margin in its thresholds and therefore in its threshold comparisons. The margin value is greater than zero but less than one. The thresholds can be calculated as:

th(i)=nsh.sub.in.sub.max(i)nsh.sub.out.sub.max.Math..sub.i.Math.margin(i).

[0071] Time filtering may be performed on the threshold comparisons by the DYRO control circuit 34 in the falling direction. In the falling direction (such as when the noise shaping input signal nsh.sub.in was previously greater than TH.sub.1, but is now less than TH.sub.1 and greater than TH.sub.2) for example, the DYRO control circuit 34 may wait to take action to change the adjustable factor and the adjustable factor until after the noise shaping input signal nsh.sub.in has fallen below and remained below the threshold in question (e.g., has fallen below TH.sub.1) for a given period of time. Such time filtering may optionally be performed in the rising direction (such as when the noise shaping input signal nsh.sub.in was previously less than TH.sub.1 and greater than TH.sub.2, but is now greater than TH.sub.1) as well, although this may not be desired in some situations.

[0072] Further details of the principles of operation of the DYRO control circuit 34 may be found in U.S. Pat. No. 7,239,258, incorporated by reference above.

[0073] B. Dither

[0074] Optionally, as shown in the embodiment of FIG. 5, the dither signal dither_in is generated by a dither circuit 38 under control of the DYRO control circuit 34 according to changes made to the adjustable factor . Dithering prevents correlation between the quantization noise and the desired information represented by the output signal OUT.

[0075] In instances where the quantizer 24 is digital, the injected dither may have a triangular probability distribution function as shown in FIG. 6, with the specific shape of the probability distribution function changing with . Details of this type of dithering may be found in Digital Dither, S. P. Lipshitz and, J. Vanderkooy, In Audio Engineering Society Convention 81, November 1986, the contents of which are incorporated by reference in their entirety.

[0076] The injected dither may instead have a rectangular probability function, also in instances where the quantizer 24 is digital. In instances where the quantizer 24 is analog, the dither circuit 38, under control of the DYRO control circuit 34, may supply the dither signal dither_in as two random analog values.

[0077] In the example generic quantizer 24 described above, the dither signal dither_in is injected to the quantizer input quantizer.sub.input prior to operation thereon by the divider 26, but is not subtracted from the quantizer output quantizer.sub.output. However, as shown in the example of FIG. 7, the quantizer 24 may include a subtractor 24 that subtracts the dither signal dither_in from the quantizer output quantizer.sub.output.

[0078] The dither signal dither_in in embodiments in which the quantizer 24 is digital, the dither signal may be generated through the sum of two linear feedback shift registers (LFSRs), or as the sum of two separated branches of a single LFSR. The dither signal may be generated through any suitable circuit, and may take any suitable form.

[0079] In the above example generic quantizer 24, dither is injected. However, as shown in FIG. 8, the quantizer 24 may not include dither injection, and the quantizer input quantizer.sub.input may be directly fed to the divider 26.

[0080] C. Quantizer Types

[0081] In the above example, the transmitter section 21 is described generically, and such description of operation applies to either an analog or a digital transmitter section. Also in the above example, the receiver section 35 is described generically, and such description of operation applies to either an analog or digital receiver section 35. With this being said, specific examples will be provided below, in which: [0082] 1. The transmitter section 21 is digital and the receiver section 35 is analog; [0083] 2. The transmitter section 21 is digital and the receiver section 35 is digital; [0084] 3. The transmitter section 21 is analog and the receiver section 35 is digital; and [0085] 4. The transmitter section 21 is analog and the receiver section 35 is analog.

[0086] Each of these will be described, but first, digital and analog quantizers for use therein will be described. Note that any digital functions or components described herein may be incorporated within a microprocessor, digital signal processor, or programmable logic device, and any analog functions or components described herein may be incorporated within discrete analog components.

[0087] A sample digital quantizer 24 is shown in FIG. 9 and has the structure and function of the digital quantizer 24 described above. In this sample digital quantizer 24, the adjustable factor is equal to 2.sup., and therefore the divider 26 performs a division of the quantizer input quantizer.sub.input (after dither injection) 2.sup., while the feedback multiplier 28 multiplies the noise shaping output nsh.sub.out by 2.sup.. Here, the data loss function 27 may be a round, floor, or ceiling function, for example. Note that it is possible in a digital implementation of the quantizer 24 for the adjustable factor to instead be implemented as a ratio of two integers or as a floating point value, depending upon hardware.

[0088] A sample generic analog quantizer 24 is shown in FIG. 10. The analog quantizer 24 includes a summer 25 through which an analog dither signal dither_in is injected into the analog quantizer input signal quantizer.sub.input prior to analog to digital conversion by an analog to digital converter (ADC) 26. During the analog to digital conversion, an effective division of the quantizer input signal quantizer.sub.input by the adjustable factor is performed. The output of the ADC 26 is the noise shaping output nsh.sub.out. A digital to analog converter (DAC) 28 converts the noise shaping output nsh.sub.out back to analog form, and performs an effective multiplication of the noise shaping output nsh.sub.out by the adjustable factor to produce an analog quantizer output signal quantizer.sub.output.

[0089] One potential implementation of the analog quantizer 24 which is intended for use with a digital receiver section 35 is shown in FIG. 11. In this implementation, the ADC 26 is arranged to be used to generate k thresholds for use in analog to digital conversion. To that end, a resistor ladder is connected between a positive voltage +V.sub. and a negative voltage V.sub., with these voltages having equal and opposite magnitudes set as a function of the current value of the adjustable factor . The voltage ladder is formed by m resistors (m being equal to 2k+1) connected in series between +V.sub. and V.sub., and generates k positive threshold voltages and k negative threshold voltages. The magnitudes of the threshold voltages can be represented as:

[00002]$V_{t{h}_i}=\frac{2i-1}{m-1}.Math.V_{},\mathrm{where}i=1,.Math.,\frac{m-1}{2}$

[0090] As illustrated, threshold voltages VTH1, . . . , VTHk and VTH1, . . . , VTHk are generated at taps between the resistors of the voltage ladder. The resistor directly connected to +V.sub. has a resistance of R.sub.T/2, as does the resistor directly connected to V.sub.. The remainder of the resistors each have a resistance of R.sub.T.

[0091] The ADC 26 in this analog quantizer 24 shown in FIG. 11 includes 2k comparators, here shown as comparators 41(1), . . . , 41(2k), providing output to 2k flip flops, here shown as flip flops 42(1), . . . , 42(2k). The flip flops 42(1), . . . , 42(2k) provide their outputs as selection signals to 2k switch circuits, here shown as switch circuits 44(1), . . . , 44(2k).

[0092] The comparators 41(1), . . . , 41(2k) each have a non-inverting input terminal coupled to receive the quantizer input signal quantizer.sub.input, which is an analog voltage V.sub.quantizer_in in this instance. The comparators 41(1), . . . , 41(2k) have respective inverting input terminals connected to different ones of the threshold voltages VTH1, . . . , VTHk and VTH1, . . . , VTHk. In the illustrated example, comparator 41(1) has its inverting input terminal connected to the threshold voltage VTHk, comparator 41(2) has its inverting input terminal connected to the threshold voltage VTH1, comparator 41(3) has its inverting input terminal connected to the threshold voltage VTH1, and comparator 41(2k) has its inverting input terminal connected to the threshold voltage VTHk. The flip flop 42(1) has its input receiving the output of the comparator 41(1) and has its output connected to provide a selection signal to the switch circuit 44(1), the flip flop 42(2) has its input receiving the output of the comparator 41(2) and has its output connected to provide a selection signal to the switch circuit 44(2), flip flop 42(3) has its input receiving the output of the comparator 41(3) and has its output connected to provide a selection signal to the switch circuit 44(3), and flip flop 42(2k) has its input receiving the output of the comparator 41(2k) and has its output connected to provide a selection signal to the switch circuit 44(2k).

[0093] Each switch circuit 44(1), . . . , 44(2k) operates to selectively connect an associated resistor (each such resistor having a resistance of R1) between either +V.sub. or V.sub. and an inverting input terminal of an amplifier 45, under control of the output of a respective flip flop 42(1), . . . , 42(2k). When the output of a respective flip flop 42(1), . . . , 42(2k) is asserted, the associated switch circuit 44(1), . . . , 44(2k) connects its respective resistor to V.sub. and otherwise connects its respective resistor to V.sub..

[0094] The amplifier 45 has its non-inverting input terminal grounded, and a resistor R2 is connected between the inverting input terminal and output of the amplifier 45. The output of the amplifier 45 is the quantizer output quantizer.sub.output, which is an analog voltage V.sub.quantizer_out in this instance.

[0095] The relationship in resistance value between R1 and R2 is as follows:

R1=(m1).Math.R2

[0096] The output of each flip flop 42(1), . . . , 42(2k) is also connected to circuit 46 (illustratively a thermometric to signed converter 46 that generates the noise shaping output nsh.sub.out in digital form therefrom).

[0097] As stated, the voltages +V.sub. and V.sub. are based upon the adjustable factory. For example, the voltages +V.sub. and V.sub. may be generated by a programmable voltage generator, with V.sub. depending on the adjustable factor (e.g., where the adjustable factor changes from 1 to 2, V.sub. changes from V.sub.1 to V.sub.2).

[0098] As another example, the ADC 26 and DAC 28 may be integrated within a noise shaper utilizing either an error feedback or sigma-delta modulator arrangement.

[0099] A first potential implementation of the analog quantizer 24 which is intended for use with an analog receiver section 35 is shown in FIG. 12A. The difference in this analog quantizer 24 over that shown in FIG. 11 is that the converter 46 in this instance includes 2k switch circuits 47(1), . . . , 47(2k) respectively connected to receive the outputs of flip flops 42(1), . . . , 42(2k) as respective selection signals. The output of the flip flops 42(1), . . . , 42(2k) here forms the noise shaping output nsh.sub.out.

[0100] Each switch circuit 47(1), . . . , 47(2k) operates to selectively connect an associated resistor (each such resistor having a resistance of R3) between either +V.sub. or V.sub. and a non-inverting input terminal of an amplifier 48, under control of the output of a respective flip flop 42(1), . . . , 42(2k). When the output of a respective flip flop 42(1), . . . , 42(2k) is asserted, the associated switch circuit 47(1), . . . , 47(2k) connects its respective resistor to V.sub. and otherwise connects its respective resistor to V.sub..

[0101] The voltages +V.sub. and V.sub. are based upon the adjustable factor . For example, the voltages +V.sub. and V.sub. may be generated by a programmable voltage generator, with V.sub. depending on the adjustable factor (e.g., where the adjustable factor changes from 1 to 2, V.sub. changes from V.sub.1 to V.sub.2).

[0102] The amplifier 48 has its non-inverting input terminal grounded, and a resistor R4 is connected between the inverting input terminal and output of the amplifier 48. The output of the amplifier 48 may be used for desired purposes.

[0103] The relationship in resistance value between R3 and R4 is as follows:

R3=(m1).Math.R4

[0104] A second potential implementation of the analog quantizer 24 is shown in FIG. 12B. The difference here is that the noise shaping output nsh.sub.out is produced at the output of the amplifier 48 as an analog voltage to be fed to the receiver 35, and here the receiver 35 is not scaled by the adjustable factor because that scaling is performed by the converter 46.

[0105] D. Digital Transmitter Section, Analog Receiver Section A signal processing chain 100 is shown in FIG. 13 which includes a noise shaping digital quantizer as a digital transmitter section 22 and an analog receiver section 35. The noise shaping digital quantizer 2 operates as described above with reference to FIGS. 4, 5, and 9 and needs no further description herein.

[0106] The analog receiver section 35 includes a current steering DAC 150 that converts the noise shaping output signal nsh.sub.out to produce an analog output signal A.sub.out. The current steering DAC 150 includes a thermometric code conversion circuit that selects elementary contributions to the analog output signal A.sub.out that are scaled by the adjustable factor . A low pass filter 151 filters quantization noise from the analog output signal A.sub.out, and the analog output signal A.sub.out is then amplified by a power amplifier 152 that drives a speaker 153 or other output device.

[0107] An example implementation of the current steering DAC 150 is now described with additional reference to FIG. 14. The DAC 150 may be any suitable type of DAC, however, as an example, the illustrated DAC 150 is a current steering DAC that receives the noise shaping output signal nsh.sub.out as input.

[0108] The DAC 150 provides differential current outputs generated by N=2.sup.n respective current sources and current sinks that are selectively connected to the input by switches based upon the noise shaping output signal nsh.sub.out, with n being, for example, 6 such that 2.sup.n=64. The current sources and current sinks each respectively source or sink a current Iref having a same magnitude multiplied by . Stated differently, these currents are equal and each changed in magnitude proportionally to the current reference.

[0109] For example, where n=6, and therefore, N=2.sup.6=64, there are 64 current sources and 64 current sinks in the DAC 150. The current sources are labeled in FIG. 14 as sourcing currents .Math.Iref.sub.1, . . . , .Math.Iref.sub.N and the current sinks are labeled in FIG. 14 as sinking currents .Math.Iref.sub.1, . . . , .Math.Iref.sub.N.

[0110] E. Digital Transmitter Section, Digital Receiver Section A signal processing chain 100 is shown in FIG. 15 which includes a noise shaping digital quantizer 24 as a digital transmitter section 22 and a digital receiver section 35. The noise shaping digital quantizer 2 operates as described above with reference to FIGS. 4, 5, and 9 and needs no further description herein.

[0111] The digital receiver section 35 includes a scaling circuit 154 that scales the noise shaping output nsh.sub.out by to produce a digital output signal D.sub.out. The digital output signal D.sub.out is thereafter passed through a decimating low-pass filter 155 and then a digital elaboration circuit 156.

[0112] F. Analog Transmitter Section, Digital Receiver Section

[0113] A signal processing chain 101 is shown in FIG. 16 which includes an analog quantizer 24 as an analog transmitter section 22 and a digital receiver section 35. The analog quantizer 24 operates as described above with reference to FIGS. 10, 11, 12 and needs no further description herein.

[0114] The digital receiver section 35 includes a scaling circuit 154 that multiplies the noise shaping output nsh.sub.out by (with 1 or <1) to produce a digital output signal D.sub.out. The digital output signal D.sub.out is thereafter passed through a decimating low-pass filter 155 and then a digital elaboration circuit 156.

[0115] G. Analog Transmitter Section, Analog Receiver Section

[0116] A signal processing chain 101 is shown in FIG. 17 which includes an analog quantizer 24 as an analog transmitter section 22 and an analog receiver section 35. The analog quantizer 24 operates as described above with reference to FIGS. 10, 12 and needs no further description herein.

[0117] The analog transmitter section 22 operates as described above with reference to FIG. 12 and needs no further description herein.

[0118] H. Noise Shaping Filter Specifics

[0119] The noise shaping filter 23 used in the above-described embodiments may utilize error feedback or sigma-delta modulation.

[0120] Now described with reference to FIG. 18 is an embodiment of the noise shaping filter 23 utilizing error feedback and designed to work with a digital quantizer 24. The noise shaping filter 23 includes an input summer 23a that subtracts an error signal err output by a noise shaping filter 23c from the noise shaping input signal nsh.sub.in to produce the quantizer input quantizer.sub.input. The digital quantizer 24 injects the dither signal dither_in to the quantizer input quantizer.sub.input and divides the quantizer input quantizer.sub.input by the adjustable factor (which in this instance may be .sup.), with that result being truncated such as by a rounding, floor, or ceiling function to produce the noise shaping output signal nsh.sub.out. The digital quantizer 24 multiplies the noise shaping output signal nsh.sub.out to produce the quantizer output quantizer.sub.output. An error summer 23b subtracts the quantizer input quantizer.sub.input from the quantizer output quantizer.sub.output and provides the result to the noise shaping filter 23c which has a transfer function of H(z). The noise shaping filter 23c produces the error signal err as output.

[0121] The above-described error feedback arrangement may also be used with an analog quantizer 24, as shown in FIG. 19, and operating as described above with reference to FIG. 18.

[0122] Now described with reference to FIG. 20 is an embodiment of the noise shaping filter 23 in which the noise shaping filter is implemented as a sigma-delta modulator 23a, and designed to work with a digital quantizer 24. The sigma-delta modulator 23a includes a U-input (L.sub.0) that receives the noise shaping input nsh.sub.in and a V-input (L.sub.1) that receives the quantizer output quantizer.sub.output and the output of the sigma-delta modulator 23a is the quantizer input quantizer.sub.input. The sigma-delta modulator 23a applies a two-input, one output filtering according to the equation Y(z)=L.sub.0(z)U(z)L.sub.1(z)V(z). The quantizer input quantizer.sub.input may be produced as a digital signal for use with the digital quantizer 24 (FIG. 20), or may be produced as an analog signal for use with the analog quantizer 24 (FIG. 21).

[0123] Sample sigma-delta modulator designs such as may be used in the embodiment of FIG. 20 may be found in Understanding Delta-Sigma Delta Data Converters, Pavan, Shanthi; Schreir, Richard; Temes, Gabor C., IEEE Press Series on Microelectronic Systems, IEEE 2017, the contents of which are incorporated by reference.

[0124] I. Audio Output Circuit with Digital Transmitter Section, Analog Receiver Section

[0125] Now described with reference to FIG. 22 is a signal processing chain 100 utilized as an audio output circuit. In this signal processing chain 100, the transmitter section 21 includes a digital quantizer 24 and error feedback based noise shaping circuit 23 as described above, and the receiver section includes a current steering DAC 150 as described above

[0126] During operation, the DYRO control circuit 14 compares the values of the noise shaping input nsh.sub.in to a series of thresholds, and based thereupon, adjusts the adjustable factor and the adjustable factor on the fly, with such adjusting maintaining the ratio / as being a fixed constant. and may each take one of i different values, and in this embodiment, =2.sup..

[0127] The thresholds for this example will now be discussed. Assume here that the noise shaping filter 23c is a finite impulse response filter with coefficients fircoeff.sub.k. The relationship between the maximum noise shaping input nsh.sub.in.sub.max and the maximum noise shaping output nsh.sub.out.sub.max can be mathematically represented as:

[00003]$\frac{\begin{array}{c}{\mathrm{nsh}}_{i{n}_{\max }}+\left({}_{k=1}^{N\mathrm{umCoeffs}}.Math.{\mathrm{fircoeff}}_k.Math.\right).Math.\\ \left(\frac{1}{2}{2}^{{}_i}+{\mathrm{dither\_max}}_i\right)+{\mathrm{dither\_max}}_i\end{array}}{2^{{}_i}}={\mathrm{nsh}}_{ou{t}_{\max }}$

[0128] An expression factor.sub.i may be written as:

[00004]${\mathrm{factor}}_i=\left({.Math.}_{k=1}^{\mathrm{NumCoeffs}}.Math.{\mathrm{fircoeff}}_k.Math.\right).Math.\left(\frac{1}{2}{2}^{{}_i}+{\mathrm{dither\_max}}_i\right)+{\mathrm{dither\_max}}_i$

[0129] Therefore, nsh.sub.in.sub.max(i) can be written as:

nsh.sub.in.sub.max(i=(2.sup..sup.i.Math.nsh.sub.out.sub.max)factor.sub.i

[0130] The thresholds can then be set as follows, assuming margin is used:

th(i)=nsh.sub.in.sub.max(i).Math.margin(i)=[(2.sup..sup.i.Math.nsh.sub.out.sub.max)factor.sub.i].Math.margin(i)

[0131] Example operation is now described with additional reference to FIG. 23. Assume in this case that the noise shaping input signal nsh.sub.in is 24 bit, and the noise shaping output signal nsh.sub.out is 7 bit. Initially, assume the adjustable factor to be set to:

=2.sup.=2.sup.17

[0132] Assume the current reference I.sub.ref used by the DAC 15 is 1 A. Prior to time T1, the input audio signal i_audio (which is interpolated to produce the noise shaping input nsh.sub.out) is playing audio and not muted. At time T1, the input audio signal i_audio is muted, and the noise shaping at the output nsh.sub.out of the noise shaping circuit 23 can be observed between times T1 and T2. The quantization noise prior to filtering within the noise shaping circuit 23 can be observed between times T1 and T2 as o_prefilt, and after filtering can observed between times T1 and T2 as o_filt.

[0133] At time T2, nsh.sub.in is below the first threshold for the given period of time, and therefore the is reduced to 16 by the DYRO control circuit 14, so the adjustable factor is set such that:

=2.sup.=2.sup.16

[0134] Since is being reduced by one, the DYRO control circuit 14 adjusts the reference current I.sub.ref within the DAC 14 accordingly by properly scaling (keeping in mind that / remains as a fixed constant), which in this case yields a reduction in the reference current .Math.I.sub.ref from 1 A to A. The reduction of the quantization noise prior to filtering within the noise shaping circuit 23 can be observed between times T2 and T3 as o_prefilt, and after filtering can observed between times T2 and T3 as o_filt.

[0135] At time T3, nsh.sub.in is below the second threshold (which is lower than the first threshold), and therefore is reduced to 15 by the DYRO control circuit 14. Since the adjustable factor is being reduced by one, the DYRO control circuit 14 adjusts the reference current .Math.I.sub.ref within the DAC 14 accordingly, which in this case is a reduction from A to A. The further reduction of the quantization noise prior to filtering within the noise shaping circuit 23 can be observed after time T3 as o_prefilt, and after filtering can observed after time T3 as o_filt.

[0136] Observe that at the changing of the adjustable factor at times T2 and T3, there is no occurrence of a transient disturbance which would manifest as an audible pop.

[0137] Although not expressly shown on in the graph of FIG. 23, note that the dither is adjusted according to the adjustable factor . For example, according to this specific embodiment where =2.sup., the dither range may be from [2.sup., 2.sup.62], with a triangular probability distribution, and with being changed as the adjustable factor is changed.

[0138] J. Audio Sampling Embodiment

[0139] The above dynamic range expansion performed through the use of variable scaling of re-quantization during digital to analog conversion is equally applicable to analog to digital conversion. To that end, an embodiment of an audio sampling circuit 200 using variable scaling of re-quantization during analog to digital conversion is now described with reference to FIG. 24.

[0140] The audio sampling circuit 200 includes a microphone 201 receiving input sound waves and converting them to an analog audio signal, which is then preconditioned by a preconditioning amplifier 202 to produce an analog audio input signal A.sub.in. The preconditioning amplifier 202 may have a low-pass filtering behavior because the noise shaping input signal nsh.sub.in is within a limited bandwidth range. A noise shaping converter 203, here a sigma-delta based analog to digital converter controlled based upon the adjustable factor , receives the analog audio input signal A.sub.in and digitizes the analog audio input signal A.sub.in to produce the noise shaping input signal nsh.sub.in, which is then compensated by a compensation circuit 204 according to the adjustable factor , and in turn decimated by a decimation filter 205 to produce output that may be used for suitable purposes, for example by a digital elaboration unit for further processing, for example in a wave file writing system. The DYRO control circuit 206 operates as described above, comparing the analog input signal A.sub.in to the thresholds and adjusting the adjustable factors and accordingly.

[0141] It is clear that modifications and variations may be made to what has been described and illustrated herein, without thereby departing from the scope of this disclosure, as defined in the annexed claims.

[0142] While the disclosure has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of this disclosure, will appreciate that other embodiments can be envisioned that do not depart from the scope of the disclosure as disclosed herein. Accordingly, the scope of the disclosure shall be limited only by the attached claims.